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| author | Piotr Sobczak <piotr.sobczak@amd.com> | 2019-04-05 07:44:09 +0000 | 
|---|---|---|
| committer | Piotr Sobczak <piotr.sobczak@amd.com> | 2019-04-05 07:44:09 +0000 | 
| commit | 0376ac1d946466eb346c2055554153e11b0fc3cf (patch) | |
| tree | a9e134c70ee7634941c786dd42ef32e5d0fb12c6 /llvm/lib/CodeGen/SelectionDAG | |
| parent | 94cd06676349f034f005b3284fc161d96baadbea (diff) | |
| download | bcm5719-llvm-0376ac1d946466eb346c2055554153e11b0fc3cf.tar.gz bcm5719-llvm-0376ac1d946466eb346c2055554153e11b0fc3cf.zip | |
[SelectionDAG] Compute known bits of CopyFromReg
Summary:
Teach SelectionDAG how to compute known bits of ISD::CopyFromReg if
the virtual reg used has one def only.
This can be particularly useful when calling isBaseWithConstantOffset()
with the ISD::CopyFromReg argument, as more optimizations may get enabled
in the result.
Also add a missing truncation on X86, found by testing of this patch.
Change-Id: Id1c9fceec862d118c54a5b53adf72ada5d6daefa
Reviewers: bogner, craig.topper, RKSimon
Reviewed By: RKSimon
Subscribers: lebedev.ri, nemanjai, jvesely, nhaehnle, javed.absar, jsji, jdoerfert, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59535
llvm-svn: 357745
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 20 | 
1 files changed, 20 insertions, 0 deletions
| diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 87ace6f66b0..148a3805b3b 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -31,6 +31,7 @@  #include "llvm/CodeGen/MachineFrameInfo.h"  #include "llvm/CodeGen/MachineFunction.h"  #include "llvm/CodeGen/MachineMemOperand.h" +#include "llvm/CodeGen/MachineRegisterInfo.h"  #include "llvm/CodeGen/RuntimeLibcalls.h"  #include "llvm/CodeGen/SelectionDAGAddressAnalysis.h"  #include "llvm/CodeGen/SelectionDAGNodes.h" @@ -3202,6 +3203,25 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,      Known.One &= Known2.One;      break;    } +  case ISD::CopyFromReg: { +    auto R = cast<RegisterSDNode>(Op.getOperand(1)); +    const unsigned Reg = R->getReg(); + +    const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); +    if (!TRI->isVirtualRegister(Reg)) +      break; + +    const MachineRegisterInfo *MRI = &MF->getRegInfo(); +    if (!MRI->hasOneDef(Reg)) +      break; + +    const FunctionLoweringInfo::LiveOutInfo *LOI = FLI->GetLiveOutRegInfo(Reg); +    if (!LOI || LOI->Known.getBitWidth() != BitWidth) +      break; + +    Known = LOI->Known; +    break; +  }    case ISD::FrameIndex:    case ISD::TargetFrameIndex:      TLI->computeKnownBitsForFrameIndex(Op, Known, DemandedElts, *this, Depth); | 

