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| author | Nate Begeman <natebegeman@mac.com> | 2005-12-01 04:51:06 +0000 |
|---|---|---|
| committer | Nate Begeman <natebegeman@mac.com> | 2005-12-01 04:51:06 +0000 |
| commit | 006bb04f3ab11fabf0d7f01149ce687fb508125a (patch) | |
| tree | 13e8f62ec30ed542e68ffa4a23ce28b5f2ce6ad1 /llvm/lib/CodeGen/SelectionDAG | |
| parent | aa5f8f2a262857da781e23fe919e374e98a0151a (diff) | |
| download | bcm5719-llvm-006bb04f3ab11fabf0d7f01149ce687fb508125a.tar.gz bcm5719-llvm-006bb04f3ab11fabf0d7f01149ce687fb508125a.zip | |
Support multiple ValueTypes per RegisterClass, needed for upcoming vector
work. This change has no effect on generated code.
llvm-svn: 24563
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp index f250a7bc050..c1a7f47bbc3 100644 --- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp @@ -1208,7 +1208,7 @@ void SimpleSched::EmitNode(NodeInfo *NI) { // Pick the register class of the right type that contains this physreg. for (MRegisterInfo::regclass_iterator I = MRI.regclass_begin(), E = MRI.regclass_end(); I != E; ++I) - if ((*I)->getType() == Node->getValueType(0) && + if ((*I)->hasType(Node->getValueType(0)) && (*I)->contains(SrcReg)) { TRC = *I; break; |
