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| author | Craig Topper <craig.topper@gmail.com> | 2017-04-20 03:49:18 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2017-04-20 03:49:18 +0000 |
| commit | 4db0c6937335f46f6752ef4afe102406fc9df626 (patch) | |
| tree | 2ed935c96ae14c20c4fa6e28ea0c177d2e3e40da /llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | |
| parent | 9df8ef55384ee0d5cce3d2a8b1e86d7ba6d07b94 (diff) | |
| download | bcm5719-llvm-4db0c6937335f46f6752ef4afe102406fc9df626.tar.gz bcm5719-llvm-4db0c6937335f46f6752ef4afe102406fc9df626.zip | |
Recommit "[APInt] Add back the asserts that check that the APInt shift methods aren't called with values larger than BitWidth."
This includes a fix to clamp a right shift of larger than BitWidth in DAG combining.
llvm-svn: 300816
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 91230b93423..24fd206a2d4 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -861,11 +861,12 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op, InnerOp.getOpcode() == ISD::SRL && InnerOp.hasOneUse() && isa<ConstantSDNode>(InnerOp.getOperand(1))) { - uint64_t InnerShAmt = cast<ConstantSDNode>(InnerOp.getOperand(1)) + unsigned InnerShAmt = cast<ConstantSDNode>(InnerOp.getOperand(1)) ->getZExtValue(); if (InnerShAmt < ShAmt && InnerShAmt < InnerBits && - NewMask.lshr(InnerBits - InnerShAmt + ShAmt) == 0 && + NewMask.lshr(std::min(InnerBits - InnerShAmt + ShAmt, + BitWidth)) == 0 && NewMask.trunc(ShAmt) == 0) { SDValue NewSA = TLO.DAG.getConstant(ShAmt - InnerShAmt, dl, |
