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| author | Craig Topper <craig.topper@gmail.com> | 2017-04-20 03:49:18 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2017-04-20 03:49:18 +0000 |
| commit | 4db0c6937335f46f6752ef4afe102406fc9df626 (patch) | |
| tree | 2ed935c96ae14c20c4fa6e28ea0c177d2e3e40da | |
| parent | 9df8ef55384ee0d5cce3d2a8b1e86d7ba6d07b94 (diff) | |
| download | bcm5719-llvm-4db0c6937335f46f6752ef4afe102406fc9df626.tar.gz bcm5719-llvm-4db0c6937335f46f6752ef4afe102406fc9df626.zip | |
Recommit "[APInt] Add back the asserts that check that the APInt shift methods aren't called with values larger than BitWidth."
This includes a fix to clamp a right shift of larger than BitWidth in DAG combining.
llvm-svn: 300816
| -rw-r--r-- | llvm/include/llvm/ADT/APInt.h | 6 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 5 | ||||
| -rw-r--r-- | llvm/unittests/ADT/APIntTest.cpp | 4 |
3 files changed, 9 insertions, 6 deletions
diff --git a/llvm/include/llvm/ADT/APInt.h b/llvm/include/llvm/ADT/APInt.h index 5b298199371..5f87765a52d 100644 --- a/llvm/include/llvm/ADT/APInt.h +++ b/llvm/include/llvm/ADT/APInt.h @@ -847,8 +847,9 @@ public: /// /// \returns *this after shifting left by ShiftAmt APInt &operator<<=(unsigned ShiftAmt) { + assert(ShiftAmt <= BitWidth && "Invalid shift amount"); if (isSingleWord()) { - if (ShiftAmt >= BitWidth) + if (ShiftAmt == BitWidth) VAL = 0; else VAL <<= ShiftAmt; @@ -893,8 +894,9 @@ public: /// Logical right-shift this APInt by ShiftAmt in place. void lshrInPlace(unsigned ShiftAmt) { + assert(ShiftAmt <= BitWidth && "Invalid shift amount"); if (isSingleWord()) { - if (ShiftAmt >= BitWidth) + if (ShiftAmt == BitWidth) VAL = 0; else VAL >>= ShiftAmt; diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 91230b93423..24fd206a2d4 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -861,11 +861,12 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op, InnerOp.getOpcode() == ISD::SRL && InnerOp.hasOneUse() && isa<ConstantSDNode>(InnerOp.getOperand(1))) { - uint64_t InnerShAmt = cast<ConstantSDNode>(InnerOp.getOperand(1)) + unsigned InnerShAmt = cast<ConstantSDNode>(InnerOp.getOperand(1)) ->getZExtValue(); if (InnerShAmt < ShAmt && InnerShAmt < InnerBits && - NewMask.lshr(InnerBits - InnerShAmt + ShAmt) == 0 && + NewMask.lshr(std::min(InnerBits - InnerShAmt + ShAmt, + BitWidth)) == 0 && NewMask.trunc(ShAmt) == 0) { SDValue NewSA = TLO.DAG.getConstant(ShAmt - InnerShAmt, dl, diff --git a/llvm/unittests/ADT/APIntTest.cpp b/llvm/unittests/ADT/APIntTest.cpp index 0f1d2d6d8f9..7d451836ad9 100644 --- a/llvm/unittests/ADT/APIntTest.cpp +++ b/llvm/unittests/ADT/APIntTest.cpp @@ -2021,7 +2021,7 @@ TEST(APIntTest, LogicalRightShift) { // Ensure we handle large shifts of multi-word. const APInt neg_one(128, static_cast<uint64_t>(-1), true); - EXPECT_EQ(0, neg_one.lshr(257)); + EXPECT_EQ(0, neg_one.lshr(128)); } TEST(APIntTest, LeftShift) { @@ -2054,7 +2054,7 @@ TEST(APIntTest, LeftShift) { // Ensure we handle large shifts of multi-word. const APInt neg_one(128, static_cast<uint64_t>(-1), true); - EXPECT_EQ(0, neg_one.shl(257)); + EXPECT_EQ(0, neg_one.shl(128)); } } // end anonymous namespace |
