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authorChris Lattner <sabre@nondot.org>2006-11-03 01:28:29 +0000
committerChris Lattner <sabre@nondot.org>2006-11-03 01:28:29 +0000
commitcd7b92251d54979b67c6dd09c039e307aee53aba (patch)
tree799ad3ad2fcff547eef986d228fa56664745d3d6 /llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
parent5314f04de5df9d6c5d4e95d3da0a21d70fc23c5d (diff)
downloadbcm5719-llvm-cd7b92251d54979b67c6dd09c039e307aee53aba.tar.gz
bcm5719-llvm-cd7b92251d54979b67c6dd09c039e307aee53aba.zip
silence warning
llvm-svn: 31397
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp35
1 files changed, 0 insertions, 35 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index 7befa9c4ca5..b37d2825bc8 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -155,41 +155,6 @@ void ScheduleDAGRRList::CommuteNodesToReducePressure() {
// Bottom-Up Scheduling
//===----------------------------------------------------------------------===//
-static const TargetRegisterClass *getRegClass(SUnit *SU,
- const TargetInstrInfo *TII,
- const MRegisterInfo *MRI,
- SSARegMap *RegMap) {
- if (SU->Node->isTargetOpcode()) {
- unsigned Opc = SU->Node->getTargetOpcode();
- const TargetInstrDescriptor &II = TII->get(Opc);
- return MRI->getRegClass(II.OpInfo->RegClass);
- } else {
- assert(SU->Node->getOpcode() == ISD::CopyFromReg);
- unsigned SrcReg = cast<RegisterSDNode>(SU->Node->getOperand(1))->getReg();
- if (MRegisterInfo::isVirtualRegister(SrcReg))
- return RegMap->getRegClass(SrcReg);
- else {
- for (MRegisterInfo::regclass_iterator I = MRI->regclass_begin(),
- E = MRI->regclass_end(); I != E; ++I)
- if ((*I)->hasType(SU->Node->getValueType(0)) &&
- (*I)->contains(SrcReg))
- return *I;
- assert(false && "Couldn't find register class for reg copy!");
- }
- return NULL;
- }
-}
-
-static unsigned getNumResults(SUnit *SU) {
- unsigned NumResults = 0;
- for (unsigned i = 0, e = SU->Node->getNumValues(); i != e; ++i) {
- MVT::ValueType VT = SU->Node->getValueType(i);
- if (VT != MVT::Other && VT != MVT::Flag)
- NumResults++;
- }
- return NumResults;
-}
-
/// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. Add it to
/// the Available queue is the count reaches zero. Also update its cycle bound.
void ScheduleDAGRRList::ReleasePred(SUnit *PredSU, bool isChain,
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