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author | Dan Gohman <gohman@apple.com> | 2008-11-11 17:50:47 +0000 |
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committer | Dan Gohman <gohman@apple.com> | 2008-11-11 17:50:47 +0000 |
commit | 5499e89d06ba27f89dbffb028cbce72e3a3c95ed (patch) | |
tree | 06107b6286caec31bb139422ead1cfae0027e1ac /llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp | |
parent | fbd2f4006b702df389acf539034727b744c08444 (diff) | |
download | bcm5719-llvm-5499e89d06ba27f89dbffb028cbce72e3a3c95ed.tar.gz bcm5719-llvm-5499e89d06ba27f89dbffb028cbce72e3a3c95ed.zip |
Change the scheduler accessor methods to accept an explicit TargetMachine
argument instead of taking the SelectionDAG's TargetMachine. This is
needed for some upcoming scheduler changes.
llvm-svn: 59055
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp')
-rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index d1617bd60c8..5ae31589611 100644 --- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -1881,27 +1881,29 @@ void TDRegReductionPriorityQueue::CalculateSethiUllmanNumbers() { llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, SelectionDAG *DAG, + const TargetMachine *TM, MachineBasicBlock *BB, bool Fast) { if (Fast) - return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), true, true, + return new ScheduleDAGRRList(*DAG, BB, *TM, true, true, new BURegReductionFastPriorityQueue()); - const TargetInstrInfo *TII = DAG->getTarget().getInstrInfo(); - const TargetRegisterInfo *TRI = DAG->getTarget().getRegisterInfo(); + const TargetInstrInfo *TII = TM->getInstrInfo(); + const TargetRegisterInfo *TRI = TM->getRegisterInfo(); BURegReductionPriorityQueue *PQ = new BURegReductionPriorityQueue(TII, TRI); ScheduleDAGRRList *SD = - new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(),true,false, PQ); + new ScheduleDAGRRList(*DAG, BB, *TM, true, false, PQ); PQ->setScheduleDAG(SD); return SD; } llvm::ScheduleDAG* llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, SelectionDAG *DAG, + const TargetMachine *TM, MachineBasicBlock *BB, bool Fast) { - return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), false, Fast, + return new ScheduleDAGRRList(*DAG, BB, *TM, false, Fast, new TDRegReductionPriorityQueue()); } |