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| author | Nadav Rotem <nadav.rotem@intel.com> | 2011-11-10 06:54:20 +0000 |
|---|---|---|
| committer | Nadav Rotem <nadav.rotem@intel.com> | 2011-11-10 06:54:20 +0000 |
| commit | 0a2f797deca72bc07b3ef7e96e32d165ed9d3c48 (patch) | |
| tree | ba0b66f14de813566348f0a1bff00f2e4c7b1897 /llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp | |
| parent | d62306a4819a67684ab342d5bd530df2c7ee9148 (diff) | |
| download | bcm5719-llvm-0a2f797deca72bc07b3ef7e96e32d165ed9d3c48.tar.gz bcm5719-llvm-0a2f797deca72bc07b3ef7e96e32d165ed9d3c48.zip | |
AVX2: Add variable shift from memory.
Note: These patterns only works in some cases because
many times the load sd node is bitcasted from a load
node of a different type.
llvm-svn: 144266
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp')
0 files changed, 0 insertions, 0 deletions
