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| author | Craig Topper <craig.topper@intel.com> | 2019-01-06 07:06:35 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-01-06 07:06:35 +0000 |
| commit | 57fc891c1b87585255b00d29f07f6b8b6f11643c (patch) | |
| tree | dcd6eccadd039dc1e1a0d2d57d27e7ad388c8b89 /llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | |
| parent | a2685cd6dcc705351902a7401639eca2190ebd66 (diff) | |
| download | bcm5719-llvm-57fc891c1b87585255b00d29f07f6b8b6f11643c.tar.gz bcm5719-llvm-57fc891c1b87585255b00d29f07f6b8b6f11643c.zip | |
[LegalizeVectorOps] Add FSHL/FSHR to the list of vector operations that should be handled.
The FSHL/FSHR nodes are handled in the expand function, but they need to also be listed in the code that queries for the operation action too.
llvm-svn: 350490
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp index 4df02c6a6bc..753158dc2c3 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp @@ -351,6 +351,8 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) { case ISD::SHL: case ISD::SRA: case ISD::SRL: + case ISD::FSHL: + case ISD::FSHR: case ISD::ROTL: case ISD::ROTR: case ISD::BSWAP: |
