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authorWang, Pengfei <pengfei.wang@intel.com>2019-12-24 09:44:22 +0800
committerWang, Pengfei <pengfei.wang@intel.com>2019-12-26 08:15:13 +0800
commit472bded3eda44eff84b259b2717e322dbdb7381e (patch)
treef1d011d804ba8b4ef93071c0a510b1a000b91b4d /llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
parentb082a2952f64b085127e0a0aad0b742c63e5075e (diff)
downloadbcm5719-llvm-472bded3eda44eff84b259b2717e322dbdb7381e.tar.gz
bcm5719-llvm-472bded3eda44eff84b259b2717e322dbdb7381e.zip
[X86] Enable STRICT_SINT_TO_FP/STRICT_UINT_TO_FP on X86 backend
Summary: Enable STRICT_SINT_TO_FP/STRICT_UINT_TO_FP on X86 backend Reviewers: craig.topper, RKSimon, LiuChen3, uweigand, andrew.w.kaylor Subscribers: hiraditya, llvm-commits, LuoYuanke Tags: #llvm Differential Revision: https://reviews.llvm.org/D71871
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp15
1 files changed, 12 insertions, 3 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index 4e907fd19e7..d9f95df57be 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -502,6 +502,8 @@ SDValue VectorLegalizer::Promote(SDValue Op) {
switch (Op.getOpcode()) {
case ISD::SINT_TO_FP:
case ISD::UINT_TO_FP:
+ case ISD::STRICT_SINT_TO_FP:
+ case ISD::STRICT_UINT_TO_FP:
// "Promote" the operation by extending the operand.
return PromoteINT_TO_FP(Op);
case ISD::FP_TO_UINT:
@@ -550,7 +552,8 @@ SDValue VectorLegalizer::Promote(SDValue Op) {
SDValue VectorLegalizer::PromoteINT_TO_FP(SDValue Op) {
// INT_TO_FP operations may require the input operand be promoted even
// when the type is otherwise legal.
- MVT VT = Op.getOperand(0).getSimpleValueType();
+ bool IsStrict = Op->isStrictFPOpcode();
+ MVT VT = Op.getOperand(IsStrict ? 1 : 0).getSimpleValueType();
MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
assert(NVT.getVectorNumElements() == VT.getVectorNumElements() &&
"Vectors have different number of elements!");
@@ -558,8 +561,10 @@ SDValue VectorLegalizer::PromoteINT_TO_FP(SDValue Op) {
SDLoc dl(Op);
SmallVector<SDValue, 4> Operands(Op.getNumOperands());
- unsigned Opc = Op.getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND :
- ISD::SIGN_EXTEND;
+ unsigned Opc = (Op.getOpcode() == ISD::UINT_TO_FP ||
+ Op.getOpcode() == ISD::STRICT_UINT_TO_FP)
+ ? ISD::ZERO_EXTEND
+ : ISD::SIGN_EXTEND;
for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
if (Op.getOperand(j).getValueType().isVector())
Operands[j] = DAG.getNode(Opc, dl, NVT, Op.getOperand(j));
@@ -567,6 +572,10 @@ SDValue VectorLegalizer::PromoteINT_TO_FP(SDValue Op) {
Operands[j] = Op.getOperand(j);
}
+ if (IsStrict)
+ return DAG.getNode(Op.getOpcode(), dl, {Op.getValueType(), MVT::Other},
+ Operands);
+
return DAG.getNode(Op.getOpcode(), dl, Op.getValueType(), Operands);
}
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