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authorSimon Pilgrim <llvm-dev@redking.me.uk>2018-10-13 15:16:55 +0000
committerSimon Pilgrim <llvm-dev@redking.me.uk>2018-10-13 15:16:55 +0000
commit1c2051ead7fa9eaee3f7e21b5e7cf4915a7232b3 (patch)
tree16b8d432480026bf11790113197675a98bce319f /llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
parent1c6d3203510bcae9680e8e721919341da063c915 (diff)
downloadbcm5719-llvm-1c2051ead7fa9eaee3f7e21b5e7cf4915a7232b3.tar.gz
bcm5719-llvm-1c2051ead7fa9eaee3f7e21b5e7cf4915a7232b3.zip
[X86][SSE] Begin removing vector CTTZ custom lowering and use LegalizeDAG instead.
Adds CTTZ vector legalization support and begins the removal of the X86/SSE custom lowering. llvm-svn: 344453
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp18
1 files changed, 15 insertions, 3 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index 8cc37b5f233..58d86e8e52e 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -129,7 +129,7 @@ class VectorLegalizer {
SDValue ExpandFSUB(SDValue Op);
SDValue ExpandBITREVERSE(SDValue Op);
SDValue ExpandCTLZ(SDValue Op);
- SDValue ExpandCTTZ_ZERO_UNDEF(SDValue Op);
+ SDValue ExpandCTTZ(SDValue Op);
SDValue ExpandStrictFPOp(SDValue Op);
/// Implements vector promotion.
@@ -717,8 +717,9 @@ SDValue VectorLegalizer::Expand(SDValue Op) {
case ISD::CTLZ:
case ISD::CTLZ_ZERO_UNDEF:
return ExpandCTLZ(Op);
+ case ISD::CTTZ:
case ISD::CTTZ_ZERO_UNDEF:
- return ExpandCTTZ_ZERO_UNDEF(Op);
+ return ExpandCTTZ(Op);
case ISD::STRICT_FADD:
case ISD::STRICT_FSUB:
case ISD::STRICT_FMUL:
@@ -1094,8 +1095,9 @@ SDValue VectorLegalizer::ExpandCTLZ(SDValue Op) {
return DAG.UnrollVectorOp(Op.getNode());
}
-SDValue VectorLegalizer::ExpandCTTZ_ZERO_UNDEF(SDValue Op) {
+SDValue VectorLegalizer::ExpandCTTZ(SDValue Op) {
EVT VT = Op.getValueType();
+ unsigned NumBitsPerElt = VT.getScalarSizeInBits();
// If the non-ZERO_UNDEF version is supported we can use that instead.
if (TLI.isOperationLegalOrCustom(ISD::CTTZ, VT)) {
@@ -1103,6 +1105,16 @@ SDValue VectorLegalizer::ExpandCTTZ_ZERO_UNDEF(SDValue Op) {
return DAG.getNode(ISD::CTTZ, DL, VT, Op.getOperand(0));
}
+ // If we have the appropriate vector bit operations, it is better to use them
+ // than unrolling and expanding each component.
+ if (isPowerOf2_32(NumBitsPerElt) &&
+ (TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) ||
+ TLI.isOperationLegalOrCustom(ISD::CTLZ, VT)) &&
+ TLI.isOperationLegalOrCustom(ISD::SUB, VT) &&
+ TLI.isOperationLegalOrCustomOrPromote(ISD::AND, VT) &&
+ TLI.isOperationLegalOrCustomOrPromote(ISD::XOR, VT))
+ return Op;
+
// Otherwise go ahead and unroll.
return DAG.UnrollVectorOp(Op.getNode());
}
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