[SelectionDAG] Initial support for FSHL/FSHR funnel shift opcodes (PR39467)

This is an initial patch to add a minimum level of support for funnel shifts to the SelectionDAG and to begin wiring it up to the X86 SHLD/SHRD instructions.

Some partial legalization code has been added to handle the case for 'SlowSHLD' where we want to expand instead and I've added a few DAG combines so we don't get regressions from the existing DAG builder expansion code.

Differential Revision: https://reviews.llvm.org/D54698

llvm-svn: 348353

1 files changed, 50 insertions, 38 deletions

diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index 4f283e9f3b8..4229e577a3d 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -129,12 +129,13 @@ class VectorLegalizer {
   SDValue ExpandFNEG(SDValue Op);
   SDValue ExpandFSUB(SDValue Op);
   SDValue ExpandBITREVERSE(SDValue Op);
-  SDValue ExpandCTPOP(SDValue Op);

-  SDValue ExpandCTLZ(SDValue Op);

-  SDValue ExpandCTTZ(SDValue Op);

-  SDValue ExpandFMINNUM_FMAXNUM(SDValue Op);

-  SDValue ExpandStrictFPOp(SDValue Op);

-

+  SDValue ExpandCTPOP(SDValue Op);
+  SDValue ExpandCTLZ(SDValue Op);
+  SDValue ExpandCTTZ(SDValue Op);
+  SDValue ExpandFunnelShift(SDValue Op);
+  SDValue ExpandFMINNUM_FMAXNUM(SDValue Op);
+  SDValue ExpandStrictFPOp(SDValue Op);
+
   /// Implements vector promotion.
   ///
   /// This is essentially just bitcasting the operands to a different type and
@@ -746,12 +747,15 @@ SDValue VectorLegalizer::Expand(SDValue Op) {
   case ISD::CTLZ:
   case ISD::CTLZ_ZERO_UNDEF:
     return ExpandCTLZ(Op);
-  case ISD::CTTZ:

-  case ISD::CTTZ_ZERO_UNDEF:

-    return ExpandCTTZ(Op);

-  case ISD::FMINNUM:

-  case ISD::FMAXNUM:

-    return ExpandFMINNUM_FMAXNUM(Op);

+  case ISD::CTTZ:
+  case ISD::CTTZ_ZERO_UNDEF:
+    return ExpandCTTZ(Op);
+  case ISD::FSHL:
+  case ISD::FSHR:
+    return ExpandFunnelShift(Op);
+  case ISD::FMINNUM:
+  case ISD::FMAXNUM:
+    return ExpandFMINNUM_FMAXNUM(Op);
   case ISD::STRICT_FADD:
   case ISD::STRICT_FSUB:
   case ISD::STRICT_FMUL:
@@ -1123,32 +1127,40 @@ SDValue VectorLegalizer::ExpandFSUB(SDValue Op) {
     return Op; // Defer to LegalizeDAG
 
   return DAG.UnrollVectorOp(Op.getNode());
-}

-

-SDValue VectorLegalizer::ExpandCTPOP(SDValue Op) {

-  SDValue Result;

-  if (TLI.expandCTPOP(Op.getNode(), Result, DAG))

-    return Result;

-

-  return DAG.UnrollVectorOp(Op.getNode());

-}

-

-SDValue VectorLegalizer::ExpandCTLZ(SDValue Op) {

-  SDValue Result;

-  if (TLI.expandCTLZ(Op.getNode(), Result, DAG))

-    return Result;

-

-  return DAG.UnrollVectorOp(Op.getNode());

-}

-

-SDValue VectorLegalizer::ExpandCTTZ(SDValue Op) {

-  SDValue Result;

-  if (TLI.expandCTTZ(Op.getNode(), Result, DAG))

-    return Result;

-

-  return DAG.UnrollVectorOp(Op.getNode());

-}

-

+}
+
+SDValue VectorLegalizer::ExpandCTPOP(SDValue Op) {
+  SDValue Result;
+  if (TLI.expandCTPOP(Op.getNode(), Result, DAG))
+    return Result;
+
+  return DAG.UnrollVectorOp(Op.getNode());
+}
+
+SDValue VectorLegalizer::ExpandCTLZ(SDValue Op) {
+  SDValue Result;
+  if (TLI.expandCTLZ(Op.getNode(), Result, DAG))
+    return Result;
+
+  return DAG.UnrollVectorOp(Op.getNode());
+}
+
+SDValue VectorLegalizer::ExpandCTTZ(SDValue Op) {
+  SDValue Result;
+  if (TLI.expandCTTZ(Op.getNode(), Result, DAG))
+    return Result;
+
+  return DAG.UnrollVectorOp(Op.getNode());
+}
+
+SDValue VectorLegalizer::ExpandFunnelShift(SDValue Op) {
+  SDValue Result;
+  if (TLI.expandFunnelShift(Op.getNode(), Result, DAG))
+    return Result;
+
+  return DAG.UnrollVectorOp(Op.getNode());
+}
+
 SDValue VectorLegalizer::ExpandFMINNUM_FMAXNUM(SDValue Op) {
   if (SDValue Expanded = TLI.expandFMINNUM_FMAXNUM(Op.getNode(), DAG))
     return Expanded;