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| author | Nadav Rotem <nadav.rotem@intel.com> | 2012-04-15 15:08:09 +0000 |
|---|---|---|
| committer | Nadav Rotem <nadav.rotem@intel.com> | 2012-04-15 15:08:09 +0000 |
| commit | 02ef0c3524777fd58023985c1ebc3f2015ff6fc6 (patch) | |
| tree | 2071df719187c3ee8b58641f71887bbc575752b1 /llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | |
| parent | 89f0b2d8a2a88609b859e040d0593fcff364e3d0 (diff) | |
| download | bcm5719-llvm-02ef0c3524777fd58023985c1ebc3f2015ff6fc6.tar.gz bcm5719-llvm-02ef0c3524777fd58023985c1ebc3f2015ff6fc6.zip | |
When emulating vselect using OR/AND/XOR make sure to bitcast the result back to the original type.
llvm-svn: 154764
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp index 3ae8345bd19..9fe4480d113 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp @@ -417,7 +417,8 @@ SDValue VectorLegalizer::ExpandVSELECT(SDValue Op) { Op1 = DAG.getNode(ISD::AND, DL, VT, Op1, Mask); Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask); - return DAG.getNode(ISD::OR, DL, VT, Op1, Op2); + SDValue Val = DAG.getNode(ISD::OR, DL, VT, Op1, Op2); + return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val); } SDValue VectorLegalizer::ExpandUINT_TO_FLOAT(SDValue Op) { |
