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authorRoman Lebedev <lebedev.ri@gmail.com>2018-05-07 21:52:11 +0000
committerRoman Lebedev <lebedev.ri@gmail.com>2018-05-07 21:52:11 +0000
commitcc42d08b1daf6874e7b65986443510bfc5e0abc3 (patch)
treeade7212a0b263366809902766925ee60d779acd4 /llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
parent45fc2c83e60265f3772ba86b9b832f3d540ef049 (diff)
downloadbcm5719-llvm-cc42d08b1daf6874e7b65986443510bfc5e0abc3.tar.gz
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[DagCombiner] Not all 'andn''s work with immediates.
Summary: Split off from D46031. In masked merge case, this degrades IPC by decreasing instruction count. {F6108777} The next patch should be able to recover and improve this. This also affects the transform @spatel have added in D27489 / rL289738, and the test coverage for X86 was missing. But after i have added it, and looked at the changes in MCA, i'm somewhat confused. {F6093591} {F6093592} {F6093593} I'd say this regression is an improvement, since `IPC` increased in that case? Reviewers: spatel, craig.topper Reviewed By: spatel Subscribers: andreadb, llvm-commits, spatel Differential Revision: https://reviews.llvm.org/D46493 llvm-svn: 331684
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp4
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 322e9be0083..b809bbc1c6c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -5428,6 +5428,10 @@ SDValue DAGCombiner::unfoldMaskedMerge(SDNode *N) {
if (!TLI.hasAndNot(M))
return SDValue();
+ // If Y is a constant, check that 'andn' works with immediates.
+ if (!TLI.hasAndNot(Y))
+ return SDValue();
+
SDLoc DL(N);
SDValue LHS = DAG.getNode(ISD::AND, DL, VT, X, M);
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