[DAGCombiner] add fold for 'All sign bits set?'

(and (setlt X,  0), (setlt Y,  0)) --> (setlt (and X, Y),  0)

We have 7 similar folds, but this one got away. The fact that the
x86 test with a branch didn't change is probably a separate bug. We
may also be missing this and the related folds in instcombine.

llvm-svn: 299252

1 files changed, 4 insertions, 2 deletions

diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 63b362d3a37..3f68390b814 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -3214,8 +3214,10 @@ SDValue DAGCombiner::foldAndOfSetCCs(SDValue N0, SDValue N1, const SDLoc &DL) {
 
     // All bits set?
     // (and (seteq X, -1), (seteq Y, -1)) --> (seteq (and X, Y), -1)
-    // TODO: All sign bits set?
-    if (isAllOnesConstant(LR) && CC1 == ISD::SETEQ) {
+    // All sign bits set?
+    // (and (setlt X,  0), (setlt Y,  0)) --> (setlt (and X, Y),  0)
+    if ((isAllOnesConstant(LR) && CC1 == ISD::SETEQ) ||
+        (isNullConstant(LR) && CC1 == ISD::SETLT)) {
       SDValue And = DAG.getNode(ISD::AND, SDLoc(N0), OpVT, LL, RL);
       AddToWorklist(And.getNode());
       return DAG.getSetCC(DL, VT, And, LR, CC1);