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author | Andrew Trick <atrick@apple.com> | 2012-01-14 02:17:18 +0000 |
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committer | Andrew Trick <atrick@apple.com> | 2012-01-14 02:17:18 +0000 |
commit | 59ac4fb706ae6e5d61bc692dd4bfb43273a891e1 (patch) | |
tree | dd8ec40fa9a3a54e08b6ab37ea9bdf9d2f146bfb /llvm/lib/CodeGen/ScheduleDAG.cpp | |
parent | dbee9d8900a33423b3d50b357c05db5d0776194a (diff) | |
download | bcm5719-llvm-59ac4fb706ae6e5d61bc692dd4bfb43273a891e1.tar.gz bcm5719-llvm-59ac4fb706ae6e5d61bc692dd4bfb43273a891e1.zip |
misched: Initial code for building an MI level scheduling DAG
llvm-svn: 148174
Diffstat (limited to 'llvm/lib/CodeGen/ScheduleDAG.cpp')
-rw-r--r-- | llvm/lib/CodeGen/ScheduleDAG.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/ScheduleDAG.cpp b/llvm/lib/CodeGen/ScheduleDAG.cpp index e829668b4c8..f92c72a47bc 100644 --- a/llvm/lib/CodeGen/ScheduleDAG.cpp +++ b/llvm/lib/CodeGen/ScheduleDAG.cpp @@ -321,7 +321,7 @@ void SUnit::dumpAll(const ScheduleDAG *G) const { dbgs() << " *"; dbgs() << ": Latency=" << I->getLatency(); if (I->isAssignedRegDep()) - dbgs() << " Reg=" << G->TRI->getName(I->getReg()); + dbgs() << " Reg=" << PrintReg(I->getReg()); dbgs() << "\n"; } } |