summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen/RegisterScavenging.cpp
diff options
context:
space:
mode:
authorNicola Zaghen <nicola.zaghen@imgtec.com>2018-05-14 12:53:11 +0000
committerNicola Zaghen <nicola.zaghen@imgtec.com>2018-05-14 12:53:11 +0000
commitd34e60ca8532511acb8c93ef26297e349fbec86a (patch)
tree1a095bc8694498d94232e81b95c1da05d462d3ec /llvm/lib/CodeGen/RegisterScavenging.cpp
parentaffbc99bea94e77f7ebccd8ba887e33051bd04ee (diff)
downloadbcm5719-llvm-d34e60ca8532511acb8c93ef26297e349fbec86a.tar.gz
bcm5719-llvm-d34e60ca8532511acb8c93ef26297e349fbec86a.zip
Rename DEBUG macro to LLVM_DEBUG.
The DEBUG() macro is very generic so it might clash with other projects. The renaming was done as follows: - git grep -l 'DEBUG' | xargs sed -i 's/\bDEBUG\s\?(/LLVM_DEBUG(/g' - git diff -U0 master | ../clang/tools/clang-format/clang-format-diff.py -i -p1 -style LLVM - Manual change to APInt - Manually chage DOCS as regex doesn't match it. In the transition period the DEBUG() macro is still present and aliased to the LLVM_DEBUG() one. Differential Revision: https://reviews.llvm.org/D43624 llvm-svn: 332240
Diffstat (limited to 'llvm/lib/CodeGen/RegisterScavenging.cpp')
-rw-r--r--llvm/lib/CodeGen/RegisterScavenging.cpp23
1 files changed, 12 insertions, 11 deletions
diff --git a/llvm/lib/CodeGen/RegisterScavenging.cpp b/llvm/lib/CodeGen/RegisterScavenging.cpp
index 9fa14c9dc5e..d7cd5a096ef 100644
--- a/llvm/lib/CodeGen/RegisterScavenging.cpp
+++ b/llvm/lib/CodeGen/RegisterScavenging.cpp
@@ -288,8 +288,8 @@ bool RegScavenger::isRegUsed(unsigned Reg, bool includeReserved) const {
unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RC) const {
for (unsigned Reg : *RC) {
if (!isRegUsed(Reg)) {
- DEBUG(dbgs() << "Scavenger found unused reg: " << printReg(Reg, TRI)
- << "\n");
+ LLVM_DEBUG(dbgs() << "Scavenger found unused reg: " << printReg(Reg, TRI)
+ << "\n");
return Reg;
}
}
@@ -561,15 +561,15 @@ unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
// If we found an unused register there is no reason to spill it.
if (!isRegUsed(SReg)) {
- DEBUG(dbgs() << "Scavenged register: " << printReg(SReg, TRI) << "\n");
+ LLVM_DEBUG(dbgs() << "Scavenged register: " << printReg(SReg, TRI) << "\n");
return SReg;
}
ScavengedInfo &Scavenged = spill(SReg, *RC, SPAdj, I, UseMI);
Scavenged.Restore = &*std::prev(UseMI);
- DEBUG(dbgs() << "Scavenged register (with spill): " << printReg(SReg, TRI)
- << "\n");
+ LLVM_DEBUG(dbgs() << "Scavenged register (with spill): "
+ << printReg(SReg, TRI) << "\n");
return SReg;
}
@@ -594,14 +594,15 @@ unsigned RegScavenger::scavengeRegisterBackwards(const TargetRegisterClass &RC,
MachineBasicBlock::iterator ReloadAfter =
RestoreAfter ? std::next(MBBI) : MBBI;
MachineBasicBlock::iterator ReloadBefore = std::next(ReloadAfter);
- DEBUG(dbgs() << "Reload before: " << *ReloadBefore << '\n');
+ LLVM_DEBUG(dbgs() << "Reload before: " << *ReloadBefore << '\n');
ScavengedInfo &Scavenged = spill(Reg, RC, SPAdj, SpillBefore, ReloadBefore);
Scavenged.Restore = &*std::prev(SpillBefore);
LiveUnits.removeReg(Reg);
- DEBUG(dbgs() << "Scavenged register with spill: " << printReg(Reg, TRI)
- << " until " << *SpillBefore);
+ LLVM_DEBUG(dbgs() << "Scavenged register with spill: " << printReg(Reg, TRI)
+ << " until " << *SpillBefore);
} else {
- DEBUG(dbgs() << "Scavenged free register: " << printReg(Reg, TRI) << '\n');
+ LLVM_DEBUG(dbgs() << "Scavenged free register: " << printReg(Reg, TRI)
+ << '\n');
}
return Reg;
}
@@ -757,8 +758,8 @@ void llvm::scavengeFrameVirtualRegs(MachineFunction &MF, RegScavenger &RS) {
bool Again = scavengeFrameVirtualRegsInBlock(MRI, RS, MBB);
if (Again) {
- DEBUG(dbgs() << "Warning: Required two scavenging passes for block "
- << MBB.getName() << '\n');
+ LLVM_DEBUG(dbgs() << "Warning: Required two scavenging passes for block "
+ << MBB.getName() << '\n');
Again = scavengeFrameVirtualRegsInBlock(MRI, RS, MBB);
// The target required a 2nd run (because it created new vregs while
// spilling). Refuse to do another pass to keep compiletime in check.
OpenPOWER on IntegriCloud