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| author | Nicola Zaghen <nicola.zaghen@imgtec.com> | 2018-05-14 12:53:11 +0000 |
|---|---|---|
| committer | Nicola Zaghen <nicola.zaghen@imgtec.com> | 2018-05-14 12:53:11 +0000 |
| commit | d34e60ca8532511acb8c93ef26297e349fbec86a (patch) | |
| tree | 1a095bc8694498d94232e81b95c1da05d462d3ec /llvm/lib/CodeGen | |
| parent | affbc99bea94e77f7ebccd8ba887e33051bd04ee (diff) | |
| download | bcm5719-llvm-d34e60ca8532511acb8c93ef26297e349fbec86a.tar.gz bcm5719-llvm-d34e60ca8532511acb8c93ef26297e349fbec86a.zip | |
Rename DEBUG macro to LLVM_DEBUG.
The DEBUG() macro is very generic so it might clash with other projects.
The renaming was done as follows:
- git grep -l 'DEBUG' | xargs sed -i 's/\bDEBUG\s\?(/LLVM_DEBUG(/g'
- git diff -U0 master | ../clang/tools/clang-format/clang-format-diff.py -i -p1 -style LLVM
- Manual change to APInt
- Manually chage DOCS as regex doesn't match it.
In the transition period the DEBUG() macro is still present and aliased
to the LLVM_DEBUG() one.
Differential Revision: https://reviews.llvm.org/D43624
llvm-svn: 332240
Diffstat (limited to 'llvm/lib/CodeGen')
110 files changed, 2220 insertions, 2143 deletions
diff --git a/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp b/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp index 1f76bdda079..632ea8e9cdc 100644 --- a/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp +++ b/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp @@ -139,10 +139,11 @@ AggressiveAntiDepBreaker::AggressiveAntiDepBreaker( CriticalPathSet |= CPSet; } - DEBUG(dbgs() << "AntiDep Critical-Path Registers:"); - DEBUG(for (unsigned r : CriticalPathSet.set_bits()) - dbgs() << " " << printReg(r, TRI)); - DEBUG(dbgs() << '\n'); + LLVM_DEBUG(dbgs() << "AntiDep Critical-Path Registers:"); + LLVM_DEBUG(for (unsigned r + : CriticalPathSet.set_bits()) dbgs() + << " " << printReg(r, TRI)); + LLVM_DEBUG(dbgs() << '\n'); } AggressiveAntiDepBreaker::~AggressiveAntiDepBreaker() { @@ -202,9 +203,9 @@ void AggressiveAntiDepBreaker::Observe(MachineInstr &MI, unsigned Count, PrescanInstruction(MI, Count, PassthruRegs); ScanInstruction(MI, Count); - DEBUG(dbgs() << "Observe: "); - DEBUG(MI.dump()); - DEBUG(dbgs() << "\tRegs:"); + LLVM_DEBUG(dbgs() << "Observe: "); + LLVM_DEBUG(MI.dump()); + LLVM_DEBUG(dbgs() << "\tRegs:"); std::vector<unsigned> &DefIndices = State->GetDefIndices(); for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { @@ -215,16 +216,16 @@ void AggressiveAntiDepBreaker::Observe(MachineInstr &MI, unsigned Count, // conservative location (i.e. the beginning of the previous // schedule region). if (State->IsLive(Reg)) { - DEBUG(if (State->GetGroup(Reg) != 0) - dbgs() << " " << printReg(Reg, TRI) << "=g" << - State->GetGroup(Reg) << "->g0(region live-out)"); + LLVM_DEBUG(if (State->GetGroup(Reg) != 0) dbgs() + << " " << printReg(Reg, TRI) << "=g" << State->GetGroup(Reg) + << "->g0(region live-out)"); State->UnionGroups(Reg, 0); } else if ((DefIndices[Reg] < InsertPosIndex) && (DefIndices[Reg] >= Count)) { DefIndices[Reg] = Count; } } - DEBUG(dbgs() << '\n'); + LLVM_DEBUG(dbgs() << '\n'); } bool AggressiveAntiDepBreaker::IsImplicitDefUse(MachineInstr &MI, @@ -313,7 +314,7 @@ void AggressiveAntiDepBreaker::HandleLastUse(unsigned Reg, unsigned KillIdx, // subregister definitions). for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) if (TRI->isSuperRegister(Reg, *AI) && State->IsLive(*AI)) { - DEBUG(if (!header && footer) dbgs() << footer); + LLVM_DEBUG(if (!header && footer) dbgs() << footer); return; } @@ -322,9 +323,11 @@ void AggressiveAntiDepBreaker::HandleLastUse(unsigned Reg, unsigned KillIdx, DefIndices[Reg] = ~0u; RegRefs.erase(Reg); State->LeaveGroup(Reg); - DEBUG(if (header) { - dbgs() << header << printReg(Reg, TRI); header = nullptr; }); - DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << tag); + LLVM_DEBUG(if (header) { + dbgs() << header << printReg(Reg, TRI); + header = nullptr; + }); + LLVM_DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << tag); // Repeat for subregisters. Note that we only do this if the superregister // was not live because otherwise, regardless whether we have an explicit // use of the subregister, the subregister's contents are needed for the @@ -336,15 +339,17 @@ void AggressiveAntiDepBreaker::HandleLastUse(unsigned Reg, unsigned KillIdx, DefIndices[SubregReg] = ~0u; RegRefs.erase(SubregReg); State->LeaveGroup(SubregReg); - DEBUG(if (header) { - dbgs() << header << printReg(Reg, TRI); header = nullptr; }); - DEBUG(dbgs() << " " << printReg(SubregReg, TRI) << "->g" << - State->GetGroup(SubregReg) << tag); + LLVM_DEBUG(if (header) { + dbgs() << header << printReg(Reg, TRI); + header = nullptr; + }); + LLVM_DEBUG(dbgs() << " " << printReg(SubregReg, TRI) << "->g" + << State->GetGroup(SubregReg) << tag); } } } - DEBUG(if (!header && footer) dbgs() << footer); + LLVM_DEBUG(if (!header && footer) dbgs() << footer); } void AggressiveAntiDepBreaker::PrescanInstruction( @@ -367,14 +372,15 @@ void AggressiveAntiDepBreaker::PrescanInstruction( HandleLastUse(Reg, Count + 1, "", "\tDead Def: ", "\n"); } - DEBUG(dbgs() << "\tDef Groups:"); + LLVM_DEBUG(dbgs() << "\tDef Groups:"); for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { MachineOperand &MO = MI.getOperand(i); if (!MO.isReg() || !MO.isDef()) continue; unsigned Reg = MO.getReg(); if (Reg == 0) continue; - DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g" << State->GetGroup(Reg)); + LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g" + << State->GetGroup(Reg)); // If MI's defs have a special allocation requirement, don't allow // any def registers to be changed. Also assume all registers @@ -383,7 +389,7 @@ void AggressiveAntiDepBreaker::PrescanInstruction( // can tell user specified registers from compiler-specified. if (MI.isCall() || MI.hasExtraDefRegAllocReq() || TII->isPredicated(MI) || MI.isInlineAsm()) { - DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)"); + LLVM_DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)"); State->UnionGroups(Reg, 0); } @@ -393,8 +399,8 @@ void AggressiveAntiDepBreaker::PrescanInstruction( unsigned AliasReg = *AI; if (State->IsLive(AliasReg)) { State->UnionGroups(Reg, AliasReg); - DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << "(via " - << printReg(AliasReg, TRI) << ")"); + LLVM_DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << "(via " + << printReg(AliasReg, TRI) << ")"); } } @@ -406,7 +412,7 @@ void AggressiveAntiDepBreaker::PrescanInstruction( RegRefs.insert(std::make_pair(Reg, RR)); } - DEBUG(dbgs() << '\n'); + LLVM_DEBUG(dbgs() << '\n'); // Scan the register defs for this instruction and update // live-ranges. @@ -437,7 +443,7 @@ void AggressiveAntiDepBreaker::PrescanInstruction( void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr &MI, unsigned Count) { - DEBUG(dbgs() << "\tUse Groups:"); + LLVM_DEBUG(dbgs() << "\tUse Groups:"); std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>& RegRefs = State->GetRegRefs(); @@ -469,7 +475,8 @@ void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr &MI, unsigned Reg = MO.getReg(); if (Reg == 0) continue; - DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g" << State->GetGroup(Reg)); + LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g" + << State->GetGroup(Reg)); // It wasn't previously live but now it is, this is a kill. Forget // the previous live-range information and start a new live-range @@ -477,7 +484,7 @@ void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr &MI, HandleLastUse(Reg, Count, "(last-use)"); if (Special) { - DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)"); + LLVM_DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)"); State->UnionGroups(Reg, 0); } @@ -489,12 +496,12 @@ void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr &MI, RegRefs.insert(std::make_pair(Reg, RR)); } - DEBUG(dbgs() << '\n'); + LLVM_DEBUG(dbgs() << '\n'); // Form a group of all defs and uses of a KILL instruction to ensure // that all registers are renamed as a group. if (MI.isKill()) { - DEBUG(dbgs() << "\tKill Group:"); + LLVM_DEBUG(dbgs() << "\tKill Group:"); unsigned FirstReg = 0; for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { @@ -504,15 +511,15 @@ void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr &MI, if (Reg == 0) continue; if (FirstReg != 0) { - DEBUG(dbgs() << "=" << printReg(Reg, TRI)); + LLVM_DEBUG(dbgs() << "=" << printReg(Reg, TRI)); State->UnionGroups(FirstReg, Reg); } else { - DEBUG(dbgs() << " " << printReg(Reg, TRI)); + LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI)); FirstReg = Reg; } } - DEBUG(dbgs() << "->g" << State->GetGroup(FirstReg) << '\n'); + LLVM_DEBUG(dbgs() << "->g" << State->GetGroup(FirstReg) << '\n'); } } @@ -535,7 +542,7 @@ BitVector AggressiveAntiDepBreaker::GetRenameRegisters(unsigned Reg) { BV &= RCBV; } - DEBUG(dbgs() << " " << TRI->getRegClassName(RC)); + LLVM_DEBUG(dbgs() << " " << TRI->getRegClassName(RC)); } return BV; @@ -562,8 +569,8 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters( // Find the "superest" register in the group. At the same time, // collect the BitVector of registers that can be used to rename // each register. - DEBUG(dbgs() << "\tRename Candidates for Group g" << AntiDepGroupIndex - << ":\n"); + LLVM_DEBUG(dbgs() << "\tRename Candidates for Group g" << AntiDepGroupIndex + << ":\n"); std::map<unsigned, BitVector> RenameRegisterMap; unsigned SuperReg = 0; for (unsigned i = 0, e = Regs.size(); i != e; ++i) { @@ -573,13 +580,13 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters( // If Reg has any references, then collect possible rename regs if (RegRefs.count(Reg) > 0) { - DEBUG(dbgs() << "\t\t" << printReg(Reg, TRI) << ":"); + LLVM_DEBUG(dbgs() << "\t\t" << printReg(Reg, TRI) << ":"); BitVector &BV = RenameRegisterMap[Reg]; assert(BV.empty()); BV = GetRenameRegisters(Reg); - DEBUG({ + LLVM_DEBUG({ dbgs() << " ::"; for (unsigned r : BV.set_bits()) dbgs() << " " << printReg(r, TRI); @@ -625,11 +632,11 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters( ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC); if (Order.empty()) { - DEBUG(dbgs() << "\tEmpty Super Regclass!!\n"); + LLVM_DEBUG(dbgs() << "\tEmpty Super Regclass!!\n"); return false; } - DEBUG(dbgs() << "\tFind Registers:"); + LLVM_DEBUG(dbgs() << "\tFind Registers:"); RenameOrder.insert(RenameOrderType::value_type(SuperRC, Order.size())); @@ -645,7 +652,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters( // Don't replace a register with itself. if (NewSuperReg == SuperReg) continue; - DEBUG(dbgs() << " [" << printReg(NewSuperReg, TRI) << ':'); + LLVM_DEBUG(dbgs() << " [" << printReg(NewSuperReg, TRI) << ':'); RenameMap.clear(); // For each referenced group register (which must be a SuperReg or @@ -662,11 +669,11 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters( NewReg = TRI->getSubReg(NewSuperReg, NewSubRegIdx); } - DEBUG(dbgs() << " " << printReg(NewReg, TRI)); + LLVM_DEBUG(dbgs() << " " << printReg(NewReg, TRI)); // Check if Reg can be renamed to NewReg. if (!RenameRegisterMap[Reg].test(NewReg)) { - DEBUG(dbgs() << "(no rename)"); + LLVM_DEBUG(dbgs() << "(no rename)"); goto next_super_reg; } @@ -675,7 +682,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters( // must also check all aliases of NewReg, because we can't define a // register when any sub or super is already live. if (State->IsLive(NewReg) || (KillIndices[Reg] > DefIndices[NewReg])) { - DEBUG(dbgs() << "(live)"); + LLVM_DEBUG(dbgs() << "(live)"); goto next_super_reg; } else { bool found = false; @@ -683,7 +690,8 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters( unsigned AliasReg = *AI; if (State->IsLive(AliasReg) || (KillIndices[Reg] > DefIndices[AliasReg])) { - DEBUG(dbgs() << "(alias " << printReg(AliasReg, TRI) << " live)"); + LLVM_DEBUG(dbgs() + << "(alias " << printReg(AliasReg, TRI) << " live)"); found = true; break; } @@ -701,7 +709,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters( continue; if (UseMI->getOperand(Idx).isEarlyClobber()) { - DEBUG(dbgs() << "(ec)"); + LLVM_DEBUG(dbgs() << "(ec)"); goto next_super_reg; } } @@ -715,7 +723,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters( MachineInstr *DefMI = Q.second.Operand->getParent(); if (DefMI->readsRegister(NewReg, TRI)) { - DEBUG(dbgs() << "(ec)"); + LLVM_DEBUG(dbgs() << "(ec)"); goto next_super_reg; } } @@ -728,14 +736,14 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters( // renamed, as recorded in RenameMap. RenameOrder.erase(SuperRC); RenameOrder.insert(RenameOrderType::value_type(SuperRC, R)); - DEBUG(dbgs() << "]\n"); + LLVM_DEBUG(dbgs() << "]\n"); return true; next_super_reg: - DEBUG(dbgs() << ']'); + LLVM_DEBUG(dbgs() << ']'); } while (R != EndR); - DEBUG(dbgs() << '\n'); + LLVM_DEBUG(dbgs() << '\n'); // No registers are free and available! return false; @@ -788,13 +796,13 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies( } #ifndef NDEBUG - DEBUG(dbgs() << "\n===== Aggressive anti-dependency breaking\n"); - DEBUG(dbgs() << "Available regs:"); + LLVM_DEBUG(dbgs() << "\n===== Aggressive anti-dependency breaking\n"); + LLVM_DEBUG(dbgs() << "Available regs:"); for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) { if (!State->IsLive(Reg)) - DEBUG(dbgs() << " " << printReg(Reg, TRI)); + LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI)); } - DEBUG(dbgs() << '\n'); + LLVM_DEBUG(dbgs() << '\n'); #endif BitVector RegAliases(TRI->getNumRegs()); @@ -811,8 +819,8 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies( if (MI.isDebugInstr()) continue; - DEBUG(dbgs() << "Anti: "); - DEBUG(MI.dump()); + LLVM_DEBUG(dbgs() << "Anti: "); + LLVM_DEBUG(MI.dump()); std::set<unsigned> PassthruRegs; GetPassthruRegs(MI, PassthruRegs); @@ -848,30 +856,30 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies( (Edge->getKind() != SDep::Output)) continue; unsigned AntiDepReg = Edge->getReg(); - DEBUG(dbgs() << "\tAntidep reg: " << printReg(AntiDepReg, TRI)); + LLVM_DEBUG(dbgs() << "\tAntidep reg: " << printReg(AntiDepReg, TRI)); assert(AntiDepReg != 0 && "Anti-dependence on reg0?"); if (!MRI.isAllocatable(AntiDepReg)) { // Don't break anti-dependencies on non-allocatable registers. - DEBUG(dbgs() << " (non-allocatable)\n"); + LLVM_DEBUG(dbgs() << " (non-allocatable)\n"); continue; } else if (ExcludeRegs && ExcludeRegs->test(AntiDepReg)) { // Don't break anti-dependencies for critical path registers // if not on the critical path - DEBUG(dbgs() << " (not critical-path)\n"); + LLVM_DEBUG(dbgs() << " (not critical-path)\n"); continue; } else if (PassthruRegs.count(AntiDepReg) != 0) { // If the anti-dep register liveness "passes-thru", then // don't try to change it. It will be changed along with // the use if required to break an earlier antidep. - DEBUG(dbgs() << " (passthru)\n"); + LLVM_DEBUG(dbgs() << " (passthru)\n"); continue; } else { // No anti-dep breaking for implicit deps MachineOperand *AntiDepOp = MI.findRegisterDefOperand(AntiDepReg); assert(AntiDepOp && "Can't find index for defined register operand"); if (!AntiDepOp || AntiDepOp->isImplicit()) { - DEBUG(dbgs() << " (implicit)\n"); + LLVM_DEBUG(dbgs() << " (implicit)\n"); continue; } @@ -897,13 +905,13 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies( PE = PathSU->Preds.end(); P != PE; ++P) { if ((P->getSUnit() == NextSU) && (P->getKind() != SDep::Anti) && (P->getKind() != SDep::Output)) { - DEBUG(dbgs() << " (real dependency)\n"); + LLVM_DEBUG(dbgs() << " (real dependency)\n"); AntiDepReg = 0; break; } else if ((P->getSUnit() != NextSU) && (P->getKind() == SDep::Data) && (P->getReg() == AntiDepReg)) { - DEBUG(dbgs() << " (other dependency)\n"); + LLVM_DEBUG(dbgs() << " (other dependency)\n"); AntiDepReg = 0; break; } @@ -941,17 +949,17 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies( // Determine AntiDepReg's register group. const unsigned GroupIndex = State->GetGroup(AntiDepReg); if (GroupIndex == 0) { - DEBUG(dbgs() << " (zero group)\n"); + LLVM_DEBUG(dbgs() << " (zero group)\n"); continue; } - DEBUG(dbgs() << '\n'); + LLVM_DEBUG(dbgs() << '\n'); // Look for a suitable register to use to break the anti-dependence. std::map<unsigned, unsigned> RenameMap; if (FindSuitableFreeRegisters(GroupIndex, RenameOrder, RenameMap)) { - DEBUG(dbgs() << "\tBreaking anti-dependence edge on " - << printReg(AntiDepReg, TRI) << ":"); + LLVM_DEBUG(dbgs() << "\tBreaking anti-dependence edge on " + << printReg(AntiDepReg, TRI) << ":"); // Handle each group register... for (std::map<unsigned, unsigned>::iterator @@ -959,9 +967,9 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies( unsigned CurrReg = S->first; unsigned NewReg = S->second; - DEBUG(dbgs() << " " << printReg(CurrReg, TRI) << "->" - << printReg(NewReg, TRI) << "(" - << RegRefs.count(CurrReg) << " refs)"); + LLVM_DEBUG(dbgs() << " " << printReg(CurrReg, TRI) << "->" + << printReg(NewReg, TRI) << "(" + << RegRefs.count(CurrReg) << " refs)"); // Update the references to the old register CurrReg to // refer to the new register NewReg. @@ -994,7 +1002,7 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies( } ++Broken; - DEBUG(dbgs() << '\n'); + LLVM_DEBUG(dbgs() << '\n'); } } } diff --git a/llvm/lib/CodeGen/AllocationOrder.cpp b/llvm/lib/CodeGen/AllocationOrder.cpp index 8e8c1d8e08d..37dcb0be824 100644 --- a/llvm/lib/CodeGen/AllocationOrder.cpp +++ b/llvm/lib/CodeGen/AllocationOrder.cpp @@ -39,7 +39,7 @@ AllocationOrder::AllocationOrder(unsigned VirtReg, HardHints = true; rewind(); - DEBUG({ + LLVM_DEBUG({ if (!Hints.empty()) { dbgs() << "hints:"; for (unsigned I = 0, E = Hints.size(); I != E; ++I) diff --git a/llvm/lib/CodeGen/AsmPrinter/DIE.cpp b/llvm/lib/CodeGen/AsmPrinter/DIE.cpp index 15bbc15021a..570424a79c8 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DIE.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/DIE.cpp @@ -87,8 +87,9 @@ void DIEAbbrev::Emit(const AsmPrinter *AP) const { // easily, which helps track down where it came from. if (!dwarf::isValidFormForVersion(AttrData.getForm(), AP->getDwarfVersion())) { - DEBUG(dbgs() << "Invalid form " << format("0x%x", AttrData.getForm()) - << " for DWARF version " << AP->getDwarfVersion() << "\n"); + LLVM_DEBUG(dbgs() << "Invalid form " << format("0x%x", AttrData.getForm()) + << " for DWARF version " << AP->getDwarfVersion() + << "\n"); llvm_unreachable("Invalid form for specified DWARF version"); } #endif diff --git a/llvm/lib/CodeGen/AsmPrinter/DIEHash.cpp b/llvm/lib/CodeGen/AsmPrinter/DIEHash.cpp index 5392b7150a7..b8f1202494d 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DIEHash.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/DIEHash.cpp @@ -43,7 +43,7 @@ static StringRef getDIEStringAttr(const DIE &Die, uint16_t Attr) { /// Adds the string in \p Str to the hash. This also hashes /// a trailing NULL with the string. void DIEHash::addString(StringRef Str) { - DEBUG(dbgs() << "Adding string " << Str << " to hash.\n"); + LLVM_DEBUG(dbgs() << "Adding string " << Str << " to hash.\n"); Hash.update(Str); Hash.update(makeArrayRef((uint8_t)'\0')); } @@ -53,7 +53,7 @@ void DIEHash::addString(StringRef Str) { /// Adds the unsigned in \p Value to the hash encoded as a ULEB128. void DIEHash::addULEB128(uint64_t Value) { - DEBUG(dbgs() << "Adding ULEB128 " << Value << " to hash.\n"); + LLVM_DEBUG(dbgs() << "Adding ULEB128 " << Value << " to hash.\n"); do { uint8_t Byte = Value & 0x7f; Value >>= 7; @@ -64,7 +64,7 @@ void DIEHash::addULEB128(uint64_t Value) { } void DIEHash::addSLEB128(int64_t Value) { - DEBUG(dbgs() << "Adding ULEB128 " << Value << " to hash.\n"); + LLVM_DEBUG(dbgs() << "Adding ULEB128 " << Value << " to hash.\n"); bool More; do { uint8_t Byte = Value & 0x7f; @@ -80,7 +80,7 @@ void DIEHash::addSLEB128(int64_t Value) { /// Including \p Parent adds the context of Parent to the hash.. void DIEHash::addParentContext(const DIE &Parent) { - DEBUG(dbgs() << "Adding parent context to hash...\n"); + LLVM_DEBUG(dbgs() << "Adding parent context to hash...\n"); // [7.27.2] For each surrounding type or namespace beginning with the // outermost such construct... @@ -108,7 +108,7 @@ void DIEHash::addParentContext(const DIE &Parent) { // ... Then the name, taken from the DW_AT_name attribute. StringRef Name = getDIEStringAttr(Die, dwarf::DW_AT_name); - DEBUG(dbgs() << "... adding context: " << Name << "\n"); + LLVM_DEBUG(dbgs() << "... adding context: " << Name << "\n"); if (!Name.empty()) addString(Name); } @@ -118,9 +118,9 @@ void DIEHash::addParentContext(const DIE &Parent) { void DIEHash::collectAttributes(const DIE &Die, DIEAttrs &Attrs) { for (const auto &V : Die.values()) { - DEBUG(dbgs() << "Attribute: " - << dwarf::AttributeString(V.getAttribute()) - << " added.\n"); + LLVM_DEBUG(dbgs() << "Attribute: " + << dwarf::AttributeString(V.getAttribute()) + << " added.\n"); switch (V.getAttribute()) { #define HANDLE_DIE_HASH_ATTR(NAME) \ case dwarf::NAME: \ diff --git a/llvm/lib/CodeGen/AsmPrinter/DbgValueHistoryCalculator.cpp b/llvm/lib/CodeGen/AsmPrinter/DbgValueHistoryCalculator.cpp index daa045939ce..7e7b1c1d0c1 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DbgValueHistoryCalculator.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/DbgValueHistoryCalculator.cpp @@ -50,8 +50,8 @@ void DbgValueHistoryMap::startInstrRange(InlinedVariable Var, auto &Ranges = VarInstrRanges[Var]; if (!Ranges.empty() && Ranges.back().second == nullptr && Ranges.back().first->isIdenticalTo(MI)) { - DEBUG(dbgs() << "Coalescing identical DBG_VALUE entries:\n" - << "\t" << Ranges.back().first << "\t" << MI << "\n"); + LLVM_DEBUG(dbgs() << "Coalescing identical DBG_VALUE entries:\n" + << "\t" << Ranges.back().first << "\t" << MI << "\n"); return; } Ranges.push_back(std::make_pair(&MI, nullptr)); diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp index b16dc3c1759..19aeb60630c 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp @@ -1034,7 +1034,7 @@ DwarfDebug::buildLocationList(SmallVectorImpl<DebugLocEntry> &DebugLoc, EndLabel = getLabelBeforeInsn(std::next(I)->first); assert(EndLabel && "Forgot label after instruction ending a range!"); - DEBUG(dbgs() << "DotDebugLoc: " << *Begin << "\n"); + LLVM_DEBUG(dbgs() << "DotDebugLoc: " << *Begin << "\n"); auto Value = getDebugLocValue(Begin); DebugLocEntry Loc(StartLabel, EndLabel, Value); @@ -1063,7 +1063,7 @@ DwarfDebug::buildLocationList(SmallVectorImpl<DebugLocEntry> &DebugLoc, // Attempt to coalesce the ranges of two otherwise identical // DebugLocEntries. auto CurEntry = DebugLoc.rbegin(); - DEBUG({ + LLVM_DEBUG({ dbgs() << CurEntry->getValues().size() << " Values:\n"; for (auto &Value : CurEntry->getValues()) Value.dump(); diff --git a/llvm/lib/CodeGen/AtomicExpandPass.cpp b/llvm/lib/CodeGen/AtomicExpandPass.cpp index 7042bc99722..460e7055d9b 100644 --- a/llvm/lib/CodeGen/AtomicExpandPass.cpp +++ b/llvm/lib/CodeGen/AtomicExpandPass.cpp @@ -379,8 +379,8 @@ LoadInst *AtomicExpand::convertAtomicLoadToIntegerType(LoadInst *LI) { NewLI->setAlignment(LI->getAlignment()); NewLI->setVolatile(LI->isVolatile()); NewLI->setAtomic(LI->getOrdering(), LI->getSyncScopeID()); - DEBUG(dbgs() << "Replaced " << *LI << " with " << *NewLI << "\n"); - + LLVM_DEBUG(dbgs() << "Replaced " << *LI << " with " << *NewLI << "\n"); + Value *NewVal = Builder.CreateBitCast(NewLI, LI->getType()); LI->replaceAllUsesWith(NewVal); LI->eraseFromParent(); @@ -462,7 +462,7 @@ StoreInst *AtomicExpand::convertAtomicStoreToIntegerType(StoreInst *SI) { NewSI->setAlignment(SI->getAlignment()); NewSI->setVolatile(SI->isVolatile()); NewSI->setAtomic(SI->getOrdering(), SI->getSyncScopeID()); - DEBUG(dbgs() << "Replaced " << *SI << " with " << *NewSI << "\n"); + LLVM_DEBUG(dbgs() << "Replaced " << *SI << " with " << *NewSI << "\n"); SI->eraseFromParent(); return NewSI; } @@ -943,7 +943,7 @@ AtomicCmpXchgInst *AtomicExpand::convertCmpXchgToIntegerType(AtomicCmpXchgInst * CI->getSyncScopeID()); NewCI->setVolatile(CI->isVolatile()); NewCI->setWeak(CI->isWeak()); - DEBUG(dbgs() << "Replaced " << *CI << " with " << *NewCI << "\n"); + LLVM_DEBUG(dbgs() << "Replaced " << *CI << " with " << *NewCI << "\n"); Value *OldVal = Builder.CreateExtractValue(NewCI, 0); Value *Succ = Builder.CreateExtractValue(NewCI, 1); diff --git a/llvm/lib/CodeGen/BranchFolding.cpp b/llvm/lib/CodeGen/BranchFolding.cpp index 8db71130588..190dfc0e473 100644 --- a/llvm/lib/CodeGen/BranchFolding.cpp +++ b/llvm/lib/CodeGen/BranchFolding.cpp @@ -152,7 +152,7 @@ BranchFolder::BranchFolder(bool defaultEnableTailMerge, bool CommonHoist, void BranchFolder::RemoveDeadBlock(MachineBasicBlock *MBB) { assert(MBB->pred_empty() && "MBB must be dead!"); - DEBUG(dbgs() << "\nRemoving MBB: " << *MBB); + LLVM_DEBUG(dbgs() << "\nRemoving MBB: " << *MBB); MachineFunction *MF = MBB->getParent(); // drop all successors. @@ -650,9 +650,9 @@ ProfitableToMerge(MachineBasicBlock *MBB1, MachineBasicBlock *MBB2, CommonTailLen = ComputeCommonTailLength(MBB1, MBB2, I1, I2); if (CommonTailLen == 0) return false; - DEBUG(dbgs() << "Common tail length of " << printMBBReference(*MBB1) - << " and " << printMBBReference(*MBB2) << " is " << CommonTailLen - << '\n'); + LLVM_DEBUG(dbgs() << "Common tail length of " << printMBBReference(*MBB1) + << " and " << printMBBReference(*MBB2) << " is " + << CommonTailLen << '\n'); // It's almost always profitable to merge any number of non-terminator // instructions with the block that falls through into the common successor. @@ -807,8 +807,8 @@ bool BranchFolder::CreateCommonTailOnlyBlock(MachineBasicBlock *&PredBB, SameTails[commonTailIndex].getTailStartPos(); MachineBasicBlock *MBB = SameTails[commonTailIndex].getBlock(); - DEBUG(dbgs() << "\nSplitting " << printMBBReference(*MBB) << ", size " - << maxCommonTailLength); + LLVM_DEBUG(dbgs() << "\nSplitting " << printMBBReference(*MBB) << ", size " + << maxCommonTailLength); // If the split block unconditionally falls-thru to SuccBB, it will be // merged. In control flow terms it should then take SuccBB's name. e.g. If @@ -817,7 +817,7 @@ bool BranchFolder::CreateCommonTailOnlyBlock(MachineBasicBlock *&PredBB, SuccBB->getBasicBlock() : MBB->getBasicBlock(); MachineBasicBlock *newMBB = SplitMBBAt(*MBB, BBI, BB); if (!newMBB) { - DEBUG(dbgs() << "... failed!"); + LLVM_DEBUG(dbgs() << "... failed!"); return false; } @@ -956,18 +956,19 @@ bool BranchFolder::TryTailMergeBlocks(MachineBasicBlock *SuccBB, unsigned MinCommonTailLength) { bool MadeChange = false; - DEBUG(dbgs() << "\nTryTailMergeBlocks: "; - for (unsigned i = 0, e = MergePotentials.size(); i != e; ++i) dbgs() - << printMBBReference(*MergePotentials[i].getBlock()) - << (i == e - 1 ? "" : ", "); - dbgs() << "\n"; if (SuccBB) { - dbgs() << " with successor " << printMBBReference(*SuccBB) << '\n'; - if (PredBB) - dbgs() << " which has fall-through from " - << printMBBReference(*PredBB) << "\n"; - } dbgs() << "Looking for common tails of at least " - << MinCommonTailLength << " instruction" - << (MinCommonTailLength == 1 ? "" : "s") << '\n';); + LLVM_DEBUG( + dbgs() << "\nTryTailMergeBlocks: "; + for (unsigned i = 0, e = MergePotentials.size(); i != e; ++i) dbgs() + << printMBBReference(*MergePotentials[i].getBlock()) + << (i == e - 1 ? "" : ", "); + dbgs() << "\n"; if (SuccBB) { + dbgs() << " with successor " << printMBBReference(*SuccBB) << '\n'; + if (PredBB) + dbgs() << " which has fall-through from " + << printMBBReference(*PredBB) << "\n"; + } dbgs() << "Looking for common tails of at least " + << MinCommonTailLength << " instruction" + << (MinCommonTailLength == 1 ? "" : "s") << '\n';); // Sort by hash value so that blocks with identical end sequences sort // together. @@ -1047,19 +1048,19 @@ bool BranchFolder::TryTailMergeBlocks(MachineBasicBlock *SuccBB, // MBB is common tail. Adjust all other BB's to jump to this one. // Traversal must be forwards so erases work. - DEBUG(dbgs() << "\nUsing common tail in " << printMBBReference(*MBB) - << " for "); + LLVM_DEBUG(dbgs() << "\nUsing common tail in " << printMBBReference(*MBB) + << " for "); for (unsigned int i=0, e = SameTails.size(); i != e; ++i) { if (commonTailIndex == i) continue; - DEBUG(dbgs() << printMBBReference(*SameTails[i].getBlock()) - << (i == e - 1 ? "" : ", ")); + LLVM_DEBUG(dbgs() << printMBBReference(*SameTails[i].getBlock()) + << (i == e - 1 ? "" : ", ")); // Hack the end off BB i, making it jump to BB commonTailIndex instead. replaceTailWithBranchTo(SameTails[i].getTailStartPos(), *MBB); // BB i is no longer a predecessor of SuccBB; remove it from the worklist. MergePotentials.erase(SameTails[i].getMPIter()); } - DEBUG(dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "\n"); // We leave commonTailIndex in the worklist in case there are other blocks // that match it with a smaller number of instructions. MadeChange = true; @@ -1363,7 +1364,8 @@ static void copyDebugInfoToPredecessor(const TargetInstrInfo *TII, for (MachineInstr &MI : MBB.instrs()) if (MI.isDebugValue()) { TII->duplicate(PredMBB, InsertBefore, MI); - DEBUG(dbgs() << "Copied debug value from empty block to pred: " << MI); + LLVM_DEBUG(dbgs() << "Copied debug value from empty block to pred: " + << MI); } } @@ -1374,7 +1376,8 @@ static void copyDebugInfoToSuccessor(const TargetInstrInfo *TII, for (MachineInstr &MI : MBB.instrs()) if (MI.isDebugValue()) { TII->duplicate(SuccMBB, InsertBefore, MI); - DEBUG(dbgs() << "Copied debug value from empty block to succ: " << MI); + LLVM_DEBUG(dbgs() << "Copied debug value from empty block to succ: " + << MI); } } @@ -1489,8 +1492,8 @@ ReoptimizeBlock: if (PriorCond.empty() && !PriorTBB && MBB->pred_size() == 1 && PrevBB.succ_size() == 1 && !MBB->hasAddressTaken() && !MBB->isEHPad()) { - DEBUG(dbgs() << "\nMerging into block: " << PrevBB - << "From MBB: " << *MBB); + LLVM_DEBUG(dbgs() << "\nMerging into block: " << PrevBB + << "From MBB: " << *MBB); // Remove redundant DBG_VALUEs first. if (PrevBB.begin() != PrevBB.end()) { MachineBasicBlock::iterator PrevBBIter = PrevBB.end(); @@ -1576,8 +1579,8 @@ ReoptimizeBlock: // Reverse the branch so we will fall through on the previous true cond. SmallVector<MachineOperand, 4> NewPriorCond(PriorCond); if (!TII->reverseBranchCondition(NewPriorCond)) { - DEBUG(dbgs() << "\nMoving MBB: " << *MBB - << "To make fallthrough to: " << *PriorTBB << "\n"); + LLVM_DEBUG(dbgs() << "\nMoving MBB: " << *MBB + << "To make fallthrough to: " << *PriorTBB << "\n"); DebugLoc dl = getBranchDebugLoc(PrevBB); TII->removeBranch(PrevBB); diff --git a/llvm/lib/CodeGen/BranchRelaxation.cpp b/llvm/lib/CodeGen/BranchRelaxation.cpp index 744612261c8..3866f51e93c 100644 --- a/llvm/lib/CodeGen/BranchRelaxation.cpp +++ b/llvm/lib/CodeGen/BranchRelaxation.cpp @@ -288,10 +288,11 @@ bool BranchRelaxation::isBlockInRange( if (TII->isBranchOffsetInRange(MI.getOpcode(), DestOffset - BrOffset)) return true; - DEBUG(dbgs() << "Out of range branch to destination " - << printMBBReference(DestBB) << " from " - << printMBBReference(*MI.getParent()) << " to " << DestOffset - << " offset " << DestOffset - BrOffset << '\t' << MI); + LLVM_DEBUG(dbgs() << "Out of range branch to destination " + << printMBBReference(DestBB) << " from " + << printMBBReference(*MI.getParent()) << " to " + << DestOffset << " offset " << DestOffset - BrOffset << '\t' + << MI); return false; } @@ -360,8 +361,9 @@ bool BranchRelaxation::fixupConditionalBranch(MachineInstr &MI) { // => // bne L2 // b L1 - DEBUG(dbgs() << " Invert condition and swap " - "its destination with " << MBB->back()); + LLVM_DEBUG(dbgs() << " Invert condition and swap " + "its destination with " + << MBB->back()); removeBranch(MBB); insertBranch(MBB, FBB, TBB, Cond); @@ -384,9 +386,9 @@ bool BranchRelaxation::fixupConditionalBranch(MachineInstr &MI) { // just created), so we can use the inverted the condition. MachineBasicBlock &NextBB = *std::next(MachineFunction::iterator(MBB)); - DEBUG(dbgs() << " Insert B to " << printMBBReference(*TBB) - << ", invert condition and change dest. to " - << printMBBReference(NextBB) << '\n'); + LLVM_DEBUG(dbgs() << " Insert B to " << printMBBReference(*TBB) + << ", invert condition and change dest. to " + << printMBBReference(NextBB) << '\n'); removeBranch(MBB); // Insert a new conditional branch and a new unconditional branch. @@ -397,8 +399,8 @@ bool BranchRelaxation::fixupConditionalBranch(MachineInstr &MI) { } // Branch cond can't be inverted. // In this case we always add a block after the MBB. - DEBUG(dbgs() << " The branch condition can't be inverted. " - << " Insert a new BB after " << MBB->back()); + LLVM_DEBUG(dbgs() << " The branch condition can't be inverted. " + << " Insert a new BB after " << MBB->back()); if (!FBB) FBB = &(*std::next(MachineFunction::iterator(MBB))); @@ -417,11 +419,12 @@ bool BranchRelaxation::fixupConditionalBranch(MachineInstr &MI) { NewBB = createNewBlockAfter(*MBB); insertUncondBranch(NewBB, TBB); - DEBUG(dbgs() << " Insert cond B to the new BB " << printMBBReference(*NewBB) - << " Keep the exiting condition.\n" - << " Insert B to " << printMBBReference(*FBB) << ".\n" - << " In the new BB: Insert B to " - << printMBBReference(*TBB) << ".\n"); + LLVM_DEBUG(dbgs() << " Insert cond B to the new BB " + << printMBBReference(*NewBB) + << " Keep the exiting condition.\n" + << " Insert B to " << printMBBReference(*FBB) << ".\n" + << " In the new BB: Insert B to " + << printMBBReference(*TBB) << ".\n"); // Update the successor lists according to the transformation to follow. MBB->replaceSuccessor(TBB, NewBB); @@ -541,7 +544,7 @@ bool BranchRelaxation::relaxBranchInstructions() { bool BranchRelaxation::runOnMachineFunction(MachineFunction &mf) { MF = &mf; - DEBUG(dbgs() << "***** BranchRelaxation *****\n"); + LLVM_DEBUG(dbgs() << "***** BranchRelaxation *****\n"); const TargetSubtargetInfo &ST = MF->getSubtarget(); TII = ST.getInstrInfo(); @@ -558,7 +561,7 @@ bool BranchRelaxation::runOnMachineFunction(MachineFunction &mf) { // sizes of each block. scanFunction(); - DEBUG(dbgs() << " Basic blocks before relaxation\n"; dumpBBs();); + LLVM_DEBUG(dbgs() << " Basic blocks before relaxation\n"; dumpBBs();); bool MadeChange = false; while (relaxBranchInstructions()) @@ -567,7 +570,7 @@ bool BranchRelaxation::runOnMachineFunction(MachineFunction &mf) { // After a while, this might be made debug-only, but it is not expensive. verify(); - DEBUG(dbgs() << " Basic blocks after relaxation\n\n"; dumpBBs()); + LLVM_DEBUG(dbgs() << " Basic blocks after relaxation\n\n"; dumpBBs()); BlockInfo.clear(); diff --git a/llvm/lib/CodeGen/BreakFalseDeps.cpp b/llvm/lib/CodeGen/BreakFalseDeps.cpp index 2e6d7275c7e..7f098cb7165 100644 --- a/llvm/lib/CodeGen/BreakFalseDeps.cpp +++ b/llvm/lib/CodeGen/BreakFalseDeps.cpp @@ -165,13 +165,13 @@ bool BreakFalseDeps::shouldBreakDependence(MachineInstr *MI, unsigned OpIdx, unsigned Pref) { unsigned reg = MI->getOperand(OpIdx).getReg(); unsigned Clearance = RDA->getClearance(MI, reg); - DEBUG(dbgs() << "Clearance: " << Clearance << ", want " << Pref); + LLVM_DEBUG(dbgs() << "Clearance: " << Clearance << ", want " << Pref); if (Pref > Clearance) { - DEBUG(dbgs() << ": Break dependency.\n"); + LLVM_DEBUG(dbgs() << ": Break dependency.\n"); return true; } - DEBUG(dbgs() << ": OK .\n"); + LLVM_DEBUG(dbgs() << ": OK .\n"); return false; } @@ -260,7 +260,7 @@ bool BreakFalseDeps::runOnMachineFunction(MachineFunction &mf) { RegClassInfo.runOnMachineFunction(mf); - DEBUG(dbgs() << "********** BREAK FALSE DEPENDENCIES **********\n"); + LLVM_DEBUG(dbgs() << "********** BREAK FALSE DEPENDENCIES **********\n"); // Traverse the basic blocks. for (MachineBasicBlock &MBB : mf) { diff --git a/llvm/lib/CodeGen/CalcSpillWeights.cpp b/llvm/lib/CodeGen/CalcSpillWeights.cpp index 5a9026926d6..57541182cab 100644 --- a/llvm/lib/CodeGen/CalcSpillWeights.cpp +++ b/llvm/lib/CodeGen/CalcSpillWeights.cpp @@ -35,8 +35,8 @@ void llvm::calculateSpillWeightsAndHints(LiveIntervals &LIS, const MachineLoopInfo &MLI, const MachineBlockFrequencyInfo &MBFI, VirtRegAuxInfo::NormalizingFn norm) { - DEBUG(dbgs() << "********** Compute Spill Weights **********\n" - << "********** Function: " << MF.getName() << '\n'); + LLVM_DEBUG(dbgs() << "********** Compute Spill Weights **********\n" + << "********** Function: " << MF.getName() << '\n'); MachineRegisterInfo &MRI = MF.getRegInfo(); VirtRegAuxInfo VRAI(MF, LIS, VRM, MLI, MBFI, norm); diff --git a/llvm/lib/CodeGen/CodeGenPrepare.cpp b/llvm/lib/CodeGen/CodeGenPrepare.cpp index 87cb2f9a19c..92996eb3fee 100644 --- a/llvm/lib/CodeGen/CodeGenPrepare.cpp +++ b/llvm/lib/CodeGen/CodeGenPrepare.cpp @@ -528,7 +528,7 @@ bool CodeGenPrepare::eliminateFallThrough(Function &F) { BranchInst *Term = dyn_cast<BranchInst>(SinglePred->getTerminator()); if (Term && !Term->isConditional()) { Changed = true; - DEBUG(dbgs() << "To merge:\n"<< *SinglePred << "\n\n\n"); + LLVM_DEBUG(dbgs() << "To merge:\n" << *SinglePred << "\n\n\n"); // Remember if SinglePred was the entry block of the function. // If so, we will need to move BB back to the entry position. bool isEntry = SinglePred == &SinglePred->getParent()->getEntryBlock(); @@ -755,7 +755,8 @@ void CodeGenPrepare::eliminateMostlyEmptyBlock(BasicBlock *BB) { BranchInst *BI = cast<BranchInst>(BB->getTerminator()); BasicBlock *DestBB = BI->getSuccessor(0); - DEBUG(dbgs() << "MERGING MOSTLY EMPTY BLOCKS - BEFORE:\n" << *BB << *DestBB); + LLVM_DEBUG(dbgs() << "MERGING MOSTLY EMPTY BLOCKS - BEFORE:\n" + << *BB << *DestBB); // If the destination block has a single pred, then this is a trivial edge, // just collapse it. @@ -769,7 +770,7 @@ void CodeGenPrepare::eliminateMostlyEmptyBlock(BasicBlock *BB) { if (isEntry && BB != &BB->getParent()->getEntryBlock()) BB->moveBefore(&BB->getParent()->getEntryBlock()); - DEBUG(dbgs() << "AFTER:\n" << *DestBB << "\n\n\n"); + LLVM_DEBUG(dbgs() << "AFTER:\n" << *DestBB << "\n\n\n"); return; } } @@ -807,7 +808,7 @@ void CodeGenPrepare::eliminateMostlyEmptyBlock(BasicBlock *BB) { BB->eraseFromParent(); ++NumBlocksElim; - DEBUG(dbgs() << "AFTER:\n" << *DestBB << "\n\n\n"); + LLVM_DEBUG(dbgs() << "AFTER:\n" << *DestBB << "\n\n\n"); } // Computes a map of base pointer relocation instructions to corresponding @@ -1272,8 +1273,8 @@ static bool sinkAndCmp0Expression(Instruction *AndI, if (!TLI.isMaskAndCmp0FoldingBeneficial(*AndI)) return false; - DEBUG(dbgs() << "found 'and' feeding only icmp 0;\n"); - DEBUG(AndI->getParent()->dump()); + LLVM_DEBUG(dbgs() << "found 'and' feeding only icmp 0;\n"); + LLVM_DEBUG(AndI->getParent()->dump()); // Push the 'and' into the same block as the icmp 0. There should only be // one (icmp (and, 0)) in each block, since CSE/GVN should have removed any @@ -1286,7 +1287,7 @@ static bool sinkAndCmp0Expression(Instruction *AndI, // Preincrement use iterator so we don't invalidate it. ++UI; - DEBUG(dbgs() << "sinking 'and' use: " << *User << "\n"); + LLVM_DEBUG(dbgs() << "sinking 'and' use: " << *User << "\n"); // Keep the 'and' in the same place if the use is already in the same block. Instruction *InsertPt = @@ -1300,7 +1301,7 @@ static bool sinkAndCmp0Expression(Instruction *AndI, // Replace a use of the 'and' with a use of the new 'and'. TheUse = InsertedAnd; ++NumAndUses; - DEBUG(User->getParent()->dump()); + LLVM_DEBUG(User->getParent()->dump()); } // We removed all uses, nuke the and. @@ -2130,13 +2131,14 @@ class TypePromotionTransaction { /// Move \p Inst before \p Before. InstructionMoveBefore(Instruction *Inst, Instruction *Before) : TypePromotionAction(Inst), Position(Inst) { - DEBUG(dbgs() << "Do: move: " << *Inst << "\nbefore: " << *Before << "\n"); + LLVM_DEBUG(dbgs() << "Do: move: " << *Inst << "\nbefore: " << *Before + << "\n"); Inst->moveBefore(Before); } /// Move the instruction back to its original position. void undo() override { - DEBUG(dbgs() << "Undo: moveBefore: " << *Inst << "\n"); + LLVM_DEBUG(dbgs() << "Undo: moveBefore: " << *Inst << "\n"); Position.insert(Inst); } }; @@ -2153,18 +2155,18 @@ class TypePromotionTransaction { /// Set \p Idx operand of \p Inst with \p NewVal. OperandSetter(Instruction *Inst, unsigned Idx, Value *NewVal) : TypePromotionAction(Inst), Idx(Idx) { - DEBUG(dbgs() << "Do: setOperand: " << Idx << "\n" - << "for:" << *Inst << "\n" - << "with:" << *NewVal << "\n"); + LLVM_DEBUG(dbgs() << "Do: setOperand: " << Idx << "\n" + << "for:" << *Inst << "\n" + << "with:" << *NewVal << "\n"); Origin = Inst->getOperand(Idx); Inst->setOperand(Idx, NewVal); } /// Restore the original value of the instruction. void undo() override { - DEBUG(dbgs() << "Undo: setOperand:" << Idx << "\n" - << "for: " << *Inst << "\n" - << "with: " << *Origin << "\n"); + LLVM_DEBUG(dbgs() << "Undo: setOperand:" << Idx << "\n" + << "for: " << *Inst << "\n" + << "with: " << *Origin << "\n"); Inst->setOperand(Idx, Origin); } }; @@ -2178,7 +2180,7 @@ class TypePromotionTransaction { public: /// Remove \p Inst from the uses of the operands of \p Inst. OperandsHider(Instruction *Inst) : TypePromotionAction(Inst) { - DEBUG(dbgs() << "Do: OperandsHider: " << *Inst << "\n"); + LLVM_DEBUG(dbgs() << "Do: OperandsHider: " << *Inst << "\n"); unsigned NumOpnds = Inst->getNumOperands(); OriginalValues.reserve(NumOpnds); for (unsigned It = 0; It < NumOpnds; ++It) { @@ -2194,7 +2196,7 @@ class TypePromotionTransaction { /// Restore the original list of uses. void undo() override { - DEBUG(dbgs() << "Undo: OperandsHider: " << *Inst << "\n"); + LLVM_DEBUG(dbgs() << "Undo: OperandsHider: " << *Inst << "\n"); for (unsigned It = 0, EndIt = OriginalValues.size(); It != EndIt; ++It) Inst->setOperand(It, OriginalValues[It]); } @@ -2211,7 +2213,7 @@ class TypePromotionTransaction { TruncBuilder(Instruction *Opnd, Type *Ty) : TypePromotionAction(Opnd) { IRBuilder<> Builder(Opnd); Val = Builder.CreateTrunc(Opnd, Ty, "promoted"); - DEBUG(dbgs() << "Do: TruncBuilder: " << *Val << "\n"); + LLVM_DEBUG(dbgs() << "Do: TruncBuilder: " << *Val << "\n"); } /// Get the built value. @@ -2219,7 +2221,7 @@ class TypePromotionTransaction { /// Remove the built instruction. void undo() override { - DEBUG(dbgs() << "Undo: TruncBuilder: " << *Val << "\n"); + LLVM_DEBUG(dbgs() << "Undo: TruncBuilder: " << *Val << "\n"); if (Instruction *IVal = dyn_cast<Instruction>(Val)) IVal->eraseFromParent(); } @@ -2237,7 +2239,7 @@ class TypePromotionTransaction { : TypePromotionAction(InsertPt) { IRBuilder<> Builder(InsertPt); Val = Builder.CreateSExt(Opnd, Ty, "promoted"); - DEBUG(dbgs() << "Do: SExtBuilder: " << *Val << "\n"); + LLVM_DEBUG(dbgs() << "Do: SExtBuilder: " << *Val << "\n"); } /// Get the built value. @@ -2245,7 +2247,7 @@ class TypePromotionTransaction { /// Remove the built instruction. void undo() override { - DEBUG(dbgs() << "Undo: SExtBuilder: " << *Val << "\n"); + LLVM_DEBUG(dbgs() << "Undo: SExtBuilder: " << *Val << "\n"); if (Instruction *IVal = dyn_cast<Instruction>(Val)) IVal->eraseFromParent(); } @@ -2263,7 +2265,7 @@ class TypePromotionTransaction { : TypePromotionAction(InsertPt) { IRBuilder<> Builder(InsertPt); Val = Builder.CreateZExt(Opnd, Ty, "promoted"); - DEBUG(dbgs() << "Do: ZExtBuilder: " << *Val << "\n"); + LLVM_DEBUG(dbgs() << "Do: ZExtBuilder: " << *Val << "\n"); } /// Get the built value. @@ -2271,7 +2273,7 @@ class TypePromotionTransaction { /// Remove the built instruction. void undo() override { - DEBUG(dbgs() << "Undo: ZExtBuilder: " << *Val << "\n"); + LLVM_DEBUG(dbgs() << "Undo: ZExtBuilder: " << *Val << "\n"); if (Instruction *IVal = dyn_cast<Instruction>(Val)) IVal->eraseFromParent(); } @@ -2286,15 +2288,15 @@ class TypePromotionTransaction { /// Mutate the type of \p Inst into \p NewTy. TypeMutator(Instruction *Inst, Type *NewTy) : TypePromotionAction(Inst), OrigTy(Inst->getType()) { - DEBUG(dbgs() << "Do: MutateType: " << *Inst << " with " << *NewTy - << "\n"); + LLVM_DEBUG(dbgs() << "Do: MutateType: " << *Inst << " with " << *NewTy + << "\n"); Inst->mutateType(NewTy); } /// Mutate the instruction back to its original type. void undo() override { - DEBUG(dbgs() << "Undo: MutateType: " << *Inst << " with " << *OrigTy - << "\n"); + LLVM_DEBUG(dbgs() << "Undo: MutateType: " << *Inst << " with " << *OrigTy + << "\n"); Inst->mutateType(OrigTy); } }; @@ -2321,8 +2323,8 @@ class TypePromotionTransaction { public: /// Replace all the use of \p Inst by \p New. UsesReplacer(Instruction *Inst, Value *New) : TypePromotionAction(Inst) { - DEBUG(dbgs() << "Do: UsersReplacer: " << *Inst << " with " << *New - << "\n"); + LLVM_DEBUG(dbgs() << "Do: UsersReplacer: " << *Inst << " with " << *New + << "\n"); // Record the original uses. for (Use &U : Inst->uses()) { Instruction *UserI = cast<Instruction>(U.getUser()); @@ -2334,7 +2336,7 @@ class TypePromotionTransaction { /// Reassign the original uses of Inst to Inst. void undo() override { - DEBUG(dbgs() << "Undo: UsersReplacer: " << *Inst << "\n"); + LLVM_DEBUG(dbgs() << "Undo: UsersReplacer: " << *Inst << "\n"); for (use_iterator UseIt = OriginalUses.begin(), EndIt = OriginalUses.end(); UseIt != EndIt; ++UseIt) { @@ -2369,7 +2371,7 @@ class TypePromotionTransaction { RemovedInsts(RemovedInsts) { if (New) Replacer = new UsesReplacer(Inst, New); - DEBUG(dbgs() << "Do: InstructionRemover: " << *Inst << "\n"); + LLVM_DEBUG(dbgs() << "Do: InstructionRemover: " << *Inst << "\n"); RemovedInsts.insert(Inst); /// The instructions removed here will be freed after completing /// optimizeBlock() for all blocks as we need to keep track of the @@ -2382,7 +2384,7 @@ class TypePromotionTransaction { /// Resurrect the instruction and reassign it to the proper uses if /// new value was provided when build this action. void undo() override { - DEBUG(dbgs() << "Undo: InstructionRemover: " << *Inst << "\n"); + LLVM_DEBUG(dbgs() << "Undo: InstructionRemover: " << *Inst << "\n"); Inserter.insert(Inst); if (Replacer) Replacer->undo(); @@ -3592,19 +3594,19 @@ Value *TypePromotionHelper::promoteOperandForOther( // Step #3. Instruction *ExtForOpnd = Ext; - DEBUG(dbgs() << "Propagate Ext to operands\n"); + LLVM_DEBUG(dbgs() << "Propagate Ext to operands\n"); for (int OpIdx = 0, EndOpIdx = ExtOpnd->getNumOperands(); OpIdx != EndOpIdx; ++OpIdx) { - DEBUG(dbgs() << "Operand:\n" << *(ExtOpnd->getOperand(OpIdx)) << '\n'); + LLVM_DEBUG(dbgs() << "Operand:\n" << *(ExtOpnd->getOperand(OpIdx)) << '\n'); if (ExtOpnd->getOperand(OpIdx)->getType() == Ext->getType() || !shouldExtOperand(ExtOpnd, OpIdx)) { - DEBUG(dbgs() << "No need to propagate\n"); + LLVM_DEBUG(dbgs() << "No need to propagate\n"); continue; } // Check if we can statically extend the operand. Value *Opnd = ExtOpnd->getOperand(OpIdx); if (const ConstantInt *Cst = dyn_cast<ConstantInt>(Opnd)) { - DEBUG(dbgs() << "Statically extend\n"); + LLVM_DEBUG(dbgs() << "Statically extend\n"); unsigned BitWidth = Ext->getType()->getIntegerBitWidth(); APInt CstVal = IsSExt ? Cst->getValue().sext(BitWidth) : Cst->getValue().zext(BitWidth); @@ -3613,7 +3615,7 @@ Value *TypePromotionHelper::promoteOperandForOther( } // UndefValue are typed, so we have to statically sign extend them. if (isa<UndefValue>(Opnd)) { - DEBUG(dbgs() << "Statically extend\n"); + LLVM_DEBUG(dbgs() << "Statically extend\n"); TPT.setOperand(ExtOpnd, OpIdx, UndefValue::get(Ext->getType())); continue; } @@ -3622,7 +3624,7 @@ Value *TypePromotionHelper::promoteOperandForOther( // Check if Ext was reused to extend an operand. if (!ExtForOpnd) { // If yes, create a new one. - DEBUG(dbgs() << "More operands to ext\n"); + LLVM_DEBUG(dbgs() << "More operands to ext\n"); Value *ValForExtOpnd = IsSExt ? TPT.createSExt(Ext, Opnd, Ext->getType()) : TPT.createZExt(Ext, Opnd, Ext->getType()); if (!isa<Instruction>(ValForExtOpnd)) { @@ -3643,7 +3645,7 @@ Value *TypePromotionHelper::promoteOperandForOther( ExtForOpnd = nullptr; } if (ExtForOpnd == Ext) { - DEBUG(dbgs() << "Extension is useless now\n"); + LLVM_DEBUG(dbgs() << "Extension is useless now\n"); TPT.eraseInstruction(Ext); } return ExtOpnd; @@ -3659,7 +3661,8 @@ Value *TypePromotionHelper::promoteOperandForOther( /// \return True if the promotion is profitable, false otherwise. bool AddressingModeMatcher::isPromotionProfitable( unsigned NewCost, unsigned OldCost, Value *PromotedOperand) const { - DEBUG(dbgs() << "OldCost: " << OldCost << "\tNewCost: " << NewCost << '\n'); + LLVM_DEBUG(dbgs() << "OldCost: " << OldCost << "\tNewCost: " << NewCost + << '\n'); // The cost of the new extensions is greater than the cost of the // old extension plus what we folded. // This is not profitable. @@ -3930,7 +3933,7 @@ bool AddressingModeMatcher::matchOperationAddr(User *AddrInst, unsigned Opcode, PromotedOperand)) { AddrMode = BackupAddrMode; AddrModeInsts.resize(OldSize); - DEBUG(dbgs() << "Sign extension does not pay off: rollback\n"); + LLVM_DEBUG(dbgs() << "Sign extension does not pay off: rollback\n"); TPT.rollback(LastKnownGood); return false; } @@ -4393,7 +4396,8 @@ bool CodeGenPrepare::optimizeMemoryInst(Instruction *MemoryInst, Value *Addr, if (!PhiOrSelectSeen && none_of(AddrModeInsts, [&](Value *V) { return IsNonLocalValue(V, MemoryInst->getParent()); })) { - DEBUG(dbgs() << "CGP: Found local addrmode: " << AddrMode << "\n"); + LLVM_DEBUG(dbgs() << "CGP: Found local addrmode: " << AddrMode + << "\n"); return false; } @@ -4412,16 +4416,16 @@ bool CodeGenPrepare::optimizeMemoryInst(Instruction *MemoryInst, Value *Addr, Value * SunkAddr = SunkAddrVH.pointsToAliveValue() ? SunkAddrVH : nullptr; if (SunkAddr) { - DEBUG(dbgs() << "CGP: Reusing nonlocal addrmode: " << AddrMode << " for " - << *MemoryInst << "\n"); + LLVM_DEBUG(dbgs() << "CGP: Reusing nonlocal addrmode: " << AddrMode + << " for " << *MemoryInst << "\n"); if (SunkAddr->getType() != Addr->getType()) SunkAddr = Builder.CreatePointerCast(SunkAddr, Addr->getType()); } else if (AddrSinkUsingGEPs || (!AddrSinkUsingGEPs.getNumOccurrences() && TM && TTI->useAA())) { // By default, we use the GEP-based method when AA is used later. This // prevents new inttoptr/ptrtoint pairs from degrading AA capabilities. - DEBUG(dbgs() << "CGP: SINKING nonlocal addrmode: " << AddrMode << " for " - << *MemoryInst << "\n"); + LLVM_DEBUG(dbgs() << "CGP: SINKING nonlocal addrmode: " << AddrMode + << " for " << *MemoryInst << "\n"); Type *IntPtrTy = DL->getIntPtrType(Addr->getType()); Value *ResultPtr = nullptr, *ResultIndex = nullptr; @@ -4560,8 +4564,8 @@ bool CodeGenPrepare::optimizeMemoryInst(Instruction *MemoryInst, Value *Addr, DL->isNonIntegralPointerType(AddrMode.BaseGV->getType()))) return false; - DEBUG(dbgs() << "CGP: SINKING nonlocal addrmode: " << AddrMode << " for " - << *MemoryInst << "\n"); + LLVM_DEBUG(dbgs() << "CGP: SINKING nonlocal addrmode: " << AddrMode + << " for " << *MemoryInst << "\n"); Type *IntPtrTy = DL->getIntPtrType(Addr->getType()); Value *Result = nullptr; @@ -5927,8 +5931,9 @@ class VectorPromoteHelper { VectorCost += TTI.getArithmeticInstrCost(Inst->getOpcode(), PromotedType, Arg0OVK, Arg1OVK); } - DEBUG(dbgs() << "Estimated cost of computation to be promoted:\nScalar: " - << ScalarCost << "\nVector: " << VectorCost << '\n'); + LLVM_DEBUG( + dbgs() << "Estimated cost of computation to be promoted:\nScalar: " + << ScalarCost << "\nVector: " << VectorCost << '\n'); return ScalarCost > VectorCost; } @@ -6133,35 +6138,36 @@ bool CodeGenPrepare::optimizeExtractElementInst(Instruction *Inst) { // => we would need to check that we are moving it at a cheaper place and // we do not do that for now. BasicBlock *Parent = Inst->getParent(); - DEBUG(dbgs() << "Found an interesting transition: " << *Inst << '\n'); + LLVM_DEBUG(dbgs() << "Found an interesting transition: " << *Inst << '\n'); VectorPromoteHelper VPH(*DL, *TLI, *TTI, Inst, CombineCost); // If the transition has more than one use, assume this is not going to be // beneficial. while (Inst->hasOneUse()) { Instruction *ToBePromoted = cast<Instruction>(*Inst->user_begin()); - DEBUG(dbgs() << "Use: " << *ToBePromoted << '\n'); + LLVM_DEBUG(dbgs() << "Use: " << *ToBePromoted << '\n'); if (ToBePromoted->getParent() != Parent) { - DEBUG(dbgs() << "Instruction to promote is in a different block (" - << ToBePromoted->getParent()->getName() - << ") than the transition (" << Parent->getName() << ").\n"); + LLVM_DEBUG(dbgs() << "Instruction to promote is in a different block (" + << ToBePromoted->getParent()->getName() + << ") than the transition (" << Parent->getName() + << ").\n"); return false; } if (VPH.canCombine(ToBePromoted)) { - DEBUG(dbgs() << "Assume " << *Inst << '\n' - << "will be combined with: " << *ToBePromoted << '\n'); + LLVM_DEBUG(dbgs() << "Assume " << *Inst << '\n' + << "will be combined with: " << *ToBePromoted << '\n'); VPH.recordCombineInstruction(ToBePromoted); bool Changed = VPH.promote(); NumStoreExtractExposed += Changed; return Changed; } - DEBUG(dbgs() << "Try promoting.\n"); + LLVM_DEBUG(dbgs() << "Try promoting.\n"); if (!VPH.canPromote(ToBePromoted) || !VPH.shouldPromote(ToBePromoted)) return false; - DEBUG(dbgs() << "Promoting is possible... Enqueue for promotion!\n"); + LLVM_DEBUG(dbgs() << "Promoting is possible... Enqueue for promotion!\n"); VPH.enqueueForPromotion(ToBePromoted); Inst = ToBePromoted; @@ -6656,7 +6662,8 @@ bool CodeGenPrepare::placeDbgValues(Function &F) { // after it. if (isa<PHINode>(VI) && VI->getParent()->getTerminator()->isEHPad()) continue; - DEBUG(dbgs() << "Moving Debug Value before :\n" << *DVI << ' ' << *VI); + LLVM_DEBUG(dbgs() << "Moving Debug Value before :\n" + << *DVI << ' ' << *VI); DVI->removeFromParent(); if (isa<PHINode>(VI)) DVI->insertBefore(&*VI->getParent()->getFirstInsertionPt()); @@ -6735,7 +6742,7 @@ bool CodeGenPrepare::splitBranchCondition(Function &F) { !match(Cond2, m_CombineOr(m_Cmp(), m_BinOp())) ) continue; - DEBUG(dbgs() << "Before branch condition splitting\n"; BB.dump()); + LLVM_DEBUG(dbgs() << "Before branch condition splitting\n"; BB.dump()); // Create a new BB. auto TmpBB = @@ -6863,8 +6870,8 @@ bool CodeGenPrepare::splitBranchCondition(Function &F) { MadeChange = true; - DEBUG(dbgs() << "After branch condition splitting\n"; BB.dump(); - TmpBB->dump()); + LLVM_DEBUG(dbgs() << "After branch condition splitting\n"; BB.dump(); + TmpBB->dump()); } return MadeChange; } diff --git a/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp b/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp index 608fc4ba89b..840e5ede644 100644 --- a/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp +++ b/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp @@ -461,14 +461,14 @@ BreakAntiDependencies(const std::vector<SUnit> &SUnits, #ifndef NDEBUG { - DEBUG(dbgs() << "Critical path has total latency " - << (Max->getDepth() + Max->Latency) << "\n"); - DEBUG(dbgs() << "Available regs:"); + LLVM_DEBUG(dbgs() << "Critical path has total latency " + << (Max->getDepth() + Max->Latency) << "\n"); + LLVM_DEBUG(dbgs() << "Available regs:"); for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) { if (KillIndices[Reg] == ~0u) - DEBUG(dbgs() << " " << printReg(Reg, TRI)); + LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI)); } - DEBUG(dbgs() << '\n'); + LLVM_DEBUG(dbgs() << '\n'); } #endif @@ -645,10 +645,10 @@ BreakAntiDependencies(const std::vector<SUnit> &SUnits, AntiDepReg, LastNewReg[AntiDepReg], RC, ForbidRegs)) { - DEBUG(dbgs() << "Breaking anti-dependence edge on " - << printReg(AntiDepReg, TRI) << " with " - << RegRefs.count(AntiDepReg) << " references" - << " using " << printReg(NewReg, TRI) << "!\n"); + LLVM_DEBUG(dbgs() << "Breaking anti-dependence edge on " + << printReg(AntiDepReg, TRI) << " with " + << RegRefs.count(AntiDepReg) << " references" + << " using " << printReg(NewReg, TRI) << "!\n"); // Update the references to the old register to refer to the new // register. diff --git a/llvm/lib/CodeGen/DFAPacketizer.cpp b/llvm/lib/CodeGen/DFAPacketizer.cpp index 848db444270..cd302e78cc3 100644 --- a/llvm/lib/CodeGen/DFAPacketizer.cpp +++ b/llvm/lib/CodeGen/DFAPacketizer.cpp @@ -222,7 +222,7 @@ VLIWPacketizerList::~VLIWPacketizerList() { // End the current packet, bundle packet instructions and reset DFA state. void VLIWPacketizerList::endPacket(MachineBasicBlock *MBB, MachineBasicBlock::iterator MI) { - DEBUG({ + LLVM_DEBUG({ if (!CurrentPacketMIs.empty()) { dbgs() << "Finalizing packet:\n"; for (MachineInstr *MI : CurrentPacketMIs) @@ -235,7 +235,7 @@ void VLIWPacketizerList::endPacket(MachineBasicBlock *MBB, } CurrentPacketMIs.clear(); ResourceTracker->clearResources(); - DEBUG(dbgs() << "End packet\n"); + LLVM_DEBUG(dbgs() << "End packet\n"); } // Bundle machine instructions into packets. @@ -248,7 +248,7 @@ void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB, std::distance(BeginItr, EndItr)); VLIWScheduler->schedule(); - DEBUG({ + LLVM_DEBUG({ dbgs() << "Scheduling DAG of the packetize region\n"; for (SUnit &SU : VLIWScheduler->SUnits) SU.dumpAll(VLIWScheduler); @@ -287,10 +287,10 @@ void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB, assert(SUI && "Missing SUnit Info!"); // Ask DFA if machine resource is available for MI. - DEBUG(dbgs() << "Checking resources for adding MI to packet " << MI); + LLVM_DEBUG(dbgs() << "Checking resources for adding MI to packet " << MI); bool ResourceAvail = ResourceTracker->canReserveResources(MI); - DEBUG({ + LLVM_DEBUG({ if (ResourceAvail) dbgs() << " Resources are available for adding MI to packet\n"; else @@ -302,31 +302,33 @@ void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB, SUnit *SUJ = MIToSUnit[MJ]; assert(SUJ && "Missing SUnit Info!"); - DEBUG(dbgs() << " Checking against MJ " << *MJ); + LLVM_DEBUG(dbgs() << " Checking against MJ " << *MJ); // Is it legal to packetize SUI and SUJ together. if (!isLegalToPacketizeTogether(SUI, SUJ)) { - DEBUG(dbgs() << " Not legal to add MI, try to prune\n"); + LLVM_DEBUG(dbgs() << " Not legal to add MI, try to prune\n"); // Allow packetization if dependency can be pruned. if (!isLegalToPruneDependencies(SUI, SUJ)) { // End the packet if dependency cannot be pruned. - DEBUG(dbgs() << " Could not prune dependencies for adding MI\n"); + LLVM_DEBUG(dbgs() + << " Could not prune dependencies for adding MI\n"); endPacket(MBB, MI); break; } - DEBUG(dbgs() << " Pruned dependence for adding MI\n"); + LLVM_DEBUG(dbgs() << " Pruned dependence for adding MI\n"); } } } else { - DEBUG(if (ResourceAvail) - dbgs() << "Resources are available, but instruction should not be " - "added to packet\n " << MI); + LLVM_DEBUG(if (ResourceAvail) dbgs() + << "Resources are available, but instruction should not be " + "added to packet\n " + << MI); // End the packet if resource is not available, or if the instruction // shoud not be added to the current packet. endPacket(MBB, MI); } // Add MI to the current packet. - DEBUG(dbgs() << "* Adding MI to packet " << MI << '\n'); + LLVM_DEBUG(dbgs() << "* Adding MI to packet " << MI << '\n'); BeginItr = addToPacket(MI); } // For all instructions in the packetization range. diff --git a/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp b/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp index e6a54bb300f..ff44c5660ba 100644 --- a/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp +++ b/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp @@ -125,7 +125,7 @@ bool DeadMachineInstructionElim::runOnMachineFunction(MachineFunction &MF) { // If the instruction is dead, delete it! if (isDead(MI)) { - DEBUG(dbgs() << "DeadMachineInstructionElim: DELETING: " << *MI); + LLVM_DEBUG(dbgs() << "DeadMachineInstructionElim: DELETING: " << *MI); // It is possible that some DBG_VALUE instructions refer to this // instruction. They get marked as undef and will be deleted // in the live debug variable analysis. diff --git a/llvm/lib/CodeGen/DetectDeadLanes.cpp b/llvm/lib/CodeGen/DetectDeadLanes.cpp index 7d7eb57352a..c83db476a4d 100644 --- a/llvm/lib/CodeGen/DetectDeadLanes.cpp +++ b/llvm/lib/CodeGen/DetectDeadLanes.cpp @@ -439,7 +439,7 @@ LaneBitmask DetectDeadLanes::determineInitialUsedLanes(unsigned Reg) { const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); CrossCopy = isCrossCopy(*MRI, UseMI, DstRC, MO); if (CrossCopy) - DEBUG(dbgs() << "Copy across incompatible classes: " << UseMI); + LLVM_DEBUG(dbgs() << "Copy across incompatible classes: " << UseMI); } if (!CrossCopy) @@ -520,17 +520,15 @@ bool DetectDeadLanes::runOnce(MachineFunction &MF) { transferDefinedLanesStep(MO, Info.DefinedLanes); } - DEBUG( - dbgs() << "Defined/Used lanes:\n"; - for (unsigned RegIdx = 0; RegIdx < NumVirtRegs; ++RegIdx) { - unsigned Reg = TargetRegisterInfo::index2VirtReg(RegIdx); - const VRegInfo &Info = VRegInfos[RegIdx]; - dbgs() << printReg(Reg, nullptr) - << " Used: " << PrintLaneMask(Info.UsedLanes) - << " Def: " << PrintLaneMask(Info.DefinedLanes) << '\n'; - } - dbgs() << "\n"; - ); + LLVM_DEBUG(dbgs() << "Defined/Used lanes:\n"; for (unsigned RegIdx = 0; + RegIdx < NumVirtRegs; + ++RegIdx) { + unsigned Reg = TargetRegisterInfo::index2VirtReg(RegIdx); + const VRegInfo &Info = VRegInfos[RegIdx]; + dbgs() << printReg(Reg, nullptr) + << " Used: " << PrintLaneMask(Info.UsedLanes) + << " Def: " << PrintLaneMask(Info.DefinedLanes) << '\n'; + } dbgs() << "\n";); bool Again = false; // Mark operands as dead/unused. @@ -545,18 +543,19 @@ bool DetectDeadLanes::runOnce(MachineFunction &MF) { unsigned RegIdx = TargetRegisterInfo::virtReg2Index(Reg); const VRegInfo &RegInfo = VRegInfos[RegIdx]; if (MO.isDef() && !MO.isDead() && RegInfo.UsedLanes.none()) { - DEBUG(dbgs() << "Marking operand '" << MO << "' as dead in " << MI); + LLVM_DEBUG(dbgs() + << "Marking operand '" << MO << "' as dead in " << MI); MO.setIsDead(); } if (MO.readsReg()) { bool CrossCopy = false; if (isUndefRegAtInput(MO, RegInfo)) { - DEBUG(dbgs() << "Marking operand '" << MO << "' as undef in " - << MI); + LLVM_DEBUG(dbgs() + << "Marking operand '" << MO << "' as undef in " << MI); MO.setIsUndef(); } else if (isUndefInput(MO, &CrossCopy)) { - DEBUG(dbgs() << "Marking operand '" << MO << "' as undef in " - << MI); + LLVM_DEBUG(dbgs() + << "Marking operand '" << MO << "' as undef in " << MI); MO.setIsUndef(); if (CrossCopy) Again = true; @@ -577,7 +576,7 @@ bool DetectDeadLanes::runOnMachineFunction(MachineFunction &MF) { // so we safe the compile time. MRI = &MF.getRegInfo(); if (!MRI->subRegLivenessEnabled()) { - DEBUG(dbgs() << "Skipping Detect dead lanes pass\n"); + LLVM_DEBUG(dbgs() << "Skipping Detect dead lanes pass\n"); return false; } diff --git a/llvm/lib/CodeGen/EarlyIfConversion.cpp b/llvm/lib/CodeGen/EarlyIfConversion.cpp index c0c67c40376..098afd885f2 100644 --- a/llvm/lib/CodeGen/EarlyIfConversion.cpp +++ b/llvm/lib/CodeGen/EarlyIfConversion.cpp @@ -185,7 +185,7 @@ bool SSAIfConv::canSpeculateInstrs(MachineBasicBlock *MBB) { // Reject any live-in physregs. It's probably CPSR/EFLAGS, and very hard to // get right. if (!MBB->livein_empty()) { - DEBUG(dbgs() << printMBBReference(*MBB) << " has live-ins.\n"); + LLVM_DEBUG(dbgs() << printMBBReference(*MBB) << " has live-ins.\n"); return false; } @@ -199,14 +199,14 @@ bool SSAIfConv::canSpeculateInstrs(MachineBasicBlock *MBB) { continue; if (++InstrCount > BlockInstrLimit && !Stress) { - DEBUG(dbgs() << printMBBReference(*MBB) << " has more than " - << BlockInstrLimit << " instructions.\n"); + LLVM_DEBUG(dbgs() << printMBBReference(*MBB) << " has more than " + << BlockInstrLimit << " instructions.\n"); return false; } // There shouldn't normally be any phis in a single-predecessor block. if (I->isPHI()) { - DEBUG(dbgs() << "Can't hoist: " << *I); + LLVM_DEBUG(dbgs() << "Can't hoist: " << *I); return false; } @@ -214,21 +214,21 @@ bool SSAIfConv::canSpeculateInstrs(MachineBasicBlock *MBB) { // speculate GOT or constant pool loads that are guaranteed not to trap, // but we don't support that for now. if (I->mayLoad()) { - DEBUG(dbgs() << "Won't speculate load: " << *I); + LLVM_DEBUG(dbgs() << "Won't speculate load: " << *I); return false; } // We never speculate stores, so an AA pointer isn't necessary. bool DontMoveAcrossStore = true; if (!I->isSafeToMove(nullptr, DontMoveAcrossStore)) { - DEBUG(dbgs() << "Can't speculate: " << *I); + LLVM_DEBUG(dbgs() << "Can't speculate: " << *I); return false; } // Check for any dependencies on Head instructions. for (const MachineOperand &MO : I->operands()) { if (MO.isRegMask()) { - DEBUG(dbgs() << "Won't speculate regmask: " << *I); + LLVM_DEBUG(dbgs() << "Won't speculate regmask: " << *I); return false; } if (!MO.isReg()) @@ -246,9 +246,10 @@ bool SSAIfConv::canSpeculateInstrs(MachineBasicBlock *MBB) { if (!DefMI || DefMI->getParent() != Head) continue; if (InsertAfter.insert(DefMI).second) - DEBUG(dbgs() << printMBBReference(*MBB) << " depends on " << *DefMI); + LLVM_DEBUG(dbgs() << printMBBReference(*MBB) << " depends on " + << *DefMI); if (DefMI->isTerminator()) { - DEBUG(dbgs() << "Can't insert instructions below terminator.\n"); + LLVM_DEBUG(dbgs() << "Can't insert instructions below terminator.\n"); return false; } } @@ -279,7 +280,7 @@ bool SSAIfConv::findInsertionPoint() { --I; // Some of the conditional code depends in I. if (InsertAfter.count(&*I)) { - DEBUG(dbgs() << "Can't insert code after " << *I); + LLVM_DEBUG(dbgs() << "Can't insert code after " << *I); return false; } @@ -313,7 +314,7 @@ bool SSAIfConv::findInsertionPoint() { // Some of the clobbered registers are live before I, not a valid insertion // point. if (!LiveRegUnits.empty()) { - DEBUG({ + LLVM_DEBUG({ dbgs() << "Would clobber"; for (SparseSet<unsigned>::const_iterator i = LiveRegUnits.begin(), e = LiveRegUnits.end(); i != e; ++i) @@ -325,10 +326,10 @@ bool SSAIfConv::findInsertionPoint() { // This is a valid insertion point. InsertionPoint = I; - DEBUG(dbgs() << "Can insert before " << *I); + LLVM_DEBUG(dbgs() << "Can insert before " << *I); return true; } - DEBUG(dbgs() << "No legal insertion point found.\n"); + LLVM_DEBUG(dbgs() << "No legal insertion point found.\n"); return false; } @@ -361,39 +362,39 @@ bool SSAIfConv::canConvertIf(MachineBasicBlock *MBB) { if (Succ1->pred_size() != 1 || Succ1->succ_size() != 1 || Succ1->succ_begin()[0] != Tail) return false; - DEBUG(dbgs() << "\nDiamond: " << printMBBReference(*Head) << " -> " - << printMBBReference(*Succ0) << "/" - << printMBBReference(*Succ1) << " -> " - << printMBBReference(*Tail) << '\n'); + LLVM_DEBUG(dbgs() << "\nDiamond: " << printMBBReference(*Head) << " -> " + << printMBBReference(*Succ0) << "/" + << printMBBReference(*Succ1) << " -> " + << printMBBReference(*Tail) << '\n'); // Live-in physregs are tricky to get right when speculating code. if (!Tail->livein_empty()) { - DEBUG(dbgs() << "Tail has live-ins.\n"); + LLVM_DEBUG(dbgs() << "Tail has live-ins.\n"); return false; } } else { - DEBUG(dbgs() << "\nTriangle: " << printMBBReference(*Head) << " -> " - << printMBBReference(*Succ0) << " -> " - << printMBBReference(*Tail) << '\n'); + LLVM_DEBUG(dbgs() << "\nTriangle: " << printMBBReference(*Head) << " -> " + << printMBBReference(*Succ0) << " -> " + << printMBBReference(*Tail) << '\n'); } // This is a triangle or a diamond. // If Tail doesn't have any phis, there must be side effects. if (Tail->empty() || !Tail->front().isPHI()) { - DEBUG(dbgs() << "No phis in tail.\n"); + LLVM_DEBUG(dbgs() << "No phis in tail.\n"); return false; } // The branch we're looking to eliminate must be analyzable. Cond.clear(); if (TII->analyzeBranch(*Head, TBB, FBB, Cond)) { - DEBUG(dbgs() << "Branch not analyzable.\n"); + LLVM_DEBUG(dbgs() << "Branch not analyzable.\n"); return false; } // This is weird, probably some sort of degenerate CFG. if (!TBB) { - DEBUG(dbgs() << "AnalyzeBranch didn't find conditional branch.\n"); + LLVM_DEBUG(dbgs() << "AnalyzeBranch didn't find conditional branch.\n"); return false; } @@ -422,7 +423,7 @@ bool SSAIfConv::canConvertIf(MachineBasicBlock *MBB) { // Get target information. if (!TII->canInsertSelect(*Head, Cond, PI.TReg, PI.FReg, PI.CondCycles, PI.TCycles, PI.FCycles)) { - DEBUG(dbgs() << "Can't convert: " << *PI.PHI); + LLVM_DEBUG(dbgs() << "Can't convert: " << *PI.PHI); return false; } } @@ -459,10 +460,10 @@ void SSAIfConv::replacePHIInstrs() { // Convert all PHIs to select instructions inserted before FirstTerm. for (unsigned i = 0, e = PHIs.size(); i != e; ++i) { PHIInfo &PI = PHIs[i]; - DEBUG(dbgs() << "If-converting " << *PI.PHI); + LLVM_DEBUG(dbgs() << "If-converting " << *PI.PHI); unsigned DstReg = PI.PHI->getOperand(0).getReg(); TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg, PI.FReg); - DEBUG(dbgs() << " --> " << *std::prev(FirstTerm)); + LLVM_DEBUG(dbgs() << " --> " << *std::prev(FirstTerm)); PI.PHI->eraseFromParent(); PI.PHI = nullptr; } @@ -481,7 +482,7 @@ void SSAIfConv::rewritePHIOperands() { PHIInfo &PI = PHIs[i]; unsigned DstReg = 0; - DEBUG(dbgs() << "If-converting " << *PI.PHI); + LLVM_DEBUG(dbgs() << "If-converting " << *PI.PHI); if (PI.TReg == PI.FReg) { // We do not need the select instruction if both incoming values are // equal. @@ -491,7 +492,7 @@ void SSAIfConv::rewritePHIOperands() { DstReg = MRI->createVirtualRegister(MRI->getRegClass(PHIDst)); TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg, PI.FReg); - DEBUG(dbgs() << " --> " << *std::prev(FirstTerm)); + LLVM_DEBUG(dbgs() << " --> " << *std::prev(FirstTerm)); } // Rewrite PHI operands TPred -> (DstReg, Head), remove FPred. @@ -505,7 +506,7 @@ void SSAIfConv::rewritePHIOperands() { PI.PHI->RemoveOperand(i-2); } } - DEBUG(dbgs() << " --> " << *PI.PHI); + LLVM_DEBUG(dbgs() << " --> " << *PI.PHI); } } @@ -563,8 +564,8 @@ void SSAIfConv::convertIf(SmallVectorImpl<MachineBasicBlock*> &RemovedBlocks) { assert(Head->succ_empty() && "Additional head successors?"); if (!ExtraPreds && Head->isLayoutSuccessor(Tail)) { // Splice Tail onto the end of Head. - DEBUG(dbgs() << "Joining tail " << printMBBReference(*Tail) << " into head " - << printMBBReference(*Head) << '\n'); + LLVM_DEBUG(dbgs() << "Joining tail " << printMBBReference(*Tail) + << " into head " << printMBBReference(*Head) << '\n'); Head->splice(Head->end(), Tail, Tail->begin(), Tail->end()); Head->transferSuccessorsAndUpdatePHIs(Tail); @@ -572,12 +573,12 @@ void SSAIfConv::convertIf(SmallVectorImpl<MachineBasicBlock*> &RemovedBlocks) { Tail->eraseFromParent(); } else { // We need a branch to Tail, let code placement work it out later. - DEBUG(dbgs() << "Converting to unconditional branch.\n"); + LLVM_DEBUG(dbgs() << "Converting to unconditional branch.\n"); SmallVector<MachineOperand, 0> EmptyCond; TII->insertBranch(*Head, Tail, nullptr, EmptyCond, HeadDL); Head->addSuccessor(Tail); } - DEBUG(dbgs() << *Head); + LLVM_DEBUG(dbgs() << *Head); } @@ -692,7 +693,7 @@ bool EarlyIfConverter::shouldConvertIf() { MachineTraceMetrics::Trace TBBTrace = MinInstr->getTrace(IfConv.getTPred()); MachineTraceMetrics::Trace FBBTrace = MinInstr->getTrace(IfConv.getFPred()); - DEBUG(dbgs() << "TBB: " << TBBTrace << "FBB: " << FBBTrace); + LLVM_DEBUG(dbgs() << "TBB: " << TBBTrace << "FBB: " << FBBTrace); unsigned MinCrit = std::min(TBBTrace.getCriticalPath(), FBBTrace.getCriticalPath()); @@ -706,10 +707,10 @@ bool EarlyIfConverter::shouldConvertIf() { if (IfConv.TBB != IfConv.Tail) ExtraBlocks.push_back(IfConv.TBB); unsigned ResLength = FBBTrace.getResourceLength(ExtraBlocks); - DEBUG(dbgs() << "Resource length " << ResLength - << ", minimal critical path " << MinCrit << '\n'); + LLVM_DEBUG(dbgs() << "Resource length " << ResLength + << ", minimal critical path " << MinCrit << '\n'); if (ResLength > MinCrit + CritLimit) { - DEBUG(dbgs() << "Not enough available ILP.\n"); + LLVM_DEBUG(dbgs() << "Not enough available ILP.\n"); return false; } @@ -719,7 +720,7 @@ bool EarlyIfConverter::shouldConvertIf() { MachineTraceMetrics::Trace HeadTrace = MinInstr->getTrace(IfConv.Head); unsigned BranchDepth = HeadTrace.getInstrCycles(*IfConv.Head->getFirstTerminator()).Depth; - DEBUG(dbgs() << "Branch depth: " << BranchDepth << '\n'); + LLVM_DEBUG(dbgs() << "Branch depth: " << BranchDepth << '\n'); // Look at all the tail phis, and compute the critical path extension caused // by inserting select instructions. @@ -728,15 +729,15 @@ bool EarlyIfConverter::shouldConvertIf() { SSAIfConv::PHIInfo &PI = IfConv.PHIs[i]; unsigned Slack = TailTrace.getInstrSlack(*PI.PHI); unsigned MaxDepth = Slack + TailTrace.getInstrCycles(*PI.PHI).Depth; - DEBUG(dbgs() << "Slack " << Slack << ":\t" << *PI.PHI); + LLVM_DEBUG(dbgs() << "Slack " << Slack << ":\t" << *PI.PHI); // The condition is pulled into the critical path. unsigned CondDepth = adjCycles(BranchDepth, PI.CondCycles); if (CondDepth > MaxDepth) { unsigned Extra = CondDepth - MaxDepth; - DEBUG(dbgs() << "Condition adds " << Extra << " cycles.\n"); + LLVM_DEBUG(dbgs() << "Condition adds " << Extra << " cycles.\n"); if (Extra > CritLimit) { - DEBUG(dbgs() << "Exceeds limit of " << CritLimit << '\n'); + LLVM_DEBUG(dbgs() << "Exceeds limit of " << CritLimit << '\n'); return false; } } @@ -745,9 +746,9 @@ bool EarlyIfConverter::shouldConvertIf() { unsigned TDepth = adjCycles(TBBTrace.getPHIDepth(*PI.PHI), PI.TCycles); if (TDepth > MaxDepth) { unsigned Extra = TDepth - MaxDepth; - DEBUG(dbgs() << "TBB data adds " << Extra << " cycles.\n"); + LLVM_DEBUG(dbgs() << "TBB data adds " << Extra << " cycles.\n"); if (Extra > CritLimit) { - DEBUG(dbgs() << "Exceeds limit of " << CritLimit << '\n'); + LLVM_DEBUG(dbgs() << "Exceeds limit of " << CritLimit << '\n'); return false; } } @@ -756,9 +757,9 @@ bool EarlyIfConverter::shouldConvertIf() { unsigned FDepth = adjCycles(FBBTrace.getPHIDepth(*PI.PHI), PI.FCycles); if (FDepth > MaxDepth) { unsigned Extra = FDepth - MaxDepth; - DEBUG(dbgs() << "FBB data adds " << Extra << " cycles.\n"); + LLVM_DEBUG(dbgs() << "FBB data adds " << Extra << " cycles.\n"); if (Extra > CritLimit) { - DEBUG(dbgs() << "Exceeds limit of " << CritLimit << '\n'); + LLVM_DEBUG(dbgs() << "Exceeds limit of " << CritLimit << '\n'); return false; } } @@ -783,8 +784,8 @@ bool EarlyIfConverter::tryConvertIf(MachineBasicBlock *MBB) { } bool EarlyIfConverter::runOnMachineFunction(MachineFunction &MF) { - DEBUG(dbgs() << "********** EARLY IF-CONVERSION **********\n" - << "********** Function: " << MF.getName() << '\n'); + LLVM_DEBUG(dbgs() << "********** EARLY IF-CONVERSION **********\n" + << "********** Function: " << MF.getName() << '\n'); if (skipFunction(MF.getFunction())) return false; diff --git a/llvm/lib/CodeGen/ExecutionDomainFix.cpp b/llvm/lib/CodeGen/ExecutionDomainFix.cpp index 6413489e9d9..458dcf2b0e2 100644 --- a/llvm/lib/CodeGen/ExecutionDomainFix.cpp +++ b/llvm/lib/CodeGen/ExecutionDomainFix.cpp @@ -161,7 +161,7 @@ void ExecutionDomainFix::enterBasicBlock( // This is the entry block. if (MBB->pred_empty()) { - DEBUG(dbgs() << printMBBReference(*MBB) << ": entry\n"); + LLVM_DEBUG(dbgs() << printMBBReference(*MBB) << ": entry\n"); return; } @@ -200,9 +200,9 @@ void ExecutionDomainFix::enterBasicBlock( force(rx, pdv->getFirstDomain()); } } - DEBUG(dbgs() << printMBBReference(*MBB) - << (!TraversedMBB.IsDone ? ": incomplete\n" - : ": all preds known\n")); + LLVM_DEBUG(dbgs() << printMBBReference(*MBB) + << (!TraversedMBB.IsDone ? ": incomplete\n" + : ": all preds known\n")); } void ExecutionDomainFix::leaveBasicBlock( @@ -245,7 +245,7 @@ void ExecutionDomainFix::processDefs(MachineInstr *MI, bool Kill) { continue; for (int rx : regIndices(MO.getReg())) { // This instruction explicitly defines rx. - DEBUG(dbgs() << printReg(RC->getRegister(rx), TRI) << ":\t" << *MI); + LLVM_DEBUG(dbgs() << printReg(RC->getRegister(rx), TRI) << ":\t" << *MI); // Kill off domains redefined by generic instructions. if (Kill) @@ -420,8 +420,8 @@ bool ExecutionDomainFix::runOnMachineFunction(MachineFunction &mf) { LiveRegs.clear(); assert(NumRegs == RC->getNumRegs() && "Bad regclass"); - DEBUG(dbgs() << "********** FIX EXECUTION DOMAIN: " - << TRI->getRegClassName(RC) << " **********\n"); + LLVM_DEBUG(dbgs() << "********** FIX EXECUTION DOMAIN: " + << TRI->getRegClassName(RC) << " **********\n"); // If no relevant registers are used in the function, we can skip it // completely. diff --git a/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp b/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp index 6ef97d6dd5e..bc747fc610f 100644 --- a/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp +++ b/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp @@ -93,11 +93,11 @@ bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) { assert(TargetRegisterInfo::isPhysicalRegister(InsReg) && "Inserted value must be in a physical register"); - DEBUG(dbgs() << "subreg: CONVERTING: " << *MI); + LLVM_DEBUG(dbgs() << "subreg: CONVERTING: " << *MI); if (MI->allDefsAreDead()) { MI->setDesc(TII->get(TargetOpcode::KILL)); - DEBUG(dbgs() << "subreg: replaced by: " << *MI); + LLVM_DEBUG(dbgs() << "subreg: replaced by: " << *MI); return true; } @@ -110,10 +110,10 @@ bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) { MI->setDesc(TII->get(TargetOpcode::KILL)); MI->RemoveOperand(3); // SubIdx MI->RemoveOperand(1); // Imm - DEBUG(dbgs() << "subreg: replace by: " << *MI); + LLVM_DEBUG(dbgs() << "subreg: replace by: " << *MI); return true; } - DEBUG(dbgs() << "subreg: eliminated!"); + LLVM_DEBUG(dbgs() << "subreg: eliminated!"); } else { TII->copyPhysReg(*MBB, MI, MI->getDebugLoc(), DstSubReg, InsReg, MI->getOperand(2).isKill()); @@ -122,10 +122,10 @@ bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) { MachineBasicBlock::iterator CopyMI = MI; --CopyMI; CopyMI->addRegisterDefined(DstReg); - DEBUG(dbgs() << "subreg: " << *CopyMI); + LLVM_DEBUG(dbgs() << "subreg: " << *CopyMI); } - DEBUG(dbgs() << '\n'); + LLVM_DEBUG(dbgs() << '\n'); MBB->erase(MI); return true; } @@ -133,9 +133,9 @@ bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) { bool ExpandPostRA::LowerCopy(MachineInstr *MI) { if (MI->allDefsAreDead()) { - DEBUG(dbgs() << "dead copy: " << *MI); + LLVM_DEBUG(dbgs() << "dead copy: " << *MI); MI->setDesc(TII->get(TargetOpcode::KILL)); - DEBUG(dbgs() << "replaced by: " << *MI); + LLVM_DEBUG(dbgs() << "replaced by: " << *MI); return true; } @@ -144,14 +144,15 @@ bool ExpandPostRA::LowerCopy(MachineInstr *MI) { bool IdentityCopy = (SrcMO.getReg() == DstMO.getReg()); if (IdentityCopy || SrcMO.isUndef()) { - DEBUG(dbgs() << (IdentityCopy ? "identity copy: " : "undef copy: ") << *MI); + LLVM_DEBUG(dbgs() << (IdentityCopy ? "identity copy: " : "undef copy: ") + << *MI); // No need to insert an identity copy instruction, but replace with a KILL // if liveness is changed. if (SrcMO.isUndef() || MI->getNumOperands() > 2) { // We must make sure the super-register gets killed. Replace the // instruction with KILL. MI->setDesc(TII->get(TargetOpcode::KILL)); - DEBUG(dbgs() << "replaced by: " << *MI); + LLVM_DEBUG(dbgs() << "replaced by: " << *MI); return true; } // Vanilla identity copy. @@ -159,13 +160,13 @@ bool ExpandPostRA::LowerCopy(MachineInstr *MI) { return true; } - DEBUG(dbgs() << "real copy: " << *MI); + LLVM_DEBUG(dbgs() << "real copy: " << *MI); TII->copyPhysReg(*MI->getParent(), MI, MI->getDebugLoc(), DstMO.getReg(), SrcMO.getReg(), SrcMO.isKill()); if (MI->getNumOperands() > 2) TransferImplicitOperands(MI); - DEBUG({ + LLVM_DEBUG({ MachineBasicBlock::iterator dMI = MI; dbgs() << "replaced by: " << *(--dMI); }); @@ -177,9 +178,9 @@ bool ExpandPostRA::LowerCopy(MachineInstr *MI) { /// copies. /// bool ExpandPostRA::runOnMachineFunction(MachineFunction &MF) { - DEBUG(dbgs() << "Machine Function\n" - << "********** EXPANDING POST-RA PSEUDO INSTRS **********\n" - << "********** Function: " << MF.getName() << '\n'); + LLVM_DEBUG(dbgs() << "Machine Function\n" + << "********** EXPANDING POST-RA PSEUDO INSTRS **********\n" + << "********** Function: " << MF.getName() << '\n'); TRI = MF.getSubtarget().getRegisterInfo(); TII = MF.getSubtarget().getInstrInfo(); diff --git a/llvm/lib/CodeGen/FaultMaps.cpp b/llvm/lib/CodeGen/FaultMaps.cpp index 2924b011e0c..361558a0e56 100644 --- a/llvm/lib/CodeGen/FaultMaps.cpp +++ b/llvm/lib/CodeGen/FaultMaps.cpp @@ -62,17 +62,17 @@ void FaultMaps::serializeToFaultMapSection() { // Emit a dummy symbol to force section inclusion. OS.EmitLabel(OutContext.getOrCreateSymbol(Twine("__LLVM_FaultMaps"))); - DEBUG(dbgs() << "********** Fault Map Output **********\n"); + LLVM_DEBUG(dbgs() << "********** Fault Map Output **********\n"); // Header OS.EmitIntValue(FaultMapVersion, 1); // Version. OS.EmitIntValue(0, 1); // Reserved. OS.EmitIntValue(0, 2); // Reserved. - DEBUG(dbgs() << WFMP << "#functions = " << FunctionInfos.size() << "\n"); + LLVM_DEBUG(dbgs() << WFMP << "#functions = " << FunctionInfos.size() << "\n"); OS.EmitIntValue(FunctionInfos.size(), 4); - DEBUG(dbgs() << WFMP << "functions:\n"); + LLVM_DEBUG(dbgs() << WFMP << "functions:\n"); for (const auto &FFI : FunctionInfos) emitFunctionInfo(FFI.first, FFI.second); @@ -82,25 +82,25 @@ void FaultMaps::emitFunctionInfo(const MCSymbol *FnLabel, const FunctionFaultInfos &FFI) { MCStreamer &OS = *AP.OutStreamer; - DEBUG(dbgs() << WFMP << " function addr: " << *FnLabel << "\n"); + LLVM_DEBUG(dbgs() << WFMP << " function addr: " << *FnLabel << "\n"); OS.EmitSymbolValue(FnLabel, 8); - DEBUG(dbgs() << WFMP << " #faulting PCs: " << FFI.size() << "\n"); + LLVM_DEBUG(dbgs() << WFMP << " #faulting PCs: " << FFI.size() << "\n"); OS.EmitIntValue(FFI.size(), 4); OS.EmitIntValue(0, 4); // Reserved for (auto &Fault : FFI) { - DEBUG(dbgs() << WFMP << " fault type: " - << faultTypeToString(Fault.Kind) << "\n"); + LLVM_DEBUG(dbgs() << WFMP << " fault type: " + << faultTypeToString(Fault.Kind) << "\n"); OS.EmitIntValue(Fault.Kind, 4); - DEBUG(dbgs() << WFMP << " faulting PC offset: " - << *Fault.FaultingOffsetExpr << "\n"); + LLVM_DEBUG(dbgs() << WFMP << " faulting PC offset: " + << *Fault.FaultingOffsetExpr << "\n"); OS.EmitValue(Fault.FaultingOffsetExpr, 4); - DEBUG(dbgs() << WFMP << " fault handler PC offset: " - << *Fault.HandlerOffsetExpr << "\n"); + LLVM_DEBUG(dbgs() << WFMP << " fault handler PC offset: " + << *Fault.HandlerOffsetExpr << "\n"); OS.EmitValue(Fault.HandlerOffsetExpr, 4); } } diff --git a/llvm/lib/CodeGen/GlobalISel/Combiner.cpp b/llvm/lib/CodeGen/GlobalISel/Combiner.cpp index dbc9dbc53de..0bc5b87de15 100644 --- a/llvm/lib/CodeGen/GlobalISel/Combiner.cpp +++ b/llvm/lib/CodeGen/GlobalISel/Combiner.cpp @@ -40,7 +40,7 @@ bool Combiner::combineMachineInstrs(MachineFunction &MF) { MRI = &MF.getRegInfo(); Builder.setMF(MF); - DEBUG(dbgs() << "Generic MI Combiner for: " << MF.getName() << '\n'); + LLVM_DEBUG(dbgs() << "Generic MI Combiner for: " << MF.getName() << '\n'); MachineOptimizationRemarkEmitter MORE(MF, /*MBFI=*/nullptr); @@ -61,7 +61,7 @@ bool Combiner::combineMachineInstrs(MachineFunction &MF) { ++MII; // Erase dead insts before even adding to the list. if (isTriviallyDead(*CurMI, *MRI)) { - DEBUG(dbgs() << *CurMI << "Is dead; erasing.\n"); + LLVM_DEBUG(dbgs() << *CurMI << "Is dead; erasing.\n"); CurMI->eraseFromParentAndMarkDBGValuesForRemoval(); continue; } @@ -71,7 +71,7 @@ bool Combiner::combineMachineInstrs(MachineFunction &MF) { // Main Loop. Process the instructions here. while (!WorkList.empty()) { MachineInstr *CurrInst = WorkList.pop_back_val(); - DEBUG(dbgs() << "Try combining " << *CurrInst << "\n";); + LLVM_DEBUG(dbgs() << "Try combining " << *CurrInst << "\n";); Changed |= CInfo.combine(*CurrInst, Builder); } MFChanged |= Changed; diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index b0a40f82f9b..18572fea181 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -652,7 +652,7 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID, const Value *Address = DI.getAddress(); if (!Address || isa<UndefValue>(Address)) { - DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); + LLVM_DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); return true; } diff --git a/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp b/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp index 7923a888118..7d37a6ce460 100644 --- a/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp +++ b/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp @@ -65,7 +65,7 @@ bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) { MachineFunctionProperties::Property::FailedISel)) return false; - DEBUG(dbgs() << "Selecting function: " << MF.getName() << '\n'); + LLVM_DEBUG(dbgs() << "Selecting function: " << MF.getName() << '\n'); const TargetPassConfig &TPC = getAnalysis<TargetPassConfig>(); const InstructionSelector *ISel = MF.getSubtarget().getInstructionSelector(); @@ -116,12 +116,12 @@ bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) { else --MII; - DEBUG(dbgs() << "Selecting: \n " << MI); + LLVM_DEBUG(dbgs() << "Selecting: \n " << MI); // We could have folded this instruction away already, making it dead. // If so, erase it. if (isTriviallyDead(MI, MRI)) { - DEBUG(dbgs() << "Is dead; erasing.\n"); + LLVM_DEBUG(dbgs() << "Is dead; erasing.\n"); MI.eraseFromParentAndMarkDBGValuesForRemoval(); continue; } @@ -134,7 +134,7 @@ bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) { } // Dump the range of instructions that MI expanded into. - DEBUG({ + LLVM_DEBUG({ auto InsertedBegin = ReachedBegin ? MBB->begin() : std::next(MII); dbgs() << "Into:\n"; for (auto &InsertedMI : make_range(InsertedBegin, AfterIt)) @@ -218,7 +218,7 @@ bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) { auto &TLI = *MF.getSubtarget().getTargetLowering(); TLI.finalizeLowering(MF); - DEBUG({ + LLVM_DEBUG({ dbgs() << "Rules covered by selecting function: " << MF.getName() << ":"; for (auto RuleID : CoverageInfo.covered()) dbgs() << " id" << RuleID; diff --git a/llvm/lib/CodeGen/GlobalISel/Legalizer.cpp b/llvm/lib/CodeGen/GlobalISel/Legalizer.cpp index f09b0d9f11e..6ce5851d436 100644 --- a/llvm/lib/CodeGen/GlobalISel/Legalizer.cpp +++ b/llvm/lib/CodeGen/GlobalISel/Legalizer.cpp @@ -72,7 +72,7 @@ bool Legalizer::runOnMachineFunction(MachineFunction &MF) { if (MF.getProperties().hasProperty( MachineFunctionProperties::Property::FailedISel)) return false; - DEBUG(dbgs() << "Legalize Machine IR for: " << MF.getName() << '\n'); + LLVM_DEBUG(dbgs() << "Legalize Machine IR for: " << MF.getName() << '\n'); init(MF); const TargetPassConfig &TPC = getAnalysis<TargetPassConfig>(); MachineOptimizationRemarkEmitter MORE(MF, /*MBFI=*/nullptr); @@ -112,7 +112,7 @@ bool Legalizer::runOnMachineFunction(MachineFunction &MF) { else InstList.insert(MI); } - DEBUG(dbgs() << ".. .. New MI: " << *MI;); + LLVM_DEBUG(dbgs() << ".. .. New MI: " << *MI;); }); const LegalizerInfo &LInfo(Helper.getLegalizerInfo()); LegalizationArtifactCombiner ArtCombiner(Helper.MIRBuilder, MF.getRegInfo(), LInfo); @@ -127,7 +127,7 @@ bool Legalizer::runOnMachineFunction(MachineFunction &MF) { MachineInstr &MI = *InstList.pop_back_val(); assert(isPreISelGenericOpcode(MI.getOpcode()) && "Expecting generic opcode"); if (isTriviallyDead(MI, MRI)) { - DEBUG(dbgs() << MI << "Is dead; erasing.\n"); + LLVM_DEBUG(dbgs() << MI << "Is dead; erasing.\n"); MI.eraseFromParentAndMarkDBGValuesForRemoval(); continue; } @@ -148,7 +148,7 @@ bool Legalizer::runOnMachineFunction(MachineFunction &MF) { MachineInstr &MI = *ArtifactList.pop_back_val(); assert(isPreISelGenericOpcode(MI.getOpcode()) && "Expecting generic opcode"); if (isTriviallyDead(MI, MRI)) { - DEBUG(dbgs() << MI << "Is dead; erasing.\n"); + LLVM_DEBUG(dbgs() << MI << "Is dead; erasing.\n"); RemoveDeadInstFromLists(&MI); MI.eraseFromParentAndMarkDBGValuesForRemoval(); continue; @@ -156,7 +156,7 @@ bool Legalizer::runOnMachineFunction(MachineFunction &MF) { SmallVector<MachineInstr *, 4> DeadInstructions; if (ArtCombiner.tryCombineInstruction(MI, DeadInstructions)) { for (auto *DeadMI : DeadInstructions) { - DEBUG(dbgs() << ".. Erasing Dead Instruction " << *DeadMI); + LLVM_DEBUG(dbgs() << ".. Erasing Dead Instruction " << *DeadMI); RemoveDeadInstFromLists(DeadMI); DeadMI->eraseFromParentAndMarkDBGValuesForRemoval(); } diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp index 410c3b72270..b5cc7f7727f 100644 --- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -35,34 +35,34 @@ LegalizerHelper::LegalizerHelper(MachineFunction &MF) LegalizerHelper::LegalizeResult LegalizerHelper::legalizeInstrStep(MachineInstr &MI) { - DEBUG(dbgs() << "Legalizing: "; MI.print(dbgs())); + LLVM_DEBUG(dbgs() << "Legalizing: "; MI.print(dbgs())); auto Step = LI.getAction(MI, MRI); switch (Step.Action) { case Legal: - DEBUG(dbgs() << ".. Already legal\n"); + LLVM_DEBUG(dbgs() << ".. Already legal\n"); return AlreadyLegal; case Libcall: - DEBUG(dbgs() << ".. Convert to libcall\n"); + LLVM_DEBUG(dbgs() << ".. Convert to libcall\n"); return libcall(MI); case NarrowScalar: - DEBUG(dbgs() << ".. Narrow scalar\n"); + LLVM_DEBUG(dbgs() << ".. Narrow scalar\n"); return narrowScalar(MI, Step.TypeIdx, Step.NewType); case WidenScalar: - DEBUG(dbgs() << ".. Widen scalar\n"); + LLVM_DEBUG(dbgs() << ".. Widen scalar\n"); return widenScalar(MI, Step.TypeIdx, Step.NewType); case Lower: - DEBUG(dbgs() << ".. Lower\n"); + LLVM_DEBUG(dbgs() << ".. Lower\n"); return lower(MI, Step.TypeIdx, Step.NewType); case FewerElements: - DEBUG(dbgs() << ".. Reduce number of elements\n"); + LLVM_DEBUG(dbgs() << ".. Reduce number of elements\n"); return fewerElementsVector(MI, Step.TypeIdx, Step.NewType); case Custom: - DEBUG(dbgs() << ".. Custom legalization\n"); + LLVM_DEBUG(dbgs() << ".. Custom legalization\n"); return LI.legalizeCustom(MI, MRI, MIRBuilder) ? Legalized : UnableToLegalize; default: - DEBUG(dbgs() << ".. Unable to legalize\n"); + LLVM_DEBUG(dbgs() << ".. Unable to legalize\n"); return UnableToLegalize; } } diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerInfo.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerInfo.cpp index a681e9f7b2d..3ff5e97e883 100644 --- a/llvm/lib/CodeGen/GlobalISel/LegalizerInfo.cpp +++ b/llvm/lib/CodeGen/GlobalISel/LegalizerInfo.cpp @@ -58,18 +58,18 @@ raw_ostream &LegalityQuery::print(raw_ostream &OS) const { } LegalizeActionStep LegalizeRuleSet::apply(const LegalityQuery &Query) const { - DEBUG(dbgs() << "Applying legalizer ruleset to: "; Query.print(dbgs()); - dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "Applying legalizer ruleset to: "; Query.print(dbgs()); + dbgs() << "\n"); if (Rules.empty()) { - DEBUG(dbgs() << ".. fallback to legacy rules (no rules defined)\n"); + LLVM_DEBUG(dbgs() << ".. fallback to legacy rules (no rules defined)\n"); return {LegalizeAction::UseLegacyRules, 0, LLT{}}; } for (const auto &Rule : Rules) { if (Rule.match(Query)) { - DEBUG(dbgs() << ".. match\n"); + LLVM_DEBUG(dbgs() << ".. match\n"); std::pair<unsigned, LLT> Mutation = Rule.determineMutation(Query); - DEBUG(dbgs() << ".. .. " << (unsigned)Rule.getAction() << ", " - << Mutation.first << ", " << Mutation.second << "\n"); + LLVM_DEBUG(dbgs() << ".. .. " << (unsigned)Rule.getAction() << ", " + << Mutation.first << ", " << Mutation.second << "\n"); assert((Query.Types[Mutation.first] != Mutation.second || Rule.getAction() == Lower || Rule.getAction() == MoreElements || @@ -77,9 +77,9 @@ LegalizeActionStep LegalizeRuleSet::apply(const LegalityQuery &Query) const { "Simple loop detected"); return {Rule.getAction(), Mutation.first, Mutation.second}; } else - DEBUG(dbgs() << ".. no match\n"); + LLVM_DEBUG(dbgs() << ".. no match\n"); } - DEBUG(dbgs() << ".. unsupported\n"); + LLVM_DEBUG(dbgs() << ".. unsupported\n"); return {LegalizeAction::Unsupported, 0, LLT{}}; } @@ -247,11 +247,11 @@ unsigned LegalizerInfo::getOpcodeIdxForOpcode(unsigned Opcode) const { unsigned LegalizerInfo::getActionDefinitionsIdx(unsigned Opcode) const { unsigned OpcodeIdx = getOpcodeIdxForOpcode(Opcode); if (unsigned Alias = RulesForOpcode[OpcodeIdx].getAlias()) { - DEBUG(dbgs() << ".. opcode " << Opcode << " is aliased to " << Alias - << "\n"); + LLVM_DEBUG(dbgs() << ".. opcode " << Opcode << " is aliased to " << Alias + << "\n"); OpcodeIdx = getOpcodeIdxForOpcode(Alias); - DEBUG(dbgs() << ".. opcode " << Alias << " is aliased to " - << RulesForOpcode[OpcodeIdx].getAlias() << "\n"); + LLVM_DEBUG(dbgs() << ".. opcode " << Alias << " is aliased to " + << RulesForOpcode[OpcodeIdx].getAlias() << "\n"); assert(RulesForOpcode[OpcodeIdx].getAlias() == 0 && "Cannot chain aliases"); } @@ -305,13 +305,14 @@ LegalizerInfo::getAction(const LegalityQuery &Query) const { for (unsigned i = 0; i < Query.Types.size(); ++i) { auto Action = getAspectAction({Query.Opcode, i, Query.Types[i]}); if (Action.first != Legal) { - DEBUG(dbgs() << ".. (legacy) Type " << i << " Action=" - << (unsigned)Action.first << ", " << Action.second << "\n"); + LLVM_DEBUG(dbgs() << ".. (legacy) Type " << i + << " Action=" << (unsigned)Action.first << ", " + << Action.second << "\n"); return {Action.first, i, Action.second}; } else - DEBUG(dbgs() << ".. (legacy) Type " << i << " Legal\n"); + LLVM_DEBUG(dbgs() << ".. (legacy) Type " << i << " Legal\n"); } - DEBUG(dbgs() << ".. (legacy) Legal\n"); + LLVM_DEBUG(dbgs() << ".. (legacy) Legal\n"); return {Legal, 0, LLT{}}; } diff --git a/llvm/lib/CodeGen/GlobalISel/Localizer.cpp b/llvm/lib/CodeGen/GlobalISel/Localizer.cpp index 8e16470b6f9..d7dc2c2c18c 100644 --- a/llvm/lib/CodeGen/GlobalISel/Localizer.cpp +++ b/llvm/lib/CodeGen/GlobalISel/Localizer.cpp @@ -59,7 +59,7 @@ bool Localizer::runOnMachineFunction(MachineFunction &MF) { MachineFunctionProperties::Property::FailedISel)) return false; - DEBUG(dbgs() << "Localize instructions for: " << MF.getName() << '\n'); + LLVM_DEBUG(dbgs() << "Localize instructions for: " << MF.getName() << '\n'); init(MF); @@ -73,7 +73,7 @@ bool Localizer::runOnMachineFunction(MachineFunction &MF) { for (MachineInstr &MI : MBB) { if (LocalizedInstrs.count(&MI) || !shouldLocalize(MI)) continue; - DEBUG(dbgs() << "Should localize: " << MI); + LLVM_DEBUG(dbgs() << "Should localize: " << MI); assert(MI.getDesc().getNumDefs() == 1 && "More than one definition not supported yet"); unsigned Reg = MI.getOperand(0).getReg(); @@ -85,12 +85,12 @@ bool Localizer::runOnMachineFunction(MachineFunction &MF) { MachineOperand &MOUse = *MOIt++; // Check if the use is already local. MachineBasicBlock *InsertMBB; - DEBUG(MachineInstr &MIUse = *MOUse.getParent(); - dbgs() << "Checking use: " << MIUse - << " #Opd: " << MIUse.getOperandNo(&MOUse) << '\n'); + LLVM_DEBUG(MachineInstr &MIUse = *MOUse.getParent(); + dbgs() << "Checking use: " << MIUse + << " #Opd: " << MIUse.getOperandNo(&MOUse) << '\n'); if (isLocalUse(MOUse, MI, InsertMBB)) continue; - DEBUG(dbgs() << "Fixing non-local use\n"); + LLVM_DEBUG(dbgs() << "Fixing non-local use\n"); Changed = true; auto MBBAndReg = std::make_pair(InsertMBB, Reg); auto NewVRegIt = MBBWithLocalDef.find(MBBAndReg); @@ -111,10 +111,10 @@ bool Localizer::runOnMachineFunction(MachineFunction &MF) { LocalizedMI->getOperand(0).setReg(NewReg); NewVRegIt = MBBWithLocalDef.insert(std::make_pair(MBBAndReg, NewReg)).first; - DEBUG(dbgs() << "Inserted: " << *LocalizedMI); + LLVM_DEBUG(dbgs() << "Inserted: " << *LocalizedMI); } - DEBUG(dbgs() << "Update use with: " << printReg(NewVRegIt->second) - << '\n'); + LLVM_DEBUG(dbgs() << "Update use with: " << printReg(NewVRegIt->second) + << '\n'); // Update the user reg. MOUse.setReg(NewVRegIt->second); } diff --git a/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp b/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp index ba59b148e7f..03bfae7c465 100644 --- a/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp +++ b/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp @@ -76,7 +76,7 @@ RegBankSelect::RegBankSelect(Mode RunningMode) if (RegBankSelectMode.getNumOccurrences() != 0) { OptMode = RegBankSelectMode; if (RegBankSelectMode != RunningMode) - DEBUG(dbgs() << "RegBankSelect mode overrided by command line\n"); + LLVM_DEBUG(dbgs() << "RegBankSelect mode overrided by command line\n"); } } @@ -123,11 +123,11 @@ bool RegBankSelect::assignmentMatch( // Reg is free of assignment, a simple assignment will make the // register bank to match. OnlyAssign = CurRegBank == nullptr; - DEBUG(dbgs() << "Does assignment already match: "; - if (CurRegBank) dbgs() << *CurRegBank; else dbgs() << "none"; - dbgs() << " against "; - assert(DesiredRegBrank && "The mapping must be valid"); - dbgs() << *DesiredRegBrank << '\n';); + LLVM_DEBUG(dbgs() << "Does assignment already match: "; + if (CurRegBank) dbgs() << *CurRegBank; else dbgs() << "none"; + dbgs() << " against "; + assert(DesiredRegBrank && "The mapping must be valid"); + dbgs() << *DesiredRegBrank << '\n';); return CurRegBank == DesiredRegBrank; } @@ -160,8 +160,8 @@ bool RegBankSelect::repairReg( // same types because the type is a placeholder when this function is called. MachineInstr *MI = MIRBuilder.buildInstrNoInsert(TargetOpcode::COPY).addDef(Dst).addUse(Src); - DEBUG(dbgs() << "Copy: " << printReg(Src) << " to: " << printReg(Dst) - << '\n'); + LLVM_DEBUG(dbgs() << "Copy: " << printReg(Src) << " to: " << printReg(Dst) + << '\n'); // TODO: // Check if MI is legal. if not, we need to legalize all the // instructions we are going to insert. @@ -246,7 +246,7 @@ const RegisterBankInfo::InstructionMapping &RegBankSelect::findBestMapping( MappingCost CurCost = computeMapping(MI, *CurMapping, LocalRepairPts, &Cost); if (CurCost < Cost) { - DEBUG(dbgs() << "New best: " << CurCost << '\n'); + LLVM_DEBUG(dbgs() << "New best: " << CurCost << '\n'); Cost = CurCost; BestMapping = CurMapping; RepairPts.clear(); @@ -398,11 +398,11 @@ RegBankSelect::MappingCost RegBankSelect::computeMapping( MappingCost Cost(MBFI ? MBFI->getBlockFreq(MI.getParent()) : 1); bool Saturated = Cost.addLocalCost(InstrMapping.getCost()); assert(!Saturated && "Possible mapping saturated the cost"); - DEBUG(dbgs() << "Evaluating mapping cost for: " << MI); - DEBUG(dbgs() << "With: " << InstrMapping << '\n'); + LLVM_DEBUG(dbgs() << "Evaluating mapping cost for: " << MI); + LLVM_DEBUG(dbgs() << "With: " << InstrMapping << '\n'); RepairPts.clear(); if (BestCost && Cost > *BestCost) { - DEBUG(dbgs() << "Mapping is too expensive from the start\n"); + LLVM_DEBUG(dbgs() << "Mapping is too expensive from the start\n"); return Cost; } @@ -418,17 +418,17 @@ RegBankSelect::MappingCost RegBankSelect::computeMapping( unsigned Reg = MO.getReg(); if (!Reg) continue; - DEBUG(dbgs() << "Opd" << OpIdx << '\n'); + LLVM_DEBUG(dbgs() << "Opd" << OpIdx << '\n'); const RegisterBankInfo::ValueMapping &ValMapping = InstrMapping.getOperandMapping(OpIdx); // If Reg is already properly mapped, this is free. bool Assign; if (assignmentMatch(Reg, ValMapping, Assign)) { - DEBUG(dbgs() << "=> is free (match).\n"); + LLVM_DEBUG(dbgs() << "=> is free (match).\n"); continue; } if (Assign) { - DEBUG(dbgs() << "=> is free (simple assignment).\n"); + LLVM_DEBUG(dbgs() << "=> is free (simple assignment).\n"); RepairPts.emplace_back(RepairingPlacement(MI, OpIdx, *TRI, *this, RepairingPlacement::Reassign)); continue; @@ -447,7 +447,7 @@ RegBankSelect::MappingCost RegBankSelect::computeMapping( // Check that the materialization of the repairing is possible. if (!RepairPt.canMaterialize()) { - DEBUG(dbgs() << "Mapping involves impossible repairing\n"); + LLVM_DEBUG(dbgs() << "Mapping involves impossible repairing\n"); return MappingCost::ImpossibleCost(); } @@ -510,7 +510,7 @@ RegBankSelect::MappingCost RegBankSelect::computeMapping( // Stop looking into what it takes to repair, this is already // too expensive. if (BestCost && Cost > *BestCost) { - DEBUG(dbgs() << "Mapping is too expensive, stop processing\n"); + LLVM_DEBUG(dbgs() << "Mapping is too expensive, stop processing\n"); return Cost; } @@ -520,7 +520,7 @@ RegBankSelect::MappingCost RegBankSelect::computeMapping( break; } } - DEBUG(dbgs() << "Total cost is: " << Cost << "\n"); + LLVM_DEBUG(dbgs() << "Total cost is: " << Cost << "\n"); return Cost; } @@ -560,14 +560,14 @@ bool RegBankSelect::applyMapping( } // Second, rewrite the instruction. - DEBUG(dbgs() << "Actual mapping of the operands: " << OpdMapper << '\n'); + LLVM_DEBUG(dbgs() << "Actual mapping of the operands: " << OpdMapper << '\n'); RBI->applyMapping(OpdMapper); return true; } bool RegBankSelect::assignInstr(MachineInstr &MI) { - DEBUG(dbgs() << "Assign: " << MI); + LLVM_DEBUG(dbgs() << "Assign: " << MI); // Remember the repairing placement for all the operands. SmallVector<RepairingPlacement, 4> RepairPts; @@ -588,7 +588,7 @@ bool RegBankSelect::assignInstr(MachineInstr &MI) { // Make sure the mapping is valid for MI. assert(BestMapping->verify(MI) && "Invalid instruction mapping"); - DEBUG(dbgs() << "Best Mapping: " << *BestMapping << '\n'); + LLVM_DEBUG(dbgs() << "Best Mapping: " << *BestMapping << '\n'); // After this call, MI may not be valid anymore. // Do not use it. @@ -601,7 +601,7 @@ bool RegBankSelect::runOnMachineFunction(MachineFunction &MF) { MachineFunctionProperties::Property::FailedISel)) return false; - DEBUG(dbgs() << "Assign register banks for: " << MF.getName() << '\n'); + LLVM_DEBUG(dbgs() << "Assign register banks for: " << MF.getName() << '\n'); const Function &F = MF.getFunction(); Mode SaveOptMode = OptMode; if (F.hasFnAttribute(Attribute::OptimizeNone)) diff --git a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp index 8977c7d81aa..dd15567ef1c 100644 --- a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp +++ b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp @@ -73,7 +73,7 @@ bool RegisterBankInfo::verify(const TargetRegisterInfo &TRI) const { const RegisterBank &RegBank = getRegBank(Idx); assert(Idx == RegBank.getID() && "ID does not match the index in the array"); - DEBUG(dbgs() << "Verify " << RegBank << '\n'); + LLVM_DEBUG(dbgs() << "Verify " << RegBank << '\n'); assert(RegBank.verify(TRI) && "RegBank is invalid"); } #endif // NDEBUG @@ -404,18 +404,18 @@ RegisterBankInfo::getInstrAlternativeMappings(const MachineInstr &MI) const { void RegisterBankInfo::applyDefaultMapping(const OperandsMapper &OpdMapper) { MachineInstr &MI = OpdMapper.getMI(); MachineRegisterInfo &MRI = OpdMapper.getMRI(); - DEBUG(dbgs() << "Applying default-like mapping\n"); + LLVM_DEBUG(dbgs() << "Applying default-like mapping\n"); for (unsigned OpIdx = 0, EndIdx = OpdMapper.getInstrMapping().getNumOperands(); OpIdx != EndIdx; ++OpIdx) { - DEBUG(dbgs() << "OpIdx " << OpIdx); + LLVM_DEBUG(dbgs() << "OpIdx " << OpIdx); MachineOperand &MO = MI.getOperand(OpIdx); if (!MO.isReg()) { - DEBUG(dbgs() << " is not a register, nothing to be done\n"); + LLVM_DEBUG(dbgs() << " is not a register, nothing to be done\n"); continue; } if (!MO.getReg()) { - DEBUG(dbgs() << " is %%noreg, nothing to be done\n"); + LLVM_DEBUG(dbgs() << " is %%noreg, nothing to be done\n"); continue; } assert(OpdMapper.getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns != @@ -427,14 +427,14 @@ void RegisterBankInfo::applyDefaultMapping(const OperandsMapper &OpdMapper) { iterator_range<SmallVectorImpl<unsigned>::const_iterator> NewRegs = OpdMapper.getVRegs(OpIdx); if (NewRegs.begin() == NewRegs.end()) { - DEBUG(dbgs() << " has not been repaired, nothing to be done\n"); + LLVM_DEBUG(dbgs() << " has not been repaired, nothing to be done\n"); continue; } unsigned OrigReg = MO.getReg(); unsigned NewReg = *NewRegs.begin(); - DEBUG(dbgs() << " changed, replace " << printReg(OrigReg, nullptr)); + LLVM_DEBUG(dbgs() << " changed, replace " << printReg(OrigReg, nullptr)); MO.setReg(NewReg); - DEBUG(dbgs() << " with " << printReg(NewReg, nullptr)); + LLVM_DEBUG(dbgs() << " with " << printReg(NewReg, nullptr)); // The OperandsMapper creates plain scalar, we may have to fix that. // Check if the types match and if not, fix that. @@ -448,11 +448,11 @@ void RegisterBankInfo::applyDefaultMapping(const OperandsMapper &OpdMapper) { assert(OrigTy.getSizeInBits() <= NewTy.getSizeInBits() && "Types with difference size cannot be handled by the default " "mapping"); - DEBUG(dbgs() << "\nChange type of new opd from " << NewTy << " to " - << OrigTy); + LLVM_DEBUG(dbgs() << "\nChange type of new opd from " << NewTy << " to " + << OrigTy); MRI.setType(NewReg, OrigTy); } - DEBUG(dbgs() << '\n'); + LLVM_DEBUG(dbgs() << '\n'); } } diff --git a/llvm/lib/CodeGen/GlobalISel/Utils.cpp b/llvm/lib/CodeGen/GlobalISel/Utils.cpp index f5b97656c3b..055f4cb6458 100644 --- a/llvm/lib/CodeGen/GlobalISel/Utils.cpp +++ b/llvm/lib/CodeGen/GlobalISel/Utils.cpp @@ -101,7 +101,7 @@ bool llvm::constrainSelectedInstRegOperands(MachineInstr &I, if (!MO.isReg()) continue; - DEBUG(dbgs() << "Converting operand: " << MO << '\n'); + LLVM_DEBUG(dbgs() << "Converting operand: " << MO << '\n'); assert(MO.isReg() && "Unsupported non-reg operand"); unsigned Reg = MO.getReg(); diff --git a/llvm/lib/CodeGen/GlobalMerge.cpp b/llvm/lib/CodeGen/GlobalMerge.cpp index be4ba4d75a5..cda5861f676 100644 --- a/llvm/lib/CodeGen/GlobalMerge.cpp +++ b/llvm/lib/CodeGen/GlobalMerge.cpp @@ -442,8 +442,8 @@ bool GlobalMerge::doMerge(const SmallVectorImpl<GlobalVariable *> &Globals, Type *Int32Ty = Type::getInt32Ty(M.getContext()); auto &DL = M.getDataLayout(); - DEBUG(dbgs() << " Trying to merge set, starts with #" - << GlobalSet.find_first() << "\n"); + LLVM_DEBUG(dbgs() << " Trying to merge set, starts with #" + << GlobalSet.find_first() << "\n"); ssize_t i = GlobalSet.find_first(); while (i != -1) { diff --git a/llvm/lib/CodeGen/IfConversion.cpp b/llvm/lib/CodeGen/IfConversion.cpp index 0ae28abc7f1..83c168bf686 100644 --- a/llvm/lib/CodeGen/IfConversion.cpp +++ b/llvm/lib/CodeGen/IfConversion.cpp @@ -361,14 +361,14 @@ bool IfConverter::runOnMachineFunction(MachineFunction &MF) { getAnalysisIfAvailable<MachineModuleInfo>()); } - DEBUG(dbgs() << "\nIfcvt: function (" << ++FnNum << ") \'" - << MF.getName() << "\'"); + LLVM_DEBUG(dbgs() << "\nIfcvt: function (" << ++FnNum << ") \'" + << MF.getName() << "\'"); if (FnNum < IfCvtFnStart || (IfCvtFnStop != -1 && FnNum > IfCvtFnStop)) { - DEBUG(dbgs() << " skipped\n"); + LLVM_DEBUG(dbgs() << " skipped\n"); return false; } - DEBUG(dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "\n"); MF.RenumberBlocks(); BBAnalysis.resize(MF.getNumBlockIDs()); @@ -406,14 +406,14 @@ bool IfConverter::runOnMachineFunction(MachineFunction &MF) { case ICSimpleFalse: { bool isFalse = Kind == ICSimpleFalse; if ((isFalse && DisableSimpleF) || (!isFalse && DisableSimple)) break; - DEBUG(dbgs() << "Ifcvt (Simple" - << (Kind == ICSimpleFalse ? " false" : "") - << "): " << printMBBReference(*BBI.BB) << " (" - << ((Kind == ICSimpleFalse) ? BBI.FalseBB->getNumber() - : BBI.TrueBB->getNumber()) - << ") "); + LLVM_DEBUG(dbgs() << "Ifcvt (Simple" + << (Kind == ICSimpleFalse ? " false" : "") + << "): " << printMBBReference(*BBI.BB) << " (" + << ((Kind == ICSimpleFalse) ? BBI.FalseBB->getNumber() + : BBI.TrueBB->getNumber()) + << ") "); RetVal = IfConvertSimple(BBI, Kind); - DEBUG(dbgs() << (RetVal ? "succeeded!" : "failed!") << "\n"); + LLVM_DEBUG(dbgs() << (RetVal ? "succeeded!" : "failed!") << "\n"); if (RetVal) { if (isFalse) ++NumSimpleFalse; else ++NumSimple; @@ -430,16 +430,16 @@ bool IfConverter::runOnMachineFunction(MachineFunction &MF) { if (DisableTriangleR && !isFalse && isRev) break; if (DisableTriangleF && isFalse && !isRev) break; if (DisableTriangleFR && isFalse && isRev) break; - DEBUG(dbgs() << "Ifcvt (Triangle"); + LLVM_DEBUG(dbgs() << "Ifcvt (Triangle"); if (isFalse) - DEBUG(dbgs() << " false"); + LLVM_DEBUG(dbgs() << " false"); if (isRev) - DEBUG(dbgs() << " rev"); - DEBUG(dbgs() << "): " << printMBBReference(*BBI.BB) - << " (T:" << BBI.TrueBB->getNumber() - << ",F:" << BBI.FalseBB->getNumber() << ") "); + LLVM_DEBUG(dbgs() << " rev"); + LLVM_DEBUG(dbgs() << "): " << printMBBReference(*BBI.BB) + << " (T:" << BBI.TrueBB->getNumber() + << ",F:" << BBI.FalseBB->getNumber() << ") "); RetVal = IfConvertTriangle(BBI, Kind); - DEBUG(dbgs() << (RetVal ? "succeeded!" : "failed!") << "\n"); + LLVM_DEBUG(dbgs() << (RetVal ? "succeeded!" : "failed!") << "\n"); if (RetVal) { if (isFalse) { if (isRev) ++NumTriangleFRev; @@ -453,24 +453,25 @@ bool IfConverter::runOnMachineFunction(MachineFunction &MF) { } case ICDiamond: if (DisableDiamond) break; - DEBUG(dbgs() << "Ifcvt (Diamond): " << printMBBReference(*BBI.BB) - << " (T:" << BBI.TrueBB->getNumber() - << ",F:" << BBI.FalseBB->getNumber() << ") "); + LLVM_DEBUG(dbgs() << "Ifcvt (Diamond): " << printMBBReference(*BBI.BB) + << " (T:" << BBI.TrueBB->getNumber() + << ",F:" << BBI.FalseBB->getNumber() << ") "); RetVal = IfConvertDiamond(BBI, Kind, NumDups, NumDups2, Token->TClobbersPred, Token->FClobbersPred); - DEBUG(dbgs() << (RetVal ? "succeeded!" : "failed!") << "\n"); + LLVM_DEBUG(dbgs() << (RetVal ? "succeeded!" : "failed!") << "\n"); if (RetVal) ++NumDiamonds; break; case ICForkedDiamond: if (DisableForkedDiamond) break; - DEBUG(dbgs() << "Ifcvt (Forked Diamond): " << printMBBReference(*BBI.BB) - << " (T:" << BBI.TrueBB->getNumber() - << ",F:" << BBI.FalseBB->getNumber() << ") "); + LLVM_DEBUG(dbgs() << "Ifcvt (Forked Diamond): " + << printMBBReference(*BBI.BB) + << " (T:" << BBI.TrueBB->getNumber() + << ",F:" << BBI.FalseBB->getNumber() << ") "); RetVal = IfConvertForkedDiamond(BBI, Kind, NumDups, NumDups2, Token->TClobbersPred, Token->FClobbersPred); - DEBUG(dbgs() << (RetVal ? "succeeded!" : "failed!") << "\n"); + LLVM_DEBUG(dbgs() << (RetVal ? "succeeded!" : "failed!") << "\n"); if (RetVal) ++NumForkedDiamonds; break; } diff --git a/llvm/lib/CodeGen/InlineSpiller.cpp b/llvm/lib/CodeGen/InlineSpiller.cpp index 3939e235995..478ea9b2bc5 100644 --- a/llvm/lib/CodeGen/InlineSpiller.cpp +++ b/llvm/lib/CodeGen/InlineSpiller.cpp @@ -336,7 +336,7 @@ void InlineSpiller::collectRegsToSpill() { if (isRegToSpill(SnipReg)) continue; RegsToSpill.push_back(SnipReg); - DEBUG(dbgs() << "\talso spill snippet " << SnipLI << '\n'); + LLVM_DEBUG(dbgs() << "\talso spill snippet " << SnipLI << '\n'); ++NumSnippets; } } @@ -388,8 +388,8 @@ bool InlineSpiller::hoistSpillInsideBB(LiveInterval &SpillLI, LiveInterval &OrigLI = LIS.getInterval(Original); VNInfo *OrigVNI = OrigLI.getVNInfoAt(Idx); StackInt->MergeValueInAsValue(OrigLI, OrigVNI, StackInt->getValNumInfo(0)); - DEBUG(dbgs() << "\tmerged orig valno " << OrigVNI->id << ": " - << *StackInt << '\n'); + LLVM_DEBUG(dbgs() << "\tmerged orig valno " << OrigVNI->id << ": " + << *StackInt << '\n'); // We are going to spill SrcVNI immediately after its def, so clear out // any later spills of the same value. @@ -410,7 +410,7 @@ bool InlineSpiller::hoistSpillInsideBB(LiveInterval &SpillLI, MRI.getRegClass(SrcReg), &TRI); --MII; // Point to store instruction. LIS.InsertMachineInstrInMaps(*MII); - DEBUG(dbgs() << "\thoisted: " << SrcVNI->def << '\t' << *MII); + LLVM_DEBUG(dbgs() << "\thoisted: " << SrcVNI->def << '\t' << *MII); HSpiller.addToMergeableSpills(*MII, StackSlot, Original); ++NumSpills; @@ -429,8 +429,8 @@ void InlineSpiller::eliminateRedundantSpills(LiveInterval &SLI, VNInfo *VNI) { LiveInterval *LI; std::tie(LI, VNI) = WorkList.pop_back_val(); unsigned Reg = LI->reg; - DEBUG(dbgs() << "Checking redundant spills for " - << VNI->id << '@' << VNI->def << " in " << *LI << '\n'); + LLVM_DEBUG(dbgs() << "Checking redundant spills for " << VNI->id << '@' + << VNI->def << " in " << *LI << '\n'); // Regs to spill are taken care of. if (isRegToSpill(Reg)) @@ -438,7 +438,7 @@ void InlineSpiller::eliminateRedundantSpills(LiveInterval &SLI, VNInfo *VNI) { // Add all of VNI's live range to StackInt. StackInt->MergeValueInAsValue(*LI, VNI, StackInt->getValNumInfo(0)); - DEBUG(dbgs() << "Merged to stack int: " << *StackInt << '\n'); + LLVM_DEBUG(dbgs() << "Merged to stack int: " << *StackInt << '\n'); // Find all spills and copies of VNI. for (MachineRegisterInfo::use_instr_nodbg_iterator @@ -466,7 +466,7 @@ void InlineSpiller::eliminateRedundantSpills(LiveInterval &SLI, VNInfo *VNI) { // Erase spills. int FI; if (Reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot) { - DEBUG(dbgs() << "Redundant spill " << Idx << '\t' << MI); + LLVM_DEBUG(dbgs() << "Redundant spill " << Idx << '\t' << MI); // eliminateDeadDefs won't normally remove stores, so switch opcode. MI.setDesc(TII.get(TargetOpcode::KILL)); DeadDefs.push_back(&MI); @@ -528,13 +528,13 @@ bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, MachineInstr &MI) { VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex()); if (!ParentVNI) { - DEBUG(dbgs() << "\tadding <undef> flags: "); + LLVM_DEBUG(dbgs() << "\tadding <undef> flags: "); for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { MachineOperand &MO = MI.getOperand(i); if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) MO.setIsUndef(); } - DEBUG(dbgs() << UseIdx << '\t' << MI); + LLVM_DEBUG(dbgs() << UseIdx << '\t' << MI); return true; } @@ -548,7 +548,7 @@ bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, MachineInstr &MI) { if (!Edit->canRematerializeAt(RM, OrigVNI, UseIdx, false)) { markValueUsed(&VirtReg, ParentVNI); - DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << MI); + LLVM_DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << MI); return false; } @@ -556,7 +556,7 @@ bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, MachineInstr &MI) { // same register for uses and defs. if (RI.Tied) { markValueUsed(&VirtReg, ParentVNI); - DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << MI); + LLVM_DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << MI); return false; } @@ -582,8 +582,8 @@ bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, MachineInstr &MI) { NewMI->setDebugLoc(MI.getDebugLoc()); (void)DefIdx; - DEBUG(dbgs() << "\tremat: " << DefIdx << '\t' - << *LIS.getInstructionFromIndex(DefIdx)); + LLVM_DEBUG(dbgs() << "\tremat: " << DefIdx << '\t' + << *LIS.getInstructionFromIndex(DefIdx)); // Replace operands for (const auto &OpPair : Ops) { @@ -593,7 +593,7 @@ bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, MachineInstr &MI) { MO.setIsKill(); } } - DEBUG(dbgs() << "\t " << UseIdx << '\t' << MI << '\n'); + LLVM_DEBUG(dbgs() << "\t " << UseIdx << '\t' << MI << '\n'); ++NumRemats; return true; @@ -638,7 +638,7 @@ void InlineSpiller::reMaterializeAll() { MI->addRegisterDead(Reg, &TRI); if (!MI->allDefsAreDead()) continue; - DEBUG(dbgs() << "All defs dead: " << *MI); + LLVM_DEBUG(dbgs() << "All defs dead: " << *MI); DeadDefs.push_back(MI); } } @@ -647,7 +647,7 @@ void InlineSpiller::reMaterializeAll() { // deleted here. if (DeadDefs.empty()) return; - DEBUG(dbgs() << "Remat created " << DeadDefs.size() << " dead defs.\n"); + LLVM_DEBUG(dbgs() << "Remat created " << DeadDefs.size() << " dead defs.\n"); Edit->eliminateDeadDefs(DeadDefs, RegsToSpill, AA); // LiveRangeEdit::eliminateDeadDef is used to remove dead define instructions @@ -670,7 +670,8 @@ void InlineSpiller::reMaterializeAll() { RegsToSpill[ResultPos++] = Reg; } RegsToSpill.erase(RegsToSpill.begin() + ResultPos, RegsToSpill.end()); - DEBUG(dbgs() << RegsToSpill.size() << " registers to spill after remat.\n"); + LLVM_DEBUG(dbgs() << RegsToSpill.size() + << " registers to spill after remat.\n"); } //===----------------------------------------------------------------------===// @@ -692,7 +693,7 @@ bool InlineSpiller::coalesceStackAccess(MachineInstr *MI, unsigned Reg) { if (!IsLoad) HSpiller.rmFromMergeableSpills(*MI, StackSlot); - DEBUG(dbgs() << "Coalescing stack access: " << *MI); + LLVM_DEBUG(dbgs() << "Coalescing stack access: " << *MI); LIS.RemoveMachineInstrFromMaps(*MI); MI->eraseFromParent(); @@ -849,8 +850,8 @@ foldMemoryOperand(ArrayRef<std::pair<MachineInstr *, unsigned>> Ops, FoldMI->RemoveOperand(i - 1); } - DEBUG(dumpMachineInstrRangeWithSlotIndex(MIS.begin(), MIS.end(), LIS, - "folded")); + LLVM_DEBUG(dumpMachineInstrRangeWithSlotIndex(MIS.begin(), MIS.end(), LIS, + "folded")); if (!WasCopy) ++NumFolded; @@ -873,8 +874,8 @@ void InlineSpiller::insertReload(unsigned NewVReg, LIS.InsertMachineInstrRangeInMaps(MIS.begin(), MI); - DEBUG(dumpMachineInstrRangeWithSlotIndex(MIS.begin(), MI, LIS, "reload", - NewVReg)); + LLVM_DEBUG(dumpMachineInstrRangeWithSlotIndex(MIS.begin(), MI, LIS, "reload", + NewVReg)); ++NumReloads; } @@ -913,8 +914,8 @@ void InlineSpiller::insertSpill(unsigned NewVReg, bool isKill, LIS.InsertMachineInstrRangeInMaps(std::next(MI), MIS.end()); - DEBUG(dumpMachineInstrRangeWithSlotIndex(std::next(MI), MIS.end(), LIS, - "spill")); + LLVM_DEBUG(dumpMachineInstrRangeWithSlotIndex(std::next(MI), MIS.end(), LIS, + "spill")); ++NumSpills; if (IsRealSpill) HSpiller.addToMergeableSpills(*std::next(MI), StackSlot, Original); @@ -922,7 +923,7 @@ void InlineSpiller::insertSpill(unsigned NewVReg, bool isKill, /// spillAroundUses - insert spill code around each use of Reg. void InlineSpiller::spillAroundUses(unsigned Reg) { - DEBUG(dbgs() << "spillAroundUses " << printReg(Reg) << '\n'); + LLVM_DEBUG(dbgs() << "spillAroundUses " << printReg(Reg) << '\n'); LiveInterval &OldLI = LIS.getInterval(Reg); // Iterate over instructions using Reg. @@ -935,7 +936,7 @@ void InlineSpiller::spillAroundUses(unsigned Reg) { if (MI->isDebugInstr()) { // Modify DBG_VALUE now that the value is in a spill slot. MachineBasicBlock *MBB = MI->getParent(); - DEBUG(dbgs() << "Modifying debug info due to spill:\t" << *MI); + LLVM_DEBUG(dbgs() << "Modifying debug info due to spill:\t" << *MI); buildDbgValueForSpill(*MBB, MI, *MI, StackSlot); MBB->erase(MI); continue; @@ -966,7 +967,7 @@ void InlineSpiller::spillAroundUses(unsigned Reg) { if (SibReg && isSibling(SibReg)) { // This may actually be a copy between snippets. if (isRegToSpill(SibReg)) { - DEBUG(dbgs() << "Found new snippet copy: " << *MI); + LLVM_DEBUG(dbgs() << "Found new snippet copy: " << *MI); SnippetCopies.insert(MI); continue; } @@ -1009,7 +1010,7 @@ void InlineSpiller::spillAroundUses(unsigned Reg) { hasLiveDef = true; } } - DEBUG(dbgs() << "\trewrite: " << Idx << '\t' << *MI << '\n'); + LLVM_DEBUG(dbgs() << "\trewrite: " << Idx << '\t' << *MI << '\n'); // FIXME: Use a second vreg if instruction has no tied ops. if (RI.Writes) @@ -1035,7 +1036,7 @@ void InlineSpiller::spillAll() { for (unsigned Reg : RegsToSpill) StackInt->MergeSegmentsInAsValue(LIS.getInterval(Reg), StackInt->getValNumInfo(0)); - DEBUG(dbgs() << "Merged spilled regs: " << *StackInt << '\n'); + LLVM_DEBUG(dbgs() << "Merged spilled regs: " << *StackInt << '\n'); // Spill around uses of all RegsToSpill. for (unsigned Reg : RegsToSpill) @@ -1043,7 +1044,7 @@ void InlineSpiller::spillAll() { // Hoisted spills may cause dead code. if (!DeadDefs.empty()) { - DEBUG(dbgs() << "Eliminating " << DeadDefs.size() << " dead defs\n"); + LLVM_DEBUG(dbgs() << "Eliminating " << DeadDefs.size() << " dead defs\n"); Edit->eliminateDeadDefs(DeadDefs, RegsToSpill, AA); } @@ -1075,10 +1076,10 @@ void InlineSpiller::spill(LiveRangeEdit &edit) { StackSlot = VRM.getStackSlot(Original); StackInt = nullptr; - DEBUG(dbgs() << "Inline spilling " - << TRI.getRegClassName(MRI.getRegClass(edit.getReg())) - << ':' << edit.getParent() - << "\nFrom original " << printReg(Original) << '\n'); + LLVM_DEBUG(dbgs() << "Inline spilling " + << TRI.getRegClassName(MRI.getRegClass(edit.getReg())) + << ':' << edit.getParent() << "\nFrom original " + << printReg(Original) << '\n'); assert(edit.getParent().isSpillable() && "Attempting to spill already spilled value."); assert(DeadDefs.empty() && "Previous spill didn't remove dead defs"); @@ -1262,11 +1263,11 @@ void HoistSpillHelper::getVisitOrders( "Orders have different size with WorkSet"); #ifndef NDEBUG - DEBUG(dbgs() << "Orders size is " << Orders.size() << "\n"); + LLVM_DEBUG(dbgs() << "Orders size is " << Orders.size() << "\n"); SmallVector<MachineDomTreeNode *, 32>::reverse_iterator RIt = Orders.rbegin(); for (; RIt != Orders.rend(); RIt++) - DEBUG(dbgs() << "BB" << (*RIt)->getBlock()->getNumber() << ","); - DEBUG(dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "BB" << (*RIt)->getBlock()->getNumber() << ","); + LLVM_DEBUG(dbgs() << "\n"); #endif } @@ -1375,7 +1376,7 @@ void HoistSpillHelper::runHoistSpills( // Current Block is the BB containing the new hoisted spill. Add it to // SpillsToKeep. LiveReg is the source of the new spill. SpillsToKeep[*RIt] = LiveReg; - DEBUG({ + LLVM_DEBUG({ dbgs() << "spills in BB: "; for (const auto Rspill : SpillsInSubTree) dbgs() << Rspill->getBlock()->getNumber() << " "; @@ -1431,7 +1432,7 @@ void HoistSpillHelper::hoistAllSpills() { if (Ent.second.empty()) continue; - DEBUG({ + LLVM_DEBUG({ dbgs() << "\nFor Slot" << Slot << " and VN" << OrigVNI->id << ":\n" << "Equal spills in BB: "; for (const auto spill : EqValSpills) @@ -1446,7 +1447,7 @@ void HoistSpillHelper::hoistAllSpills() { runHoistSpills(OrigLI, *OrigVNI, EqValSpills, SpillsToRm, SpillsToIns); - DEBUG({ + LLVM_DEBUG({ dbgs() << "Finally inserted spills in BB: "; for (const auto Ispill : SpillsToIns) dbgs() << Ispill.first->getNumber() << " "; diff --git a/llvm/lib/CodeGen/InterleavedAccessPass.cpp b/llvm/lib/CodeGen/InterleavedAccessPass.cpp index e3dc9649473..fd2ff162630 100644 --- a/llvm/lib/CodeGen/InterleavedAccessPass.cpp +++ b/llvm/lib/CodeGen/InterleavedAccessPass.cpp @@ -332,7 +332,7 @@ bool InterleavedAccess::lowerInterleavedLoad( if (!tryReplaceExtracts(Extracts, Shuffles)) return false; - DEBUG(dbgs() << "IA: Found an interleaved load: " << *LI << "\n"); + LLVM_DEBUG(dbgs() << "IA: Found an interleaved load: " << *LI << "\n"); // Try to create target specific intrinsics to replace the load and shuffles. if (!TLI->lowerInterleavedLoad(LI, Shuffles, Indices, Factor)) @@ -424,7 +424,7 @@ bool InterleavedAccess::lowerInterleavedStore( if (!isReInterleaveMask(SVI->getShuffleMask(), Factor, MaxFactor, OpNumElts)) return false; - DEBUG(dbgs() << "IA: Found an interleaved store: " << *SI << "\n"); + LLVM_DEBUG(dbgs() << "IA: Found an interleaved store: " << *SI << "\n"); // Try to create target specific intrinsics to replace the store and shuffle. if (!TLI->lowerInterleavedStore(SI, SVI, Factor)) @@ -441,7 +441,7 @@ bool InterleavedAccess::runOnFunction(Function &F) { if (!TPC || !LowerInterleavedAccesses) return false; - DEBUG(dbgs() << "*** " << getPassName() << ": " << F.getName() << "\n"); + LLVM_DEBUG(dbgs() << "*** " << getPassName() << ": " << F.getName() << "\n"); DT = &getAnalysis<DominatorTreeWrapperPass>().getDomTree(); auto &TM = TPC->getTM<TargetMachine>(); diff --git a/llvm/lib/CodeGen/LazyMachineBlockFrequencyInfo.cpp b/llvm/lib/CodeGen/LazyMachineBlockFrequencyInfo.cpp index 996d40ca6e1..5b52cc66a29 100644 --- a/llvm/lib/CodeGen/LazyMachineBlockFrequencyInfo.cpp +++ b/llvm/lib/CodeGen/LazyMachineBlockFrequencyInfo.cpp @@ -57,23 +57,23 @@ MachineBlockFrequencyInfo & LazyMachineBlockFrequencyInfoPass::calculateIfNotAvailable() const { auto *MBFI = getAnalysisIfAvailable<MachineBlockFrequencyInfo>(); if (MBFI) { - DEBUG(dbgs() << "MachineBlockFrequencyInfo is available\n"); + LLVM_DEBUG(dbgs() << "MachineBlockFrequencyInfo is available\n"); return *MBFI; } auto &MBPI = getAnalysis<MachineBranchProbabilityInfo>(); auto *MLI = getAnalysisIfAvailable<MachineLoopInfo>(); auto *MDT = getAnalysisIfAvailable<MachineDominatorTree>(); - DEBUG(dbgs() << "Building MachineBlockFrequencyInfo on the fly\n"); - DEBUG(if (MLI) dbgs() << "LoopInfo is available\n"); + LLVM_DEBUG(dbgs() << "Building MachineBlockFrequencyInfo on the fly\n"); + LLVM_DEBUG(if (MLI) dbgs() << "LoopInfo is available\n"); if (!MLI) { - DEBUG(dbgs() << "Building LoopInfo on the fly\n"); + LLVM_DEBUG(dbgs() << "Building LoopInfo on the fly\n"); // First create a dominator tree. - DEBUG(if (MDT) dbgs() << "DominatorTree is available\n"); + LLVM_DEBUG(if (MDT) dbgs() << "DominatorTree is available\n"); if (!MDT) { - DEBUG(dbgs() << "Building DominatorTree on the fly\n"); + LLVM_DEBUG(dbgs() << "Building DominatorTree on the fly\n"); OwnedMDT = make_unique<MachineDominatorTree>(); OwnedMDT->getBase().recalculate(*MF); MDT = OwnedMDT.get(); diff --git a/llvm/lib/CodeGen/LiveDebugValues.cpp b/llvm/lib/CodeGen/LiveDebugValues.cpp index 0554908584e..82d8580ab75 100644 --- a/llvm/lib/CodeGen/LiveDebugValues.cpp +++ b/llvm/lib/CodeGen/LiveDebugValues.cpp @@ -480,8 +480,8 @@ void LiveDebugValues::transferSpillInst(MachineInstr &MI, // Check if the register is the location of a debug value. for (unsigned ID : OpenRanges.getVarLocs()) { if (VarLocIDs[ID].isDescribedByReg() == Reg) { - DEBUG(dbgs() << "Spilling Register " << printReg(Reg, TRI) << '(' - << VarLocIDs[ID].Var.getVar()->getName() << ")\n"); + LLVM_DEBUG(dbgs() << "Spilling Register " << printReg(Reg, TRI) << '(' + << VarLocIDs[ID].Var.getVar()->getName() << ")\n"); // Create a DBG_VALUE instruction to describe the Var in its spilled // location, but don't insert it yet to avoid invalidating the @@ -494,8 +494,8 @@ void LiveDebugValues::transferSpillInst(MachineInstr &MI, MachineInstr *SpDMI = BuildMI(*MF, DMI->getDebugLoc(), DMI->getDesc(), true, SpillBase, DMI->getDebugVariable(), SpillExpr); - DEBUG(dbgs() << "Creating DBG_VALUE inst for spill: "; - SpDMI->print(dbgs(), false, TII)); + LLVM_DEBUG(dbgs() << "Creating DBG_VALUE inst for spill: "; + SpDMI->print(dbgs(), false, TII)); // The newly created DBG_VALUE instruction SpDMI must be inserted after // MI. Keep track of the pairing. @@ -527,10 +527,12 @@ bool LiveDebugValues::transferTerminatorInst(MachineInstr &MI, if (OpenRanges.empty()) return false; - DEBUG(for (unsigned ID : OpenRanges.getVarLocs()) { - // Copy OpenRanges to OutLocs, if not already present. - dbgs() << "Add to OutLocs: "; VarLocIDs[ID].dump(); - }); + LLVM_DEBUG(for (unsigned ID + : OpenRanges.getVarLocs()) { + // Copy OpenRanges to OutLocs, if not already present. + dbgs() << "Add to OutLocs: "; + VarLocIDs[ID].dump(); + }); VarLocSet &VLS = OutLocs[CurMBB]; Changed = VLS |= OpenRanges.getVarLocs(); OpenRanges.clear(); @@ -556,7 +558,7 @@ bool LiveDebugValues::transfer(MachineInstr &MI, OpenRangesSet &OpenRanges, bool LiveDebugValues::join(MachineBasicBlock &MBB, VarLocInMBB &OutLocs, VarLocInMBB &InLocs, const VarLocMap &VarLocIDs, SmallPtrSet<const MachineBasicBlock *, 16> &Visited) { - DEBUG(dbgs() << "join MBB: " << MBB.getName() << "\n"); + LLVM_DEBUG(dbgs() << "join MBB: " << MBB.getName() << "\n"); bool Changed = false; VarLocSet InLocsT; // Temporary incoming locations. @@ -616,7 +618,7 @@ bool LiveDebugValues::join(MachineBasicBlock &MBB, VarLocInMBB &OutLocs, DMI->getDebugVariable(), DMI->getDebugExpression()); if (DMI->isIndirectDebugValue()) MI->getOperand(1).setImm(DMI->getOperand(1).getImm()); - DEBUG(dbgs() << "Inserted: "; MI->dump();); + LLVM_DEBUG(dbgs() << "Inserted: "; MI->dump();); ILS.set(ID); ++NumInserted; Changed = true; @@ -627,7 +629,7 @@ bool LiveDebugValues::join(MachineBasicBlock &MBB, VarLocInMBB &OutLocs, /// Calculate the liveness information for the given machine function and /// extend ranges across basic blocks. bool LiveDebugValues::ExtendRanges(MachineFunction &MF) { - DEBUG(dbgs() << "\nDebug Range Extension\n"); + LLVM_DEBUG(dbgs() << "\nDebug Range Extension\n"); bool Changed = false; bool OLChanged = false; @@ -658,8 +660,8 @@ bool LiveDebugValues::ExtendRanges(MachineFunction &MF) { transfer(MI, OpenRanges, OutLocs, VarLocIDs, Spills, /*transferSpills=*/false); - DEBUG(printVarLocInMBB(MF, OutLocs, VarLocIDs, "OutLocs after initialization", - dbgs())); + LLVM_DEBUG(printVarLocInMBB(MF, OutLocs, VarLocIDs, + "OutLocs after initialization", dbgs())); ReversePostOrderTraversal<MachineFunction *> RPOT(&MF); unsigned int RPONumber = 0; @@ -679,7 +681,7 @@ bool LiveDebugValues::ExtendRanges(MachineFunction &MF) { // thing twice. We could avoid this with a custom priority queue, but this // is probably not worth it. SmallPtrSet<MachineBasicBlock *, 16> OnPending; - DEBUG(dbgs() << "Processing Worklist\n"); + LLVM_DEBUG(dbgs() << "Processing Worklist\n"); while (!Worklist.empty()) { MachineBasicBlock *MBB = OrderToBB[Worklist.top()]; Worklist.pop(); @@ -701,10 +703,10 @@ bool LiveDebugValues::ExtendRanges(MachineFunction &MF) { SP.DebugInst); Spills.clear(); - DEBUG(printVarLocInMBB(MF, OutLocs, VarLocIDs, - "OutLocs after propagating", dbgs())); - DEBUG(printVarLocInMBB(MF, InLocs, VarLocIDs, - "InLocs after propagating", dbgs())); + LLVM_DEBUG(printVarLocInMBB(MF, OutLocs, VarLocIDs, + "OutLocs after propagating", dbgs())); + LLVM_DEBUG(printVarLocInMBB(MF, InLocs, VarLocIDs, + "InLocs after propagating", dbgs())); if (OLChanged) { OLChanged = false; @@ -721,8 +723,8 @@ bool LiveDebugValues::ExtendRanges(MachineFunction &MF) { assert(Pending.empty() && "Pending should be empty"); } - DEBUG(printVarLocInMBB(MF, OutLocs, VarLocIDs, "Final OutLocs", dbgs())); - DEBUG(printVarLocInMBB(MF, InLocs, VarLocIDs, "Final InLocs", dbgs())); + LLVM_DEBUG(printVarLocInMBB(MF, OutLocs, VarLocIDs, "Final OutLocs", dbgs())); + LLVM_DEBUG(printVarLocInMBB(MF, InLocs, VarLocIDs, "Final InLocs", dbgs())); return Changed; } diff --git a/llvm/lib/CodeGen/LiveDebugVariables.cpp b/llvm/lib/CodeGen/LiveDebugVariables.cpp index 9940b294931..91c5e8565c0 100644 --- a/llvm/lib/CodeGen/LiveDebugVariables.cpp +++ b/llvm/lib/CodeGen/LiveDebugVariables.cpp @@ -511,7 +511,7 @@ bool LDVImpl::handleDebugValue(MachineInstr &MI, SlotIndex Idx) { if (MI.getNumOperands() != 4 || !(MI.getOperand(1).isReg() || MI.getOperand(1).isImm()) || !MI.getOperand(2).isMetadata()) { - DEBUG(dbgs() << "Can't handle " << MI); + LLVM_DEBUG(dbgs() << "Can't handle " << MI); return false; } @@ -530,8 +530,8 @@ bool LDVImpl::handleDebugValue(MachineInstr &MI, SlotIndex Idx) { // The DBG_VALUE is described by a virtual register that does not have a // live interval. Discard the DBG_VALUE. Discard = true; - DEBUG(dbgs() << "Discarding debug info (no LIS interval): " - << Idx << " " << MI); + LLVM_DEBUG(dbgs() << "Discarding debug info (no LIS interval): " << Idx + << " " << MI); } else { // The DBG_VALUE is only valid if either Reg is live out from Idx, or Reg // is defined dead at Idx (where Idx is the slot index for the instruction @@ -542,8 +542,8 @@ bool LDVImpl::handleDebugValue(MachineInstr &MI, SlotIndex Idx) { // We have found a DBG_VALUE with the value in a virtual register that // is not live. Discard the DBG_VALUE. Discard = true; - DEBUG(dbgs() << "Discarding debug info (reg not live): " - << Idx << " " << MI); + LLVM_DEBUG(dbgs() << "Discarding debug info (reg not live): " << Idx + << " " << MI); } } } @@ -688,7 +688,8 @@ void UserValue::addDefsFromCopies( if (CopyValues.empty()) return; - DEBUG(dbgs() << "Got " << CopyValues.size() << " copies of " << *LI << '\n'); + LLVM_DEBUG(dbgs() << "Got " << CopyValues.size() << " copies of " << *LI + << '\n'); // Try to add defs of the copied values for each kill point. for (unsigned i = 0, e = Kills.size(); i != e; ++i) { @@ -702,8 +703,8 @@ void UserValue::addDefsFromCopies( LocMap::iterator I = locInts.find(Idx); if (I.valid() && I.start() <= Idx) continue; - DEBUG(dbgs() << "Kill at " << Idx << " covered by valno #" - << DstVNI->id << " in " << *DstLI << '\n'); + LLVM_DEBUG(dbgs() << "Kill at " << Idx << " covered by valno #" + << DstVNI->id << " in " << *DstLI << '\n'); MachineInstr *CopyMI = LIS.getInstructionFromIndex(DstVNI->def); assert(CopyMI && CopyMI->isCopy() && "Bad copy value"); unsigned LocNo = getLocationNo(CopyMI->getOperand(0)); @@ -851,12 +852,12 @@ bool LDVImpl::runOnMachineFunction(MachineFunction &mf) { MF = &mf; LIS = &pass.getAnalysis<LiveIntervals>(); TRI = mf.getSubtarget().getRegisterInfo(); - DEBUG(dbgs() << "********** COMPUTING LIVE DEBUG VARIABLES: " - << mf.getName() << " **********\n"); + LLVM_DEBUG(dbgs() << "********** COMPUTING LIVE DEBUG VARIABLES: " + << mf.getName() << " **********\n"); bool Changed = collectDebugValues(mf); computeIntervals(); - DEBUG(print(dbgs())); + LLVM_DEBUG(print(dbgs())); ModifiedMF = Changed; return Changed; } @@ -902,7 +903,7 @@ LiveDebugVariables::~LiveDebugVariables() { bool UserValue::splitLocation(unsigned OldLocNo, ArrayRef<unsigned> NewRegs, LiveIntervals& LIS) { - DEBUG({ + LLVM_DEBUG({ dbgs() << "Splitting Loc" << OldLocNo << '\t'; print(dbgs(), nullptr); }); @@ -985,8 +986,8 @@ UserValue::splitLocation(unsigned OldLocNo, ArrayRef<unsigned> NewRegs, while (LocMapI.valid()) { DbgValueLocation v = LocMapI.value(); if (v.locNo() == OldLocNo) { - DEBUG(dbgs() << "Erasing [" << LocMapI.start() << ';' - << LocMapI.stop() << ")\n"); + LLVM_DEBUG(dbgs() << "Erasing [" << LocMapI.start() << ';' + << LocMapI.stop() << ")\n"); LocMapI.erase(); } else { if (v.locNo() > OldLocNo) @@ -995,7 +996,10 @@ UserValue::splitLocation(unsigned OldLocNo, ArrayRef<unsigned> NewRegs, } } - DEBUG({dbgs() << "Split result: \t"; print(dbgs(), nullptr);}); + LLVM_DEBUG({ + dbgs() << "Split result: \t"; + print(dbgs(), nullptr); + }); return DidChange; } @@ -1213,11 +1217,11 @@ void UserValue::emitDebugValues(VirtRegMap *VRM, LiveIntervals &LIS, if (trimmedDefs.count(Start)) Start = Start.getPrevIndex(); - DEBUG(dbgs() << "\t[" << Start << ';' << Stop << "):" << Loc.locNo()); + LLVM_DEBUG(dbgs() << "\t[" << Start << ';' << Stop << "):" << Loc.locNo()); MachineFunction::iterator MBB = LIS.getMBBFromIndex(Start)->getIterator(); SlotIndex MBBEnd = LIS.getMBBEndIdx(&*MBB); - DEBUG(dbgs() << ' ' << printMBBReference(*MBB) << '-' << MBBEnd); + LLVM_DEBUG(dbgs() << ' ' << printMBBReference(*MBB) << '-' << MBBEnd); insertDebugValue(&*MBB, Start, Stop, Loc, Spilled, LIS, TII, TRI); // This interval may span multiple basic blocks. // Insert a DBG_VALUE into each one. @@ -1227,10 +1231,10 @@ void UserValue::emitDebugValues(VirtRegMap *VRM, LiveIntervals &LIS, if (++MBB == MFEnd) break; MBBEnd = LIS.getMBBEndIdx(&*MBB); - DEBUG(dbgs() << ' ' << printMBBReference(*MBB) << '-' << MBBEnd); + LLVM_DEBUG(dbgs() << ' ' << printMBBReference(*MBB) << '-' << MBBEnd); insertDebugValue(&*MBB, Start, Stop, Loc, Spilled, LIS, TII, TRI); } - DEBUG(dbgs() << '\n'); + LLVM_DEBUG(dbgs() << '\n'); if (MBB == MFEnd) break; @@ -1239,13 +1243,13 @@ void UserValue::emitDebugValues(VirtRegMap *VRM, LiveIntervals &LIS, } void LDVImpl::emitDebugValues(VirtRegMap *VRM) { - DEBUG(dbgs() << "********** EMITTING LIVE DEBUG VARIABLES **********\n"); + LLVM_DEBUG(dbgs() << "********** EMITTING LIVE DEBUG VARIABLES **********\n"); if (!MF) return; const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); BitVector SpilledLocations; for (unsigned i = 0, e = userValues.size(); i != e; ++i) { - DEBUG(userValues[i]->print(dbgs(), TRI)); + LLVM_DEBUG(userValues[i]->print(dbgs(), TRI)); userValues[i]->rewriteLocations(*VRM, *TRI, SpilledLocations); userValues[i]->emitDebugValues(VRM, *LIS, *TII, *TRI, SpilledLocations); } diff --git a/llvm/lib/CodeGen/LiveIntervals.cpp b/llvm/lib/CodeGen/LiveIntervals.cpp index ed0a62b99f2..f4a56a343a9 100644 --- a/llvm/lib/CodeGen/LiveIntervals.cpp +++ b/llvm/lib/CodeGen/LiveIntervals.cpp @@ -148,7 +148,7 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) { for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i) getRegUnit(i); } - DEBUG(dump()); + LLVM_DEBUG(dump()); return true; } @@ -311,7 +311,7 @@ void LiveIntervals::computeRegUnitRange(LiveRange &LR, unsigned Unit) { /// entering the entry block or a landing pad. void LiveIntervals::computeLiveInRegUnits() { RegUnitRanges.resize(TRI->getNumRegUnits()); - DEBUG(dbgs() << "Computing live-in reg-units in ABI blocks.\n"); + LLVM_DEBUG(dbgs() << "Computing live-in reg-units in ABI blocks.\n"); // Keep track of the live range sets allocated. SmallVector<unsigned, 8> NewRanges; @@ -324,7 +324,7 @@ void LiveIntervals::computeLiveInRegUnits() { // Create phi-defs at Begin for all live-in registers. SlotIndex Begin = Indexes->getMBBStartIdx(&MBB); - DEBUG(dbgs() << Begin << "\t" << printMBBReference(MBB)); + LLVM_DEBUG(dbgs() << Begin << "\t" << printMBBReference(MBB)); for (const auto &LI : MBB.liveins()) { for (MCRegUnitIterator Units(LI.PhysReg, TRI); Units.isValid(); ++Units) { unsigned Unit = *Units; @@ -336,12 +336,12 @@ void LiveIntervals::computeLiveInRegUnits() { } VNInfo *VNI = LR->createDeadDef(Begin, getVNInfoAllocator()); (void)VNI; - DEBUG(dbgs() << ' ' << printRegUnit(Unit, TRI) << '#' << VNI->id); + LLVM_DEBUG(dbgs() << ' ' << printRegUnit(Unit, TRI) << '#' << VNI->id); } } - DEBUG(dbgs() << '\n'); + LLVM_DEBUG(dbgs() << '\n'); } - DEBUG(dbgs() << "Created " << NewRanges.size() << " new intervals.\n"); + LLVM_DEBUG(dbgs() << "Created " << NewRanges.size() << " new intervals.\n"); // Compute the 'normal' part of the ranges. for (unsigned Unit : NewRanges) @@ -397,7 +397,7 @@ static void extendSegmentsToUses(LiveRange &LR, const SlotIndexes &Indexes, } // VNI is live-in to MBB. - DEBUG(dbgs() << " live-in at " << BlockStart << '\n'); + LLVM_DEBUG(dbgs() << " live-in at " << BlockStart << '\n'); LR.addSegment(LiveRange::Segment(BlockStart, Idx, VNI)); // Make sure VNI is live-out from the predecessors. @@ -414,7 +414,7 @@ static void extendSegmentsToUses(LiveRange &LR, const SlotIndexes &Indexes, bool LiveIntervals::shrinkToUses(LiveInterval *li, SmallVectorImpl<MachineInstr*> *dead) { - DEBUG(dbgs() << "Shrink: " << *li << '\n'); + LLVM_DEBUG(dbgs() << "Shrink: " << *li << '\n'); assert(TargetRegisterInfo::isVirtualRegister(li->reg) && "Can only shrink virtual registers"); @@ -443,9 +443,10 @@ bool LiveIntervals::shrinkToUses(LiveInterval *li, // This shouldn't happen: readsVirtualRegister returns true, but there is // no live value. It is likely caused by a target getting <undef> flags // wrong. - DEBUG(dbgs() << Idx << '\t' << UseMI - << "Warning: Instr claims to read non-existent value in " - << *li << '\n'); + LLVM_DEBUG( + dbgs() << Idx << '\t' << UseMI + << "Warning: Instr claims to read non-existent value in " + << *li << '\n'); continue; } // Special case: An early-clobber tied operand reads and writes the @@ -466,7 +467,7 @@ bool LiveIntervals::shrinkToUses(LiveInterval *li, // Handle dead values. bool CanSeparate = computeDeadValues(*li, dead); - DEBUG(dbgs() << "Shrunk: " << *li << '\n'); + LLVM_DEBUG(dbgs() << "Shrunk: " << *li << '\n'); return CanSeparate; } @@ -496,7 +497,7 @@ bool LiveIntervals::computeDeadValues(LiveInterval &LI, // This is a dead PHI. Remove it. VNI->markUnused(); LI.removeSegment(I); - DEBUG(dbgs() << "Dead PHI at " << Def << " may separate interval\n"); + LLVM_DEBUG(dbgs() << "Dead PHI at " << Def << " may separate interval\n"); MayHaveSplitComponents = true; } else { // This is a dead def. Make sure the instruction knows. @@ -504,7 +505,7 @@ bool LiveIntervals::computeDeadValues(LiveInterval &LI, assert(MI && "No instruction defining live value"); MI->addRegisterDead(LI.reg, TRI); if (dead && MI->allDefsAreDead()) { - DEBUG(dbgs() << "All defs dead: " << Def << '\t' << *MI); + LLVM_DEBUG(dbgs() << "All defs dead: " << Def << '\t' << *MI); dead->push_back(MI); } } @@ -513,7 +514,7 @@ bool LiveIntervals::computeDeadValues(LiveInterval &LI, } void LiveIntervals::shrinkToUses(LiveInterval::SubRange &SR, unsigned Reg) { - DEBUG(dbgs() << "Shrink: " << SR << '\n'); + LLVM_DEBUG(dbgs() << "Shrink: " << SR << '\n'); assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Can only shrink virtual registers"); // Find all the values used, including PHI kills. @@ -572,13 +573,14 @@ void LiveIntervals::shrinkToUses(LiveInterval::SubRange &SR, unsigned Reg) { continue; if (VNI->isPHIDef()) { // This is a dead PHI. Remove it. - DEBUG(dbgs() << "Dead PHI at " << VNI->def << " may separate interval\n"); + LLVM_DEBUG(dbgs() << "Dead PHI at " << VNI->def + << " may separate interval\n"); VNI->markUnused(); SR.removeSegment(*Segment); } } - DEBUG(dbgs() << "Shrunk: " << SR << '\n'); + LLVM_DEBUG(dbgs() << "Shrunk: " << SR << '\n'); } void LiveIntervals::extendToIndices(LiveRange &LR, @@ -943,7 +945,8 @@ public: /// Update all live ranges touched by MI, assuming a move from OldIdx to /// NewIdx. void updateAllRanges(MachineInstr *MI) { - DEBUG(dbgs() << "handleMove " << OldIdx << " -> " << NewIdx << ": " << *MI); + LLVM_DEBUG(dbgs() << "handleMove " << OldIdx << " -> " << NewIdx << ": " + << *MI); bool hasRegMask = false; for (MachineOperand &MO : MI->operands()) { if (MO.isRegMask()) @@ -993,7 +996,7 @@ private: void updateRange(LiveRange &LR, unsigned Reg, LaneBitmask LaneMask) { if (!Updated.insert(&LR).second) return; - DEBUG({ + LLVM_DEBUG({ dbgs() << " "; if (TargetRegisterInfo::isVirtualRegister(Reg)) { dbgs() << printReg(Reg); @@ -1008,7 +1011,7 @@ private: handleMoveDown(LR); else handleMoveUp(LR, Reg, LaneMask); - DEBUG(dbgs() << " -->\t" << LR << '\n'); + LLVM_DEBUG(dbgs() << " -->\t" << LR << '\n'); LR.verify(); } @@ -1611,7 +1614,7 @@ void LiveIntervals::splitSeparateComponents(LiveInterval &LI, unsigned NumComp = ConEQ.Classify(LI); if (NumComp <= 1) return; - DEBUG(dbgs() << " Split " << NumComp << " components: " << LI << '\n'); + LLVM_DEBUG(dbgs() << " Split " << NumComp << " components: " << LI << '\n'); unsigned Reg = LI.reg; const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); for (unsigned I = 1; I < NumComp; ++I) { diff --git a/llvm/lib/CodeGen/LiveRangeEdit.cpp b/llvm/lib/CodeGen/LiveRangeEdit.cpp index 22f6b3260f4..8dfe8b68c3a 100644 --- a/llvm/lib/CodeGen/LiveRangeEdit.cpp +++ b/llvm/lib/CodeGen/LiveRangeEdit.cpp @@ -220,8 +220,8 @@ bool LiveRangeEdit::foldAsLoad(LiveInterval *LI, if (!DefMI->isSafeToMove(nullptr, SawStore)) return false; - DEBUG(dbgs() << "Try to fold single def: " << *DefMI - << " into single use: " << *UseMI); + LLVM_DEBUG(dbgs() << "Try to fold single def: " << *DefMI + << " into single use: " << *UseMI); SmallVector<unsigned, 8> Ops; if (UseMI->readsWritesVirtualRegister(LI->reg, &Ops).second) @@ -230,7 +230,7 @@ bool LiveRangeEdit::foldAsLoad(LiveInterval *LI, MachineInstr *FoldMI = TII.foldMemoryOperand(*UseMI, Ops, *DefMI, &LIS); if (!FoldMI) return false; - DEBUG(dbgs() << " folded: " << *FoldMI); + LLVM_DEBUG(dbgs() << " folded: " << *FoldMI); LIS.ReplaceMachineInstrInMaps(*UseMI, *FoldMI); UseMI->eraseFromParent(); DefMI->addRegisterDead(LI->reg, nullptr); @@ -267,18 +267,18 @@ void LiveRangeEdit::eliminateDeadDef(MachineInstr *MI, ToShrinkSet &ToShrink, } // Never delete inline asm. if (MI->isInlineAsm()) { - DEBUG(dbgs() << "Won't delete: " << Idx << '\t' << *MI); + LLVM_DEBUG(dbgs() << "Won't delete: " << Idx << '\t' << *MI); return; } // Use the same criteria as DeadMachineInstructionElim. bool SawStore = false; if (!MI->isSafeToMove(nullptr, SawStore)) { - DEBUG(dbgs() << "Can't delete: " << Idx << '\t' << *MI); + LLVM_DEBUG(dbgs() << "Can't delete: " << Idx << '\t' << *MI); return; } - DEBUG(dbgs() << "Deleting dead def " << Idx << '\t' << *MI); + LLVM_DEBUG(dbgs() << "Deleting dead def " << Idx << '\t' << *MI); // Collect virtual registers to be erased after MI is gone. SmallVector<unsigned, 8> RegsToErase; @@ -352,7 +352,7 @@ void LiveRangeEdit::eliminateDeadDef(MachineInstr *MI, ToShrinkSet &ToShrink, continue; MI->RemoveOperand(i-1); } - DEBUG(dbgs() << "Converted physregs to:\t" << *MI); + LLVM_DEBUG(dbgs() << "Converted physregs to:\t" << *MI); } else { // If the dest of MI is an original reg and MI is reMaterializable, // don't delete the inst. Replace the dest with a new reg, and keep @@ -465,7 +465,7 @@ LiveRangeEdit::calculateRegClassAndHint(MachineFunction &MF, for (unsigned I = 0, Size = size(); I < Size; ++I) { LiveInterval &LI = LIS.getInterval(get(I)); if (MRI.recomputeRegClass(LI.reg)) - DEBUG({ + LLVM_DEBUG({ const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); dbgs() << "Inflated " << printReg(LI.reg) << " to " << TRI->getRegClassName(MRI.getRegClass(LI.reg)) << '\n'; diff --git a/llvm/lib/CodeGen/LiveRangeShrink.cpp b/llvm/lib/CodeGen/LiveRangeShrink.cpp index 1aa3bbd90a9..f75d513c89f 100644 --- a/llvm/lib/CodeGen/LiveRangeShrink.cpp +++ b/llvm/lib/CodeGen/LiveRangeShrink.cpp @@ -111,7 +111,7 @@ bool LiveRangeShrink::runOnMachineFunction(MachineFunction &MF) { MachineRegisterInfo &MRI = MF.getRegInfo(); - DEBUG(dbgs() << "**** Analysing " << MF.getName() << '\n'); + LLVM_DEBUG(dbgs() << "**** Analysing " << MF.getName() << '\n'); InstOrderMap IOM; // Map from register to instruction order (value of IOM) where the diff --git a/llvm/lib/CodeGen/LiveRegMatrix.cpp b/llvm/lib/CodeGen/LiveRegMatrix.cpp index d8faf75466c..e72977b0267 100644 --- a/llvm/lib/CodeGen/LiveRegMatrix.cpp +++ b/llvm/lib/CodeGen/LiveRegMatrix.cpp @@ -102,37 +102,37 @@ static bool foreachUnit(const TargetRegisterInfo *TRI, } void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { - DEBUG(dbgs() << "assigning " << printReg(VirtReg.reg, TRI) - << " to " << printReg(PhysReg, TRI) << ':'); + LLVM_DEBUG(dbgs() << "assigning " << printReg(VirtReg.reg, TRI) << " to " + << printReg(PhysReg, TRI) << ':'); assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment"); VRM->assignVirt2Phys(VirtReg.reg, PhysReg); - foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit, - const LiveRange &Range) { - DEBUG(dbgs() << ' ' << printRegUnit(Unit, TRI) << ' ' << Range); - Matrix[Unit].unify(VirtReg, Range); - return false; - }); + foreachUnit( + TRI, VirtReg, PhysReg, [&](unsigned Unit, const LiveRange &Range) { + LLVM_DEBUG(dbgs() << ' ' << printRegUnit(Unit, TRI) << ' ' << Range); + Matrix[Unit].unify(VirtReg, Range); + return false; + }); ++NumAssigned; - DEBUG(dbgs() << '\n'); + LLVM_DEBUG(dbgs() << '\n'); } void LiveRegMatrix::unassign(LiveInterval &VirtReg) { unsigned PhysReg = VRM->getPhys(VirtReg.reg); - DEBUG(dbgs() << "unassigning " << printReg(VirtReg.reg, TRI) - << " from " << printReg(PhysReg, TRI) << ':'); + LLVM_DEBUG(dbgs() << "unassigning " << printReg(VirtReg.reg, TRI) << " from " + << printReg(PhysReg, TRI) << ':'); VRM->clearVirt(VirtReg.reg); - foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit, - const LiveRange &Range) { - DEBUG(dbgs() << ' ' << printRegUnit(Unit, TRI)); - Matrix[Unit].extract(VirtReg, Range); - return false; - }); + foreachUnit(TRI, VirtReg, PhysReg, + [&](unsigned Unit, const LiveRange &Range) { + LLVM_DEBUG(dbgs() << ' ' << printRegUnit(Unit, TRI)); + Matrix[Unit].extract(VirtReg, Range); + return false; + }); ++NumUnassigned; - DEBUG(dbgs() << '\n'); + LLVM_DEBUG(dbgs() << '\n'); } bool LiveRegMatrix::isPhysRegUsed(unsigned PhysReg) const { diff --git a/llvm/lib/CodeGen/LocalStackSlotAllocation.cpp b/llvm/lib/CodeGen/LocalStackSlotAllocation.cpp index b2a0d21e023..1dbf11ee96e 100644 --- a/llvm/lib/CodeGen/LocalStackSlotAllocation.cpp +++ b/llvm/lib/CodeGen/LocalStackSlotAllocation.cpp @@ -164,8 +164,8 @@ void LocalStackSlotPass::AdjustStackOffset(MachineFrameInfo &MFI, Offset = (Offset + Align - 1) / Align * Align; int64_t LocalOffset = StackGrowsDown ? -Offset : Offset; - DEBUG(dbgs() << "Allocate FI(" << FrameIdx << ") to local offset " - << LocalOffset << "\n"); + LLVM_DEBUG(dbgs() << "Allocate FI(" << FrameIdx << ") to local offset " + << LocalOffset << "\n"); // Keep the offset available for base register allocation LocalOffsets[FrameIdx] = LocalOffset; // And tell MFI about it for PEI to use later @@ -351,7 +351,7 @@ bool LocalStackSlotPass::insertFrameReferenceRegisters(MachineFunction &Fn) { assert(MFI.isObjectPreAllocated(FrameIdx) && "Only pre-allocated locals expected!"); - DEBUG(dbgs() << "Considering: " << MI); + LLVM_DEBUG(dbgs() << "Considering: " << MI); unsigned idx = 0; for (unsigned f = MI.getNumOperands(); idx != f; ++idx) { @@ -367,7 +367,7 @@ bool LocalStackSlotPass::insertFrameReferenceRegisters(MachineFunction &Fn) { int64_t Offset = 0; int64_t FrameSizeAdjust = StackGrowsDown ? MFI.getLocalFrameSize() : 0; - DEBUG(dbgs() << " Replacing FI in: " << MI); + LLVM_DEBUG(dbgs() << " Replacing FI in: " << MI); // If we have a suitable base register available, use it; otherwise // create a new one. Note that any offset encoded in the @@ -377,7 +377,7 @@ bool LocalStackSlotPass::insertFrameReferenceRegisters(MachineFunction &Fn) { if (UsedBaseReg && lookupCandidateBaseReg(BaseReg, BaseOffset, FrameSizeAdjust, LocalOffset, MI, TRI)) { - DEBUG(dbgs() << " Reusing base register " << BaseReg << "\n"); + LLVM_DEBUG(dbgs() << " Reusing base register " << BaseReg << "\n"); // We found a register to reuse. Offset = FrameSizeAdjust + LocalOffset - BaseOffset; } else { @@ -405,8 +405,9 @@ bool LocalStackSlotPass::insertFrameReferenceRegisters(MachineFunction &Fn) { const TargetRegisterClass *RC = TRI->getPointerRegClass(*MF); BaseReg = Fn.getRegInfo().createVirtualRegister(RC); - DEBUG(dbgs() << " Materializing base register " << BaseReg << - " at frame local offset " << LocalOffset + InstrOffset << "\n"); + LLVM_DEBUG(dbgs() << " Materializing base register " << BaseReg + << " at frame local offset " + << LocalOffset + InstrOffset << "\n"); // Tell the target to insert the instruction to initialize // the base register. @@ -427,7 +428,7 @@ bool LocalStackSlotPass::insertFrameReferenceRegisters(MachineFunction &Fn) { // Modify the instruction to use the new base register rather // than the frame index operand. TRI->resolveFrameIndex(MI, BaseReg, Offset); - DEBUG(dbgs() << "Resolved: " << MI); + LLVM_DEBUG(dbgs() << "Resolved: " << MI); ++NumReplacements; } diff --git a/llvm/lib/CodeGen/MIRCanonicalizerPass.cpp b/llvm/lib/CodeGen/MIRCanonicalizerPass.cpp index a04e9942131..8f02423d88a 100644 --- a/llvm/lib/CodeGen/MIRCanonicalizerPass.cpp +++ b/llvm/lib/CodeGen/MIRCanonicalizerPass.cpp @@ -141,7 +141,7 @@ rescheduleLexographically(std::vector<MachineInstr *> instructions, for (auto &II : StringInstrMap) { - DEBUG({ + LLVM_DEBUG({ dbgs() << "Splicing "; II.second->dump(); dbgs() << " right before: "; @@ -233,7 +233,7 @@ static bool rescheduleCanonically(unsigned &PseudoIdempotentInstCount, continue; } - DEBUG(dbgs() << "Operand " << 0 << " of "; II->dump(); MO.dump();); + LLVM_DEBUG(dbgs() << "Operand " << 0 << " of "; II->dump(); MO.dump();); MachineInstr *Def = II; unsigned Distance = ~0U; @@ -280,7 +280,7 @@ static bool rescheduleCanonically(unsigned &PseudoIdempotentInstCount, if (DefI == BBE || UseI == BBE) continue; - DEBUG({ + LLVM_DEBUG({ dbgs() << "Splicing "; DefI->dump(); dbgs() << " right before: "; @@ -302,13 +302,15 @@ static bool rescheduleCanonically(unsigned &PseudoIdempotentInstCount, if (UseI == MBB->instr_end()) continue; - DEBUG(dbgs() << "Rescheduling Multi-Use Instructions Lexographically.";); + LLVM_DEBUG( + dbgs() << "Rescheduling Multi-Use Instructions Lexographically.";); Changed |= rescheduleLexographically( E.second, MBB, [&]() -> MachineBasicBlock::iterator { return UseI; }); } PseudoIdempotentInstCount = PseudoIdempotentInstructions.size(); - DEBUG(dbgs() << "Rescheduling Idempotent Instructions Lexographically.";); + LLVM_DEBUG( + dbgs() << "Rescheduling Idempotent Instructions Lexographically.";); Changed |= rescheduleLexographically( PseudoIdempotentInstructions, MBB, [&]() -> MachineBasicBlock::iterator { return MBB->begin(); }); @@ -384,7 +386,7 @@ static std::vector<MachineInstr *> populateCandidates(MachineBasicBlock *MBB) { if (!MI->mayStore() && !MI->isBranch() && !DoesMISideEffect) continue; - DEBUG(dbgs() << "Found Candidate: "; MI->dump();); + LLVM_DEBUG(dbgs() << "Found Candidate: "; MI->dump();); Candidates.push_back(MI); } @@ -405,7 +407,7 @@ static void doCandidateWalk(std::vector<TypedVReg> &VRegs, RegQueue.pop(); if (TReg.isFrameIndex()) { - DEBUG(dbgs() << "Popping frame index.\n";); + LLVM_DEBUG(dbgs() << "Popping frame index.\n";); VRegs.push_back(TypedVReg(RSE_FrameIndex)); continue; } @@ -414,7 +416,7 @@ static void doCandidateWalk(std::vector<TypedVReg> &VRegs, unsigned Reg = TReg.getReg(); if (TargetRegisterInfo::isVirtualRegister(Reg)) { - DEBUG({ + LLVM_DEBUG({ dbgs() << "Popping vreg "; MRI.def_begin(Reg)->dump(); dbgs() << "\n"; @@ -426,7 +428,7 @@ static void doCandidateWalk(std::vector<TypedVReg> &VRegs, VRegs.push_back(TypedVReg(Reg)); } } else { - DEBUG(dbgs() << "Popping physreg.\n";); + LLVM_DEBUG(dbgs() << "Popping physreg.\n";); VRegs.push_back(TypedVReg(Reg)); continue; } @@ -442,7 +444,7 @@ static void doCandidateWalk(std::vector<TypedVReg> &VRegs, break; } - DEBUG({ + LLVM_DEBUG({ dbgs() << "\n========================\n"; dbgs() << "Visited MI: "; Def->dump(); @@ -454,7 +456,7 @@ static void doCandidateWalk(std::vector<TypedVReg> &VRegs, MachineOperand &MO = Def->getOperand(I); if (MO.isFI()) { - DEBUG(dbgs() << "Pushing frame index.\n";); + LLVM_DEBUG(dbgs() << "Pushing frame index.\n";); RegQueue.push(TypedVReg(RSE_FrameIndex)); } @@ -526,7 +528,7 @@ GetVRegRenameMap(const std::vector<TypedVReg> &VRegs, // from a copy from a frame index. So it's safe to skip by one. unsigned LastRenameReg = NVC.incrementVirtualVReg(); (void)LastRenameReg; - DEBUG(dbgs() << "Skipping rename for FI " << LastRenameReg << "\n";); + LLVM_DEBUG(dbgs() << "Skipping rename for FI " << LastRenameReg << "\n";); continue; } else if (vreg.isCandidate()) { @@ -543,7 +545,7 @@ GetVRegRenameMap(const std::vector<TypedVReg> &VRegs, } else if (!TargetRegisterInfo::isVirtualRegister(vreg.getReg())) { unsigned LastRenameReg = NVC.incrementVirtualVReg(); (void)LastRenameReg; - DEBUG({ + LLVM_DEBUG({ dbgs() << "Skipping rename for Phys Reg " << LastRenameReg << "\n"; }); continue; @@ -551,26 +553,27 @@ GetVRegRenameMap(const std::vector<TypedVReg> &VRegs, auto Reg = vreg.getReg(); if (llvm::find(renamedInOtherBB, Reg) != renamedInOtherBB.end()) { - DEBUG(dbgs() << "Vreg " << Reg << " already renamed in other BB.\n";); + LLVM_DEBUG(dbgs() << "Vreg " << Reg + << " already renamed in other BB.\n";); continue; } auto Rename = NVC.createVirtualRegister(MRI.getRegClass(Reg)); if (VRegRenameMap.find(Reg) == VRegRenameMap.end()) { - DEBUG(dbgs() << "Mapping vreg ";); + LLVM_DEBUG(dbgs() << "Mapping vreg ";); if (MRI.reg_begin(Reg) != MRI.reg_end()) { - DEBUG(auto foo = &*MRI.reg_begin(Reg); foo->dump();); + LLVM_DEBUG(auto foo = &*MRI.reg_begin(Reg); foo->dump();); } else { - DEBUG(dbgs() << Reg;); + LLVM_DEBUG(dbgs() << Reg;); } - DEBUG(dbgs() << " to ";); + LLVM_DEBUG(dbgs() << " to ";); if (MRI.reg_begin(Rename) != MRI.reg_end()) { - DEBUG(auto foo = &*MRI.reg_begin(Rename); foo->dump();); + LLVM_DEBUG(auto foo = &*MRI.reg_begin(Rename); foo->dump();); } else { - DEBUG(dbgs() << Rename;); + LLVM_DEBUG(dbgs() << Rename;); } - DEBUG(dbgs() << "\n";); + LLVM_DEBUG(dbgs() << "\n";); VRegRenameMap.insert(std::pair<unsigned, unsigned>(Reg, Rename)); } @@ -638,18 +641,19 @@ static bool runOnBasicBlock(MachineBasicBlock *MBB, if (CanonicalizeBasicBlockNumber != ~0U) { if (CanonicalizeBasicBlockNumber != basicBlockNum++) return false; - DEBUG(dbgs() << "\n Canonicalizing BasicBlock " << MBB->getName() << "\n";); + LLVM_DEBUG(dbgs() << "\n Canonicalizing BasicBlock " << MBB->getName() + << "\n";); } if (llvm::find(bbNames, MBB->getName()) != bbNames.end()) { - DEBUG({ + LLVM_DEBUG({ dbgs() << "Found potentially duplicate BasicBlocks: " << MBB->getName() << "\n"; }); return false; } - DEBUG({ + LLVM_DEBUG({ dbgs() << "\n\n NEW BASIC BLOCK: " << MBB->getName() << " \n\n"; dbgs() << "\n\n================================================\n\n"; }); @@ -659,16 +663,17 @@ static bool runOnBasicBlock(MachineBasicBlock *MBB, MachineRegisterInfo &MRI = MF.getRegInfo(); bbNames.push_back(MBB->getName()); - DEBUG(dbgs() << "\n\n NEW BASIC BLOCK: " << MBB->getName() << "\n\n";); + LLVM_DEBUG(dbgs() << "\n\n NEW BASIC BLOCK: " << MBB->getName() << "\n\n";); - DEBUG(dbgs() << "MBB Before Canonical Copy Propagation:\n"; MBB->dump();); + LLVM_DEBUG(dbgs() << "MBB Before Canonical Copy Propagation:\n"; + MBB->dump();); Changed |= propagateLocalCopies(MBB); - DEBUG(dbgs() << "MBB After Canonical Copy Propagation:\n"; MBB->dump();); + LLVM_DEBUG(dbgs() << "MBB After Canonical Copy Propagation:\n"; MBB->dump();); - DEBUG(dbgs() << "MBB Before Scheduling:\n"; MBB->dump();); + LLVM_DEBUG(dbgs() << "MBB Before Scheduling:\n"; MBB->dump();); unsigned IdempotentInstCount = 0; Changed |= rescheduleCanonically(IdempotentInstCount, MBB); - DEBUG(dbgs() << "MBB After Scheduling:\n"; MBB->dump();); + LLVM_DEBUG(dbgs() << "MBB After Scheduling:\n"; MBB->dump();); std::vector<MachineInstr *> Candidates = populateCandidates(MBB); std::vector<MachineInstr *> VisitedMIs; @@ -693,7 +698,7 @@ static bool runOnBasicBlock(MachineBasicBlock *MBB, if (!(MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))) continue; - DEBUG(dbgs() << "Enqueue register"; MO.dump(); dbgs() << "\n";); + LLVM_DEBUG(dbgs() << "Enqueue register"; MO.dump(); dbgs() << "\n";); RegQueue.push(TypedVReg(MO.getReg())); } @@ -710,7 +715,7 @@ static bool runOnBasicBlock(MachineBasicBlock *MBB, if (!MO.isReg() && !MO.isFI()) continue; - DEBUG(dbgs() << "Enqueue Reg/FI"; MO.dump(); dbgs() << "\n";); + LLVM_DEBUG(dbgs() << "Enqueue Reg/FI"; MO.dump(); dbgs() << "\n";); RegQueue.push(MO.isReg() ? TypedVReg(MO.getReg()) : TypedVReg(RSE_FrameIndex)); @@ -752,8 +757,10 @@ static bool runOnBasicBlock(MachineBasicBlock *MBB, Changed |= doDefKillClear(MBB); - DEBUG(dbgs() << "Updated MachineBasicBlock:\n"; MBB->dump(); dbgs() << "\n";); - DEBUG(dbgs() << "\n\n================================================\n\n"); + LLVM_DEBUG(dbgs() << "Updated MachineBasicBlock:\n"; MBB->dump(); + dbgs() << "\n";); + LLVM_DEBUG( + dbgs() << "\n\n================================================\n\n"); return Changed; } @@ -763,19 +770,21 @@ bool MIRCanonicalizer::runOnMachineFunction(MachineFunction &MF) { if (CanonicalizeFunctionNumber != ~0U) { if (CanonicalizeFunctionNumber != functionNum++) return false; - DEBUG(dbgs() << "\n Canonicalizing Function " << MF.getName() << "\n";); + LLVM_DEBUG(dbgs() << "\n Canonicalizing Function " << MF.getName() + << "\n";); } // we need a valid vreg to create a vreg type for skipping all those // stray vreg numbers so reach alignment/canonical vreg values. std::vector<MachineBasicBlock *> RPOList = GetRPOList(MF); - DEBUG(dbgs() << "\n\n NEW MACHINE FUNCTION: " << MF.getName() << " \n\n"; - dbgs() << "\n\n================================================\n\n"; - dbgs() << "Total Basic Blocks: " << RPOList.size() << "\n"; - for (auto MBB - : RPOList) { dbgs() << MBB->getName() << "\n"; } dbgs() - << "\n\n================================================\n\n";); + LLVM_DEBUG( + dbgs() << "\n\n NEW MACHINE FUNCTION: " << MF.getName() << " \n\n"; + dbgs() << "\n\n================================================\n\n"; + dbgs() << "Total Basic Blocks: " << RPOList.size() << "\n"; + for (auto MBB + : RPOList) { dbgs() << MBB->getName() << "\n"; } dbgs() + << "\n\n================================================\n\n";); std::vector<StringRef> BBNames; std::vector<unsigned> RenamedInOtherBB; diff --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp index 319174de2d8..64cc2e669ad 100644 --- a/llvm/lib/CodeGen/MachineBasicBlock.cpp +++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp @@ -855,9 +855,9 @@ MachineBasicBlock *MachineBasicBlock::SplitCriticalEdge(MachineBasicBlock *Succ, MachineBasicBlock *NMBB = MF->CreateMachineBasicBlock(); MF->insert(std::next(MachineFunction::iterator(this)), NMBB); - DEBUG(dbgs() << "Splitting critical edge: " << printMBBReference(*this) - << " -- " << printMBBReference(*NMBB) << " -- " - << printMBBReference(*Succ) << '\n'); + LLVM_DEBUG(dbgs() << "Splitting critical edge: " << printMBBReference(*this) + << " -- " << printMBBReference(*NMBB) << " -- " + << printMBBReference(*Succ) << '\n'); LiveIntervals *LIS = P.getAnalysisIfAvailable<LiveIntervals>(); SlotIndexes *Indexes = P.getAnalysisIfAvailable<SlotIndexes>(); @@ -886,7 +886,7 @@ MachineBasicBlock *MachineBasicBlock::SplitCriticalEdge(MachineBasicBlock *Succ, if (TargetRegisterInfo::isPhysicalRegister(Reg) || LV->getVarInfo(Reg).removeKill(*MI)) { KilledRegs.push_back(Reg); - DEBUG(dbgs() << "Removing terminator kill: " << *MI); + LLVM_DEBUG(dbgs() << "Removing terminator kill: " << *MI); OI->setIsKill(false); } } @@ -977,7 +977,7 @@ MachineBasicBlock *MachineBasicBlock::SplitCriticalEdge(MachineBasicBlock *Succ, continue; if (TargetRegisterInfo::isVirtualRegister(Reg)) LV->getVarInfo(Reg).Kills.push_back(&*I); - DEBUG(dbgs() << "Restored terminator kill: " << *I); + LLVM_DEBUG(dbgs() << "Restored terminator kill: " << *I); break; } } @@ -1110,8 +1110,8 @@ bool MachineBasicBlock::canSplitCriticalEdge( // case that we can't handle. Since this never happens in properly optimized // code, just skip those edges. if (TBB && TBB == FBB) { - DEBUG(dbgs() << "Won't split critical edge after degenerate " - << printMBBReference(*this) << '\n'); + LLVM_DEBUG(dbgs() << "Won't split critical edge after degenerate " + << printMBBReference(*this) << '\n'); return false; } return true; diff --git a/llvm/lib/CodeGen/MachineBlockPlacement.cpp b/llvm/lib/CodeGen/MachineBlockPlacement.cpp index ec43097c23b..7ca19945b8f 100644 --- a/llvm/lib/CodeGen/MachineBlockPlacement.cpp +++ b/llvm/lib/CodeGen/MachineBlockPlacement.cpp @@ -643,7 +643,8 @@ BranchProbability MachineBlockPlacement::collectViableSuccessors( if (SuccChain == &Chain) { SkipSucc = true; } else if (Succ != *SuccChain->begin()) { - DEBUG(dbgs() << " " << getBlockName(Succ) << " -> Mid chain!\n"); + LLVM_DEBUG(dbgs() << " " << getBlockName(Succ) + << " -> Mid chain!\n"); continue; } } @@ -1010,7 +1011,7 @@ MachineBlockPlacement::getBestTrellisSuccessor( // If we have a trellis, and BB doesn't have the best fallthrough edges, // we shouldn't choose any successor. We've already looked and there's a // better fallthrough edge for all the successors. - DEBUG(dbgs() << "Trellis, but not one of the chosen edges.\n"); + LLVM_DEBUG(dbgs() << "Trellis, but not one of the chosen edges.\n"); return Result; } @@ -1027,10 +1028,11 @@ MachineBlockPlacement::getBestTrellisSuccessor( canTailDuplicateUnplacedPreds(BB, Succ2, Chain, BlockFilter) && isProfitableToTailDup(BB, Succ2, MBPI->getEdgeProbability(BB, Succ1), Chain, BlockFilter)) { - DEBUG(BranchProbability Succ2Prob = getAdjustedProbability( - MBPI->getEdgeProbability(BB, Succ2), AdjustedSumProb); - dbgs() << " Selected: " << getBlockName(Succ2) - << ", probability: " << Succ2Prob << " (Tail Duplicate)\n"); + LLVM_DEBUG(BranchProbability Succ2Prob = getAdjustedProbability( + MBPI->getEdgeProbability(BB, Succ2), AdjustedSumProb); + dbgs() << " Selected: " << getBlockName(Succ2) + << ", probability: " << Succ2Prob + << " (Tail Duplicate)\n"); Result.BB = Succ2; Result.ShouldTailDup = true; return Result; @@ -1041,10 +1043,10 @@ MachineBlockPlacement::getBestTrellisSuccessor( ComputedEdges[BestB.Src] = { BestB.Dest, false }; auto TrellisSucc = BestA.Dest; - DEBUG(BranchProbability SuccProb = getAdjustedProbability( - MBPI->getEdgeProbability(BB, TrellisSucc), AdjustedSumProb); - dbgs() << " Selected: " << getBlockName(TrellisSucc) - << ", probability: " << SuccProb << " (Trellis)\n"); + LLVM_DEBUG(BranchProbability SuccProb = getAdjustedProbability( + MBPI->getEdgeProbability(BB, TrellisSucc), AdjustedSumProb); + dbgs() << " Selected: " << getBlockName(TrellisSucc) + << ", probability: " << SuccProb << " (Trellis)\n"); Result.BB = TrellisSucc; return Result; } @@ -1150,7 +1152,7 @@ void MachineBlockPlacement::precomputeTriangleChains() { if (TriangleChainCount == 0) return; - DEBUG(dbgs() << "Pre-computing triangle chains.\n"); + LLVM_DEBUG(dbgs() << "Pre-computing triangle chains.\n"); // Map from last block to the chain that contains it. This allows us to extend // chains as we find new triangles. DenseMap<const MachineBasicBlock *, TriangleChain> TriangleChainMap; @@ -1224,8 +1226,9 @@ void MachineBlockPlacement::precomputeTriangleChains() { MachineBasicBlock *dst = Chain.Edges.back(); Chain.Edges.pop_back(); for (MachineBasicBlock *src : reverse(Chain.Edges)) { - DEBUG(dbgs() << "Marking edge: " << getBlockName(src) << "->" << - getBlockName(dst) << " as pre-computed based on triangles.\n"); + LLVM_DEBUG(dbgs() << "Marking edge: " << getBlockName(src) << "->" + << getBlockName(dst) + << " as pre-computed based on triangles.\n"); auto InsertResult = ComputedEdges.insert({src, {dst, true}}); assert(InsertResult.second && "Block seen twice."); @@ -1431,8 +1434,8 @@ bool MachineBlockPlacement::hasBetterLayoutPredecessor( } if (BadCFGConflict) { - DEBUG(dbgs() << " Not a candidate: " << getBlockName(Succ) << " -> " << SuccProb - << " (prob) (non-cold CFG conflict)\n"); + LLVM_DEBUG(dbgs() << " Not a candidate: " << getBlockName(Succ) << " -> " + << SuccProb << " (prob) (non-cold CFG conflict)\n"); return true; } @@ -1462,7 +1465,8 @@ MachineBlockPlacement::selectBestSuccessor( auto AdjustedSumProb = collectViableSuccessors(BB, Chain, BlockFilter, Successors); - DEBUG(dbgs() << "Selecting best successor for: " << getBlockName(BB) << "\n"); + LLVM_DEBUG(dbgs() << "Selecting best successor for: " << getBlockName(BB) + << "\n"); // if we already precomputed the best successor for BB, return that if still // applicable. @@ -1503,18 +1507,18 @@ MachineBlockPlacement::selectBestSuccessor( continue; } - DEBUG( - dbgs() << " Candidate: " << getBlockName(Succ) << ", probability: " - << SuccProb + LLVM_DEBUG( + dbgs() << " Candidate: " << getBlockName(Succ) + << ", probability: " << SuccProb << (SuccChain.UnscheduledPredecessors != 0 ? " (CFG break)" : "") << "\n"); if (BestSucc.BB && BestProb >= SuccProb) { - DEBUG(dbgs() << " Not the best candidate, continuing\n"); + LLVM_DEBUG(dbgs() << " Not the best candidate, continuing\n"); continue; } - DEBUG(dbgs() << " Setting it as best candidate\n"); + LLVM_DEBUG(dbgs() << " Setting it as best candidate\n"); BestSucc.BB = Succ; BestProb = SuccProb; } @@ -1539,10 +1543,9 @@ MachineBlockPlacement::selectBestSuccessor( break; if (canTailDuplicateUnplacedPreds(BB, Succ, Chain, BlockFilter) && (isProfitableToTailDup(BB, Succ, BestProb, Chain, BlockFilter))) { - DEBUG( - dbgs() << " Candidate: " << getBlockName(Succ) << ", probability: " - << DupProb - << " (Tail Duplicate)\n"); + LLVM_DEBUG(dbgs() << " Candidate: " << getBlockName(Succ) + << ", probability: " << DupProb + << " (Tail Duplicate)\n"); BestSucc.BB = Succ; BestSucc.ShouldTailDup = true; break; @@ -1550,7 +1553,7 @@ MachineBlockPlacement::selectBestSuccessor( } if (BestSucc.BB) - DEBUG(dbgs() << " Selected: " << getBlockName(BestSucc.BB) << "\n"); + LLVM_DEBUG(dbgs() << " Selected: " << getBlockName(BestSucc.BB) << "\n"); return BestSucc; } @@ -1596,8 +1599,8 @@ MachineBasicBlock *MachineBlockPlacement::selectBestCandidateBlock( "Found CFG-violating block"); BlockFrequency CandidateFreq = MBFI->getBlockFreq(MBB); - DEBUG(dbgs() << " " << getBlockName(MBB) << " -> "; - MBFI->printBlockFreq(dbgs(), CandidateFreq) << " (freq)\n"); + LLVM_DEBUG(dbgs() << " " << getBlockName(MBB) << " -> "; + MBFI->printBlockFreq(dbgs(), CandidateFreq) << " (freq)\n"); // For ehpad, we layout the least probable first as to avoid jumping back // from least probable landingpads to more probable ones. @@ -1723,8 +1726,8 @@ void MachineBlockPlacement::buildChain( if (!BestSucc) break; - DEBUG(dbgs() << "Unnatural loop CFG detected, forcibly merging the " - "layout successor until the CFG reduces\n"); + LLVM_DEBUG(dbgs() << "Unnatural loop CFG detected, forcibly merging the " + "layout successor until the CFG reduces\n"); } // Placement may have changed tail duplication opportunities. @@ -1743,15 +1746,15 @@ void MachineBlockPlacement::buildChain( // Zero out UnscheduledPredecessors for the successor we're about to merge in case // we selected a successor that didn't fit naturally into the CFG. SuccChain.UnscheduledPredecessors = 0; - DEBUG(dbgs() << "Merging from " << getBlockName(BB) << " to " - << getBlockName(BestSucc) << "\n"); + LLVM_DEBUG(dbgs() << "Merging from " << getBlockName(BB) << " to " + << getBlockName(BestSucc) << "\n"); markChainSuccessors(SuccChain, LoopHeaderBB, BlockFilter); Chain.merge(BestSucc, &SuccChain); BB = *std::prev(Chain.end()); } - DEBUG(dbgs() << "Finished forming chain for header block " - << getBlockName(*Chain.begin()) << "\n"); + LLVM_DEBUG(dbgs() << "Finished forming chain for header block " + << getBlockName(*Chain.begin()) << "\n"); } /// Find the best loop top block for layout. @@ -1784,17 +1787,17 @@ MachineBlockPlacement::findBestLoopTop(const MachineLoop &L, if (!LoopBlockSet.count(*HeaderChain.begin())) return L.getHeader(); - DEBUG(dbgs() << "Finding best loop top for: " << getBlockName(L.getHeader()) - << "\n"); + LLVM_DEBUG(dbgs() << "Finding best loop top for: " + << getBlockName(L.getHeader()) << "\n"); BlockFrequency BestPredFreq; MachineBasicBlock *BestPred = nullptr; for (MachineBasicBlock *Pred : L.getHeader()->predecessors()) { if (!LoopBlockSet.count(Pred)) continue; - DEBUG(dbgs() << " header pred: " << getBlockName(Pred) << ", has " - << Pred->succ_size() << " successors, "; - MBFI->printBlockFreq(dbgs(), Pred) << " freq\n"); + LLVM_DEBUG(dbgs() << " header pred: " << getBlockName(Pred) << ", has " + << Pred->succ_size() << " successors, "; + MBFI->printBlockFreq(dbgs(), Pred) << " freq\n"); if (Pred->succ_size() > 1) continue; @@ -1809,7 +1812,7 @@ MachineBlockPlacement::findBestLoopTop(const MachineLoop &L, // If no direct predecessor is fine, just use the loop header. if (!BestPred) { - DEBUG(dbgs() << " final top unchanged\n"); + LLVM_DEBUG(dbgs() << " final top unchanged\n"); return L.getHeader(); } @@ -1819,7 +1822,7 @@ MachineBlockPlacement::findBestLoopTop(const MachineLoop &L, *BestPred->pred_begin() != L.getHeader()) BestPred = *BestPred->pred_begin(); - DEBUG(dbgs() << " final top: " << getBlockName(BestPred) << "\n"); + LLVM_DEBUG(dbgs() << " final top: " << getBlockName(BestPred) << "\n"); return BestPred; } @@ -1851,8 +1854,8 @@ MachineBlockPlacement::findBestLoopExit(const MachineLoop &L, // blocks where rotating to exit with that block will reach an outer loop. SmallPtrSet<MachineBasicBlock *, 4> BlocksExitingToOuterLoop; - DEBUG(dbgs() << "Finding best loop exit for: " << getBlockName(L.getHeader()) - << "\n"); + LLVM_DEBUG(dbgs() << "Finding best loop exit for: " + << getBlockName(L.getHeader()) << "\n"); for (MachineBasicBlock *MBB : L.getBlocks()) { BlockChain &Chain = *BlockToChain[MBB]; // Ensure that this block is at the end of a chain; otherwise it could be @@ -1875,15 +1878,15 @@ MachineBlockPlacement::findBestLoopExit(const MachineLoop &L, BlockChain &SuccChain = *BlockToChain[Succ]; // Don't split chains, either this chain or the successor's chain. if (&Chain == &SuccChain) { - DEBUG(dbgs() << " exiting: " << getBlockName(MBB) << " -> " - << getBlockName(Succ) << " (chain conflict)\n"); + LLVM_DEBUG(dbgs() << " exiting: " << getBlockName(MBB) << " -> " + << getBlockName(Succ) << " (chain conflict)\n"); continue; } auto SuccProb = MBPI->getEdgeProbability(MBB, Succ); if (LoopBlockSet.count(Succ)) { - DEBUG(dbgs() << " looping: " << getBlockName(MBB) << " -> " - << getBlockName(Succ) << " (" << SuccProb << ")\n"); + LLVM_DEBUG(dbgs() << " looping: " << getBlockName(MBB) << " -> " + << getBlockName(Succ) << " (" << SuccProb << ")\n"); HasLoopingSucc = true; continue; } @@ -1896,9 +1899,10 @@ MachineBlockPlacement::findBestLoopExit(const MachineLoop &L, } BlockFrequency ExitEdgeFreq = MBFI->getBlockFreq(MBB) * SuccProb; - DEBUG(dbgs() << " exiting: " << getBlockName(MBB) << " -> " - << getBlockName(Succ) << " [L:" << SuccLoopDepth << "] ("; - MBFI->printBlockFreq(dbgs(), ExitEdgeFreq) << ")\n"); + LLVM_DEBUG(dbgs() << " exiting: " << getBlockName(MBB) << " -> " + << getBlockName(Succ) << " [L:" << SuccLoopDepth + << "] ("; + MBFI->printBlockFreq(dbgs(), ExitEdgeFreq) << ")\n"); // Note that we bias this toward an existing layout successor to retain // incoming order in the absence of better information. The exit must have // a frequency higher than the current exit before we consider breaking @@ -1922,11 +1926,12 @@ MachineBlockPlacement::findBestLoopExit(const MachineLoop &L, // Without a candidate exiting block or with only a single block in the // loop, just use the loop header to layout the loop. if (!ExitingBB) { - DEBUG(dbgs() << " No other candidate exit blocks, using loop header\n"); + LLVM_DEBUG( + dbgs() << " No other candidate exit blocks, using loop header\n"); return nullptr; } if (L.getNumBlocks() == 1) { - DEBUG(dbgs() << " Loop has 1 block, using loop header as exit\n"); + LLVM_DEBUG(dbgs() << " Loop has 1 block, using loop header as exit\n"); return nullptr; } @@ -1937,7 +1942,8 @@ MachineBlockPlacement::findBestLoopExit(const MachineLoop &L, !BlocksExitingToOuterLoop.count(ExitingBB)) return nullptr; - DEBUG(dbgs() << " Best exiting block: " << getBlockName(ExitingBB) << "\n"); + LLVM_DEBUG(dbgs() << " Best exiting block: " << getBlockName(ExitingBB) + << "\n"); return ExitingBB; } @@ -2014,8 +2020,8 @@ void MachineBlockPlacement::rotateLoop(BlockChain &LoopChain, return; } - DEBUG(dbgs() << "Rotating loop to put exit " << getBlockName(ExitingBB) - << " at bottom\n"); + LLVM_DEBUG(dbgs() << "Rotating loop to put exit " << getBlockName(ExitingBB) + << " at bottom\n"); std::rotate(LoopChain.begin(), std::next(ExitIt), LoopChain.end()); } @@ -2150,8 +2156,9 @@ void MachineBlockPlacement::rotateLoopWithProfile( } } - DEBUG(dbgs() << "The cost of loop rotation by making " << getBlockName(*Iter) - << " to the top: " << Cost.getFrequency() << "\n"); + LLVM_DEBUG(dbgs() << "The cost of loop rotation by making " + << getBlockName(*Iter) + << " to the top: " << Cost.getFrequency() << "\n"); if (Cost < SmallestRotationCost) { SmallestRotationCost = Cost; @@ -2160,8 +2167,8 @@ void MachineBlockPlacement::rotateLoopWithProfile( } if (RotationPos != LoopChain.end()) { - DEBUG(dbgs() << "Rotate loop by making " << getBlockName(*RotationPos) - << " to the top\n"); + LLVM_DEBUG(dbgs() << "Rotate loop by making " << getBlockName(*RotationPos) + << " to the top\n"); std::rotate(LoopChain.begin(), RotationPos, LoopChain.end()); } } @@ -2265,7 +2272,7 @@ void MachineBlockPlacement::buildLoopChains(const MachineLoop &L) { else rotateLoop(LoopChain, PreferredLoopExit, LoopBlockSet); - DEBUG({ + LLVM_DEBUG({ // Crash at the end so we get all of the debugging output first. bool BadLoop = false; if (LoopChain.UnscheduledPredecessors) { @@ -2324,9 +2331,9 @@ void MachineBlockPlacement::buildCFGChains() { // Ensure that the layout successor is a viable block, as we know that // fallthrough is a possibility. assert(NextFI != FE && "Can't fallthrough past the last block."); - DEBUG(dbgs() << "Pre-merging due to unanalyzable fallthrough: " - << getBlockName(BB) << " -> " << getBlockName(NextBB) - << "\n"); + LLVM_DEBUG(dbgs() << "Pre-merging due to unanalyzable fallthrough: " + << getBlockName(BB) << " -> " << getBlockName(NextBB) + << "\n"); Chain->merge(NextBB, nullptr); #ifndef NDEBUG BlocksWithUnanalyzableExits.insert(&*BB); @@ -2356,7 +2363,7 @@ void MachineBlockPlacement::buildCFGChains() { #ifndef NDEBUG using FunctionBlockSetType = SmallPtrSet<MachineBasicBlock *, 16>; #endif - DEBUG({ + LLVM_DEBUG({ // Crash at the end so we get all of the debugging output first. bool BadFunc = false; FunctionBlockSetType FunctionBlockSet; @@ -2381,11 +2388,11 @@ void MachineBlockPlacement::buildCFGChains() { // Splice the blocks into place. MachineFunction::iterator InsertPos = F->begin(); - DEBUG(dbgs() << "[MBP] Function: "<< F->getName() << "\n"); + LLVM_DEBUG(dbgs() << "[MBP] Function: " << F->getName() << "\n"); for (MachineBasicBlock *ChainBB : FunctionChain) { - DEBUG(dbgs() << (ChainBB == *FunctionChain.begin() ? "Placing chain " - : " ... ") - << getBlockName(ChainBB) << "\n"); + LLVM_DEBUG(dbgs() << (ChainBB == *FunctionChain.begin() ? "Placing chain " + : " ... ") + << getBlockName(ChainBB) << "\n"); if (InsertPos != MachineFunction::iterator(ChainBB)) F->splice(InsertPos, ChainBB); else @@ -2470,11 +2477,11 @@ void MachineBlockPlacement::optimizeBranches() { MBPI->getEdgeProbability(ChainBB, FBB) > MBPI->getEdgeProbability(ChainBB, TBB) && !TII->reverseBranchCondition(Cond)) { - DEBUG(dbgs() << "Reverse order of the two branches: " - << getBlockName(ChainBB) << "\n"); - DEBUG(dbgs() << " Edge probability: " - << MBPI->getEdgeProbability(ChainBB, FBB) << " vs " - << MBPI->getEdgeProbability(ChainBB, TBB) << "\n"); + LLVM_DEBUG(dbgs() << "Reverse order of the two branches: " + << getBlockName(ChainBB) << "\n"); + LLVM_DEBUG(dbgs() << " Edge probability: " + << MBPI->getEdgeProbability(ChainBB, FBB) << " vs " + << MBPI->getEdgeProbability(ChainBB, TBB) << "\n"); DebugLoc dl; // FIXME: this is nowhere TII->removeBranch(*ChainBB); TII->insertBranch(*ChainBB, FBB, TBB, Cond, dl); @@ -2638,8 +2645,8 @@ bool MachineBlockPlacement::maybeTailDuplicateBlock( if (!shouldTailDuplicate(BB)) return false; - DEBUG(dbgs() << "Redoing tail duplication for Succ#" - << BB->getNumber() << "\n"); + LLVM_DEBUG(dbgs() << "Redoing tail duplication for Succ#" << BB->getNumber() + << "\n"); // This has to be a callback because none of it can be done after // BB is deleted. @@ -2687,8 +2694,8 @@ bool MachineBlockPlacement::maybeTailDuplicateBlock( if (RemBB == PreferredLoopExit) PreferredLoopExit = nullptr; - DEBUG(dbgs() << "TailDuplicator deleted block: " - << getBlockName(RemBB) << "\n"); + LLVM_DEBUG(dbgs() << "TailDuplicator deleted block: " + << getBlockName(RemBB) << "\n"); }; auto RemovalCallbackRef = function_ref<void(MachineBasicBlock*)>(RemovalCallback); diff --git a/llvm/lib/CodeGen/MachineCSE.cpp b/llvm/lib/CodeGen/MachineCSE.cpp index 75a3d071bdc..cca4aa86bb0 100644 --- a/llvm/lib/CodeGen/MachineCSE.cpp +++ b/llvm/lib/CodeGen/MachineCSE.cpp @@ -178,8 +178,8 @@ bool MachineCSE::PerformTrivialCopyPropagation(MachineInstr *MI, continue; if (!MRI->constrainRegAttrs(SrcReg, Reg)) continue; - DEBUG(dbgs() << "Coalescing: " << *DefMI); - DEBUG(dbgs() << "*** to: " << *MI); + LLVM_DEBUG(dbgs() << "Coalescing: " << *DefMI); + LLVM_DEBUG(dbgs() << "*** to: " << *MI); // Propagate SrcReg of copies to MI. MO.setReg(SrcReg); MRI->clearKillFlags(SrcReg); @@ -455,13 +455,13 @@ bool MachineCSE::isProfitableToCSE(unsigned CSReg, unsigned Reg, } void MachineCSE::EnterScope(MachineBasicBlock *MBB) { - DEBUG(dbgs() << "Entering: " << MBB->getName() << '\n'); + LLVM_DEBUG(dbgs() << "Entering: " << MBB->getName() << '\n'); ScopeType *Scope = new ScopeType(VNT); ScopeMap[MBB] = Scope; } void MachineCSE::ExitScope(MachineBasicBlock *MBB) { - DEBUG(dbgs() << "Exiting: " << MBB->getName() << '\n'); + LLVM_DEBUG(dbgs() << "Exiting: " << MBB->getName() << '\n'); DenseMap<MachineBasicBlock*, ScopeType*>::iterator SI = ScopeMap.find(MBB); assert(SI != ScopeMap.end()); delete SI->second; @@ -545,8 +545,8 @@ bool MachineCSE::ProcessBlock(MachineBasicBlock *MBB) { // Found a common subexpression, eliminate it. unsigned CSVN = VNT.lookup(MI); MachineInstr *CSMI = Exps[CSVN]; - DEBUG(dbgs() << "Examining: " << *MI); - DEBUG(dbgs() << "*** Found a common subexpression: " << *CSMI); + LLVM_DEBUG(dbgs() << "Examining: " << *MI); + LLVM_DEBUG(dbgs() << "*** Found a common subexpression: " << *CSMI); // Check if it's profitable to perform this CSE. bool DoCSE = true; @@ -580,7 +580,7 @@ bool MachineCSE::ProcessBlock(MachineBasicBlock *MBB) { "Do not CSE physical register defs!"); if (!isProfitableToCSE(NewReg, OldReg, CSMI, MI)) { - DEBUG(dbgs() << "*** Not profitable, avoid CSE!\n"); + LLVM_DEBUG(dbgs() << "*** Not profitable, avoid CSE!\n"); DoCSE = false; break; } @@ -589,7 +589,8 @@ bool MachineCSE::ProcessBlock(MachineBasicBlock *MBB) { // within the constraints (register class, bank, or low-level type) of // the old instruction. if (!MRI->constrainRegAttrs(NewReg, OldReg)) { - DEBUG(dbgs() << "*** Not the same register constraints, avoid CSE!\n"); + LLVM_DEBUG( + dbgs() << "*** Not the same register constraints, avoid CSE!\n"); DoCSE = false; break; } diff --git a/llvm/lib/CodeGen/MachineCombiner.cpp b/llvm/lib/CodeGen/MachineCombiner.cpp index 498b4cb836f..0c6efff7bb4 100644 --- a/llvm/lib/CodeGen/MachineCombiner.cpp +++ b/llvm/lib/CodeGen/MachineCombiner.cpp @@ -308,8 +308,8 @@ bool MachineCombiner::improvesCriticalPathLen( unsigned NewRootDepth = getDepth(InsInstrs, InstrIdxForVirtReg, BlockTrace); unsigned RootDepth = BlockTrace.getInstrCycles(*Root).Depth; - DEBUG(dbgs() << " Dependence data for " << *Root << "\tNewRootDepth: " - << NewRootDepth << "\tRootDepth: " << RootDepth); + LLVM_DEBUG(dbgs() << " Dependence data for " << *Root << "\tNewRootDepth: " + << NewRootDepth << "\tRootDepth: " << RootDepth); // For a transform such as reassociation, the cost equation is // conservatively calculated so that we must improve the depth (data @@ -317,9 +317,10 @@ bool MachineCombiner::improvesCriticalPathLen( // Being conservative also protects against inaccuracies in the underlying // machine trace metrics and CPU models. if (getCombinerObjective(Pattern) == CombinerObjective::MustReduceDepth) { - DEBUG(dbgs() << "\tIt MustReduceDepth "); - DEBUG(NewRootDepth < RootDepth ? dbgs() << "\t and it does it\n" - : dbgs() << "\t but it does NOT do it\n"); + LLVM_DEBUG(dbgs() << "\tIt MustReduceDepth "); + LLVM_DEBUG(NewRootDepth < RootDepth + ? dbgs() << "\t and it does it\n" + : dbgs() << "\t but it does NOT do it\n"); return NewRootDepth < RootDepth; } @@ -336,17 +337,17 @@ bool MachineCombiner::improvesCriticalPathLen( unsigned NewCycleCount = NewRootDepth + NewRootLatency; unsigned OldCycleCount = RootDepth + RootLatency + (SlackIsAccurate ? RootSlack : 0); - DEBUG(dbgs() << "\n\tNewRootLatency: " << NewRootLatency << "\tRootLatency: " - << RootLatency << "\n\tRootSlack: " << RootSlack - << " SlackIsAccurate=" << SlackIsAccurate - << "\n\tNewRootDepth + NewRootLatency = " << NewCycleCount - << "\n\tRootDepth + RootLatency + RootSlack = " - << OldCycleCount;); - DEBUG(NewCycleCount <= OldCycleCount - ? dbgs() << "\n\t It IMPROVES PathLen because" - : dbgs() << "\n\t It DOES NOT improve PathLen because"); - DEBUG(dbgs() << "\n\t\tNewCycleCount = " << NewCycleCount - << ", OldCycleCount = " << OldCycleCount << "\n"); + LLVM_DEBUG(dbgs() << "\n\tNewRootLatency: " << NewRootLatency + << "\tRootLatency: " << RootLatency << "\n\tRootSlack: " + << RootSlack << " SlackIsAccurate=" << SlackIsAccurate + << "\n\tNewRootDepth + NewRootLatency = " << NewCycleCount + << "\n\tRootDepth + RootLatency + RootSlack = " + << OldCycleCount;); + LLVM_DEBUG(NewCycleCount <= OldCycleCount + ? dbgs() << "\n\t It IMPROVES PathLen because" + : dbgs() << "\n\t It DOES NOT improve PathLen because"); + LLVM_DEBUG(dbgs() << "\n\t\tNewCycleCount = " << NewCycleCount + << ", OldCycleCount = " << OldCycleCount << "\n"); return NewCycleCount <= OldCycleCount; } @@ -392,10 +393,10 @@ bool MachineCombiner::preservesResourceLen( unsigned ResLenAfterCombine = BlockTrace.getResourceLength(MBBarr, MSCInsArr, MSCDelArr); - DEBUG(dbgs() << "\t\tResource length before replacement: " - << ResLenBeforeCombine << " and after: " << ResLenAfterCombine - << "\n";); - DEBUG( + LLVM_DEBUG(dbgs() << "\t\tResource length before replacement: " + << ResLenBeforeCombine + << " and after: " << ResLenAfterCombine << "\n";); + LLVM_DEBUG( ResLenAfterCombine <= ResLenBeforeCombine ? dbgs() << "\t\t As result it IMPROVES/PRESERVES Resource Length\n" : dbgs() << "\t\t As result it DOES NOT improve/preserve Resource " @@ -492,7 +493,7 @@ void MachineCombiner::verifyPatternOrder( /// sequence is shorter. bool MachineCombiner::combineInstructions(MachineBasicBlock *MBB) { bool Changed = false; - DEBUG(dbgs() << "Combining MBB " << MBB->getName() << "\n"); + LLVM_DEBUG(dbgs() << "Combining MBB " << MBB->getName() << "\n"); bool IncrementalUpdate = false; auto BlockIter = MBB->begin(); @@ -555,7 +556,7 @@ bool MachineCombiner::combineInstructions(MachineBasicBlock *MBB) { if (!NewInstCount) continue; - DEBUG(if (dump_intrs) { + LLVM_DEBUG(if (dump_intrs) { dbgs() << "\tFor the Pattern (" << (int)P << ") these instructions could be removed\n"; for (auto const *InstrPtr : DelInstrs) { dbgs() << "\t\t" << STI->getSchedInfoStr(*InstrPtr) << ": "; @@ -640,9 +641,11 @@ bool MachineCombiner::runOnMachineFunction(MachineFunction &MF) { MinInstr = nullptr; OptSize = MF.getFunction().optForSize(); - DEBUG(dbgs() << getPassName() << ": " << MF.getName() << '\n'); + LLVM_DEBUG(dbgs() << getPassName() << ": " << MF.getName() << '\n'); if (!TII->useMachineCombiner()) { - DEBUG(dbgs() << " Skipping pass: Target does not support machine combiner\n"); + LLVM_DEBUG( + dbgs() + << " Skipping pass: Target does not support machine combiner\n"); return false; } diff --git a/llvm/lib/CodeGen/MachineCopyPropagation.cpp b/llvm/lib/CodeGen/MachineCopyPropagation.cpp index 8b6777f06db..d3bdc772ae4 100644 --- a/llvm/lib/CodeGen/MachineCopyPropagation.cpp +++ b/llvm/lib/CodeGen/MachineCopyPropagation.cpp @@ -181,7 +181,8 @@ void MachineCopyPropagation::ReadRegister(unsigned Reg) { for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) { Reg2MIMap::iterator CI = CopyMap.find(*AI); if (CI != CopyMap.end()) { - DEBUG(dbgs() << "MCP: Copy is used - not dead: "; CI->second->dump()); + LLVM_DEBUG(dbgs() << "MCP: Copy is used - not dead: "; + CI->second->dump()); MaybeDeadCopies.remove(CI->second); } } @@ -229,7 +230,7 @@ bool MachineCopyPropagation::eraseIfRedundant(MachineInstr &Copy, unsigned Src, if (!isNopCopy(PrevCopy, Src, Def, TRI)) return false; - DEBUG(dbgs() << "MCP: copy is a NOP, removing: "; Copy.dump()); + LLVM_DEBUG(dbgs() << "MCP: copy is a NOP, removing: "; Copy.dump()); // Copy was redundantly redefining either Src or Def. Remove earlier kill // flags between Copy and PrevCopy because the value will be reused now. @@ -351,8 +352,9 @@ void MachineCopyPropagation::forwardUses(MachineInstr &MI) { // FIXME: Don't handle partial uses of wider COPYs yet. if (MOUse.getReg() != CopyDstReg) { - DEBUG(dbgs() << "MCP: FIXME! Not forwarding COPY to sub-register use:\n " - << MI); + LLVM_DEBUG( + dbgs() << "MCP: FIXME! Not forwarding COPY to sub-register use:\n " + << MI); continue; } @@ -367,20 +369,20 @@ void MachineCopyPropagation::forwardUses(MachineInstr &MI) { continue; if (!DebugCounter::shouldExecute(FwdCounter)) { - DEBUG(dbgs() << "MCP: Skipping forwarding due to debug counter:\n " - << MI); + LLVM_DEBUG(dbgs() << "MCP: Skipping forwarding due to debug counter:\n " + << MI); continue; } - DEBUG(dbgs() << "MCP: Replacing " << printReg(MOUse.getReg(), TRI) - << "\n with " << printReg(CopySrcReg, TRI) << "\n in " - << MI << " from " << Copy); + LLVM_DEBUG(dbgs() << "MCP: Replacing " << printReg(MOUse.getReg(), TRI) + << "\n with " << printReg(CopySrcReg, TRI) + << "\n in " << MI << " from " << Copy); MOUse.setReg(CopySrcReg); if (!CopySrc.isRenamable()) MOUse.setIsRenamable(false); - DEBUG(dbgs() << "MCP: After replacement: " << MI << "\n"); + LLVM_DEBUG(dbgs() << "MCP: After replacement: " << MI << "\n"); // Clear kill markers that may have been invalidated. for (MachineInstr &KMI : @@ -393,7 +395,7 @@ void MachineCopyPropagation::forwardUses(MachineInstr &MI) { } void MachineCopyPropagation::CopyPropagateBlock(MachineBasicBlock &MBB) { - DEBUG(dbgs() << "MCP: CopyPropagateBlock " << MBB.getName() << "\n"); + LLVM_DEBUG(dbgs() << "MCP: CopyPropagateBlock " << MBB.getName() << "\n"); for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ) { MachineInstr *MI = &*I; @@ -444,7 +446,7 @@ void MachineCopyPropagation::CopyPropagateBlock(MachineBasicBlock &MBB) { ReadRegister(Reg); } - DEBUG(dbgs() << "MCP: Copy is a deletion candidate: "; MI->dump()); + LLVM_DEBUG(dbgs() << "MCP: Copy is a deletion candidate: "; MI->dump()); // Copy is now a candidate for deletion. if (!MRI->isReserved(Def)) @@ -536,8 +538,8 @@ void MachineCopyPropagation::CopyPropagateBlock(MachineBasicBlock &MBB) { continue; } - DEBUG(dbgs() << "MCP: Removing copy due to regmask clobbering: "; - MaybeDead->dump()); + LLVM_DEBUG(dbgs() << "MCP: Removing copy due to regmask clobbering: "; + MaybeDead->dump()); // erase() will return the next valid iterator pointing to the next // element after the erased one. @@ -569,8 +571,8 @@ void MachineCopyPropagation::CopyPropagateBlock(MachineBasicBlock &MBB) { // since we don't want to trust live-in lists. if (MBB.succ_empty()) { for (MachineInstr *MaybeDead : MaybeDeadCopies) { - DEBUG(dbgs() << "MCP: Removing copy due to no live-out succ: "; - MaybeDead->dump()); + LLVM_DEBUG(dbgs() << "MCP: Removing copy due to no live-out succ: "; + MaybeDead->dump()); assert(!MRI->isReserved(MaybeDead->getOperand(0).getReg())); MaybeDead->eraseFromParent(); Changed = true; diff --git a/llvm/lib/CodeGen/MachineFrameInfo.cpp b/llvm/lib/CodeGen/MachineFrameInfo.cpp index d0c737b261d..0b316871dbd 100644 --- a/llvm/lib/CodeGen/MachineFrameInfo.cpp +++ b/llvm/lib/CodeGen/MachineFrameInfo.cpp @@ -41,9 +41,9 @@ static inline unsigned clampStackAlignment(bool ShouldClamp, unsigned Align, unsigned StackAlign) { if (!ShouldClamp || Align <= StackAlign) return Align; - DEBUG(dbgs() << "Warning: requested alignment " << Align - << " exceeds the stack alignment " << StackAlign - << " when stack realignment is off" << '\n'); + LLVM_DEBUG(dbgs() << "Warning: requested alignment " << Align + << " exceeds the stack alignment " << StackAlign + << " when stack realignment is off" << '\n'); return StackAlign; } diff --git a/llvm/lib/CodeGen/MachineLICM.cpp b/llvm/lib/CodeGen/MachineLICM.cpp index 0ad3ef18e55..e2d92009f21 100644 --- a/llvm/lib/CodeGen/MachineLICM.cpp +++ b/llvm/lib/CodeGen/MachineLICM.cpp @@ -319,10 +319,10 @@ bool MachineLICMBase::runOnMachineFunction(MachineFunction &MF) { PreRegAlloc = MRI->isSSA(); if (PreRegAlloc) - DEBUG(dbgs() << "******** Pre-regalloc Machine LICM: "); + LLVM_DEBUG(dbgs() << "******** Pre-regalloc Machine LICM: "); else - DEBUG(dbgs() << "******** Post-regalloc Machine LICM: "); - DEBUG(dbgs() << MF.getName() << " ********\n"); + LLVM_DEBUG(dbgs() << "******** Post-regalloc Machine LICM: "); + LLVM_DEBUG(dbgs() << MF.getName() << " ********\n"); if (PreRegAlloc) { // Estimate register pressure during pre-regalloc pass. @@ -591,8 +591,9 @@ void MachineLICMBase::HoistPostRA(MachineInstr *MI, unsigned Def) { // Now move the instructions to the predecessor, inserting it before any // terminator instructions. - DEBUG(dbgs() << "Hoisting to " << printMBBReference(*Preheader) << " from " - << printMBBReference(*MI->getParent()) << ": " << *MI); + LLVM_DEBUG(dbgs() << "Hoisting to " << printMBBReference(*Preheader) + << " from " << printMBBReference(*MI->getParent()) << ": " + << *MI); // Splice the instruction to the preheader. MachineBasicBlock *MBB = MI->getParent(); @@ -629,14 +630,14 @@ bool MachineLICMBase::IsGuaranteedToExecute(MachineBasicBlock *BB) { } void MachineLICMBase::EnterScope(MachineBasicBlock *MBB) { - DEBUG(dbgs() << "Entering " << printMBBReference(*MBB) << '\n'); + LLVM_DEBUG(dbgs() << "Entering " << printMBBReference(*MBB) << '\n'); // Remember livein register pressure. BackTrace.push_back(RegPressure); } void MachineLICMBase::ExitScope(MachineBasicBlock *MBB) { - DEBUG(dbgs() << "Exiting " << printMBBReference(*MBB) << '\n'); + LLVM_DEBUG(dbgs() << "Exiting " << printMBBReference(*MBB) << '\n'); BackTrace.pop_back(); } @@ -1208,7 +1209,7 @@ bool MachineLICMBase::IsProfitableToHoist(MachineInstr &MI) { // Don't hoist a cheap instruction if it would create a copy in the loop. if (CheapInstr && CreatesCopy) { - DEBUG(dbgs() << "Won't hoist cheap instr with loop PHI use: " << MI); + LLVM_DEBUG(dbgs() << "Won't hoist cheap instr with loop PHI use: " << MI); return false; } @@ -1227,7 +1228,7 @@ bool MachineLICMBase::IsProfitableToHoist(MachineInstr &MI) { if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue; if (MO.isDef() && HasHighOperandLatency(MI, i, Reg)) { - DEBUG(dbgs() << "Hoist High Latency: " << MI); + LLVM_DEBUG(dbgs() << "Hoist High Latency: " << MI); ++NumHighLatency; return true; } @@ -1245,14 +1246,14 @@ bool MachineLICMBase::IsProfitableToHoist(MachineInstr &MI) { // Visit BBs from header to current BB, if hoisting this doesn't cause // high register pressure, then it's safe to proceed. if (!CanCauseHighRegPressure(Cost, CheapInstr)) { - DEBUG(dbgs() << "Hoist non-reg-pressure: " << MI); + LLVM_DEBUG(dbgs() << "Hoist non-reg-pressure: " << MI); ++NumLowRP; return true; } // Don't risk increasing register pressure if it would create copies. if (CreatesCopy) { - DEBUG(dbgs() << "Won't hoist instr with loop PHI use: " << MI); + LLVM_DEBUG(dbgs() << "Won't hoist instr with loop PHI use: " << MI); return false; } @@ -1261,7 +1262,7 @@ bool MachineLICMBase::IsProfitableToHoist(MachineInstr &MI) { // conservative. if (AvoidSpeculation && (!IsGuaranteedToExecute(MI.getParent()) && !MayCSE(&MI))) { - DEBUG(dbgs() << "Won't speculate: " << MI); + LLVM_DEBUG(dbgs() << "Won't speculate: " << MI); return false; } @@ -1269,7 +1270,7 @@ bool MachineLICMBase::IsProfitableToHoist(MachineInstr &MI) { // to be remat'ed. if (!TII->isTriviallyReMaterializable(MI, AA) && !MI.isDereferenceableInvariantLoad(AA)) { - DEBUG(dbgs() << "Can't remat / high reg-pressure: " << MI); + LLVM_DEBUG(dbgs() << "Can't remat / high reg-pressure: " << MI); return false; } @@ -1366,7 +1367,7 @@ bool MachineLICMBase::EliminateCSE(MachineInstr *MI, return false; if (const MachineInstr *Dup = LookForDuplicate(MI, CI->second)) { - DEBUG(dbgs() << "CSEing " << *MI << " with " << *Dup); + LLVM_DEBUG(dbgs() << "CSEing " << *MI << " with " << *Dup); // Replace virtual registers defined by MI by their counterparts defined // by Dup. @@ -1446,14 +1447,14 @@ bool MachineLICMBase::Hoist(MachineInstr *MI, MachineBasicBlock *Preheader) { // Now move the instructions to the predecessor, inserting it before any // terminator instructions. - DEBUG({ - dbgs() << "Hoisting " << *MI; - if (MI->getParent()->getBasicBlock()) - dbgs() << " from " << printMBBReference(*MI->getParent()); - if (Preheader->getBasicBlock()) - dbgs() << " to " << printMBBReference(*Preheader); - dbgs() << "\n"; - }); + LLVM_DEBUG({ + dbgs() << "Hoisting " << *MI; + if (MI->getParent()->getBasicBlock()) + dbgs() << " from " << printMBBReference(*MI->getParent()); + if (Preheader->getBasicBlock()) + dbgs() << " to " << printMBBReference(*Preheader); + dbgs() << "\n"; + }); // If this is the first instruction being hoisted to the preheader, // initialize the CSE map with potential common expressions. diff --git a/llvm/lib/CodeGen/MachineOutliner.cpp b/llvm/lib/CodeGen/MachineOutliner.cpp index e9000fffdb5..a524fca972e 100644 --- a/llvm/lib/CodeGen/MachineOutliner.cpp +++ b/llvm/lib/CodeGen/MachineOutliner.cpp @@ -1112,11 +1112,11 @@ void MachineOutliner::prune(Candidate &C, // Remove C from the CandidateList. C.InCandidateList = false; - DEBUG(dbgs() << "- Removed a Candidate \n"; - dbgs() << "--- Num fns left for candidate: " << F.getOccurrenceCount() - << "\n"; - dbgs() << "--- Candidate's functions's benefit: " << F.getBenefit() - << "\n";); + LLVM_DEBUG(dbgs() << "- Removed a Candidate \n"; + dbgs() << "--- Num fns left for candidate: " + << F.getOccurrenceCount() << "\n"; + dbgs() << "--- Candidate's functions's benefit: " << F.getBenefit() + << "\n";); } void MachineOutliner::pruneOverlaps( @@ -1441,7 +1441,7 @@ bool MachineOutliner::outline( NumOutlined++; } - DEBUG(dbgs() << "OutlinedSomething = " << OutlinedSomething << "\n";); + LLVM_DEBUG(dbgs() << "OutlinedSomething = " << OutlinedSomething << "\n";); return OutlinedSomething; } @@ -1461,8 +1461,9 @@ bool MachineOutliner::runOnModule(Module &M) { // Does the target implement the MachineOutliner? If it doesn't, quit here. if (!TII->useMachineOutliner()) { // No. So we're done. - DEBUG(dbgs() - << "Skipping pass: Target does not support the MachineOutliner.\n"); + LLVM_DEBUG( + dbgs() + << "Skipping pass: Target does not support the MachineOutliner.\n"); return false; } diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp index da2e67832bd..ef96cec4f97 100644 --- a/llvm/lib/CodeGen/MachinePipeliner.cpp +++ b/llvm/lib/CodeGen/MachinePipeliner.cpp @@ -886,7 +886,7 @@ void SwingSchedulerDAG::schedule() { Topo.InitDAGTopologicalSorting(); postprocessDAG(); changeDependences(); - DEBUG({ + LLVM_DEBUG({ for (unsigned su = 0, e = SUnits.size(); su != e; ++su) SUnits[su].dumpAll(this); }); @@ -906,8 +906,8 @@ void SwingSchedulerDAG::schedule() { RecMII = 0; MII = std::max(ResMII, RecMII); - DEBUG(dbgs() << "MII = " << MII << " (rec=" << RecMII << ", res=" << ResMII - << ")\n"); + LLVM_DEBUG(dbgs() << "MII = " << MII << " (rec=" << RecMII + << ", res=" << ResMII << ")\n"); // Can't schedule a loop without a valid MII. if (MII == 0) @@ -925,7 +925,7 @@ void SwingSchedulerDAG::schedule() { checkNodeSets(NodeSets); - DEBUG({ + LLVM_DEBUG({ for (auto &I : NodeSets) { dbgs() << " Rec NodeSet "; I.dump(); @@ -938,7 +938,7 @@ void SwingSchedulerDAG::schedule() { removeDuplicateNodes(NodeSets); - DEBUG({ + LLVM_DEBUG({ for (auto &I : NodeSets) { dbgs() << " NodeSet "; I.dump(); @@ -1634,7 +1634,7 @@ static bool ignoreDependence(const SDep &D, bool isPred) { void SwingSchedulerDAG::computeNodeFunctions(NodeSetType &NodeSets) { ScheduleInfo.resize(SUnits.size()); - DEBUG({ + LLVM_DEBUG({ for (ScheduleDAGTopologicalSort::const_iterator I = Topo.begin(), E = Topo.end(); I != E; ++I) { @@ -1696,7 +1696,7 @@ void SwingSchedulerDAG::computeNodeFunctions(NodeSetType &NodeSets) { for (NodeSet &I : NodeSets) I.computeNodeSetInfo(this); - DEBUG({ + LLVM_DEBUG({ for (unsigned i = 0; i < SUnits.size(); i++) { dbgs() << "\tNode " << i << ":\n"; dbgs() << "\t ASAP = " << getASAP(&SUnits[i]) << "\n"; @@ -1883,9 +1883,10 @@ void SwingSchedulerDAG::registerPressureFilter(NodeSetType &NodeSets) { CriticalPSets, RecRegPressure.MaxSetPressure); if (RPDelta.Excess.isValid()) { - DEBUG(dbgs() << "Excess register pressure: SU(" << SU->NodeNum << ") " - << TRI->getRegPressureSetName(RPDelta.Excess.getPSet()) - << ":" << RPDelta.Excess.getUnitInc()); + LLVM_DEBUG( + dbgs() << "Excess register pressure: SU(" << SU->NodeNum << ") " + << TRI->getRegPressureSetName(RPDelta.Excess.getPSet()) + << ":" << RPDelta.Excess.getUnitInc()); NS.setExceedPressure(SU); break; } @@ -1936,7 +1937,7 @@ void SwingSchedulerDAG::checkNodeSets(NodeSetType &NodeSets) { return; } NodeSets.clear(); - DEBUG(dbgs() << "Clear recurrence node-sets\n"); + LLVM_DEBUG(dbgs() << "Clear recurrence node-sets\n"); return; } @@ -2082,28 +2083,28 @@ void SwingSchedulerDAG::computeNodeOrder(NodeSetType &NodeSets) { NodeOrder.clear(); for (auto &Nodes : NodeSets) { - DEBUG(dbgs() << "NodeSet size " << Nodes.size() << "\n"); + LLVM_DEBUG(dbgs() << "NodeSet size " << Nodes.size() << "\n"); OrderKind Order; SmallSetVector<SUnit *, 8> N; if (pred_L(NodeOrder, N) && isSubset(N, Nodes)) { R.insert(N.begin(), N.end()); Order = BottomUp; - DEBUG(dbgs() << " Bottom up (preds) "); + LLVM_DEBUG(dbgs() << " Bottom up (preds) "); } else if (succ_L(NodeOrder, N) && isSubset(N, Nodes)) { R.insert(N.begin(), N.end()); Order = TopDown; - DEBUG(dbgs() << " Top down (succs) "); + LLVM_DEBUG(dbgs() << " Top down (succs) "); } else if (isIntersect(N, Nodes, R)) { // If some of the successors are in the existing node-set, then use the // top-down ordering. Order = TopDown; - DEBUG(dbgs() << " Top down (intersect) "); + LLVM_DEBUG(dbgs() << " Top down (intersect) "); } else if (NodeSets.size() == 1) { for (auto &N : Nodes) if (N->Succs.size() == 0) R.insert(N); Order = BottomUp; - DEBUG(dbgs() << " Bottom up (all) "); + LLVM_DEBUG(dbgs() << " Bottom up (all) "); } else { // Find the node with the highest ASAP. SUnit *maxASAP = nullptr; @@ -2114,7 +2115,7 @@ void SwingSchedulerDAG::computeNodeOrder(NodeSetType &NodeSets) { } R.insert(maxASAP); Order = BottomUp; - DEBUG(dbgs() << " Bottom up (default) "); + LLVM_DEBUG(dbgs() << " Bottom up (default) "); } while (!R.empty()) { @@ -2137,7 +2138,7 @@ void SwingSchedulerDAG::computeNodeOrder(NodeSetType &NodeSets) { maxHeight = I; } NodeOrder.insert(maxHeight); - DEBUG(dbgs() << maxHeight->NodeNum << " "); + LLVM_DEBUG(dbgs() << maxHeight->NodeNum << " "); R.remove(maxHeight); for (const auto &I : maxHeight->Succs) { if (Nodes.count(I.getSUnit()) == 0) @@ -2160,7 +2161,7 @@ void SwingSchedulerDAG::computeNodeOrder(NodeSetType &NodeSets) { } } Order = BottomUp; - DEBUG(dbgs() << "\n Switching order to bottom up "); + LLVM_DEBUG(dbgs() << "\n Switching order to bottom up "); SmallSetVector<SUnit *, 8> N; if (pred_L(NodeOrder, N, &Nodes)) R.insert(N.begin(), N.end()); @@ -2182,7 +2183,7 @@ void SwingSchedulerDAG::computeNodeOrder(NodeSetType &NodeSets) { maxDepth = I; } NodeOrder.insert(maxDepth); - DEBUG(dbgs() << maxDepth->NodeNum << " "); + LLVM_DEBUG(dbgs() << maxDepth->NodeNum << " "); R.remove(maxDepth); if (Nodes.isExceedSU(maxDepth)) { Order = TopDown; @@ -2209,16 +2210,16 @@ void SwingSchedulerDAG::computeNodeOrder(NodeSetType &NodeSets) { } } Order = TopDown; - DEBUG(dbgs() << "\n Switching order to top down "); + LLVM_DEBUG(dbgs() << "\n Switching order to top down "); SmallSetVector<SUnit *, 8> N; if (succ_L(NodeOrder, N, &Nodes)) R.insert(N.begin(), N.end()); } } - DEBUG(dbgs() << "\nDone with Nodeset\n"); + LLVM_DEBUG(dbgs() << "\nDone with Nodeset\n"); } - DEBUG({ + LLVM_DEBUG({ dbgs() << "Node order: "; for (SUnit *I : NodeOrder) dbgs() << " " << I->NodeNum << " "; @@ -2237,7 +2238,7 @@ bool SwingSchedulerDAG::schedulePipeline(SMSchedule &Schedule) { for (unsigned II = MII; II < MII + 10 && !scheduleFound; ++II) { Schedule.reset(); Schedule.setInitiationInterval(II); - DEBUG(dbgs() << "Try to schedule with " << II << "\n"); + LLVM_DEBUG(dbgs() << "Try to schedule with " << II << "\n"); SetVector<SUnit *>::iterator NI = NodeOrder.begin(); SetVector<SUnit *>::iterator NE = NodeOrder.end(); @@ -2254,12 +2255,12 @@ bool SwingSchedulerDAG::schedulePipeline(SMSchedule &Schedule) { int SchedStart = INT_MIN; Schedule.computeStart(SU, &EarlyStart, &LateStart, &SchedEnd, &SchedStart, II, this); - DEBUG({ + LLVM_DEBUG({ dbgs() << "Inst (" << SU->NodeNum << ") "; SU->getInstr()->dump(); dbgs() << "\n"; }); - DEBUG({ + LLVM_DEBUG({ dbgs() << "\tes: " << EarlyStart << " ls: " << LateStart << " me: " << SchedEnd << " ms: " << SchedStart << "\n"; }); @@ -2295,7 +2296,7 @@ bool SwingSchedulerDAG::schedulePipeline(SMSchedule &Schedule) { Schedule.getMaxStageCount() > (unsigned)SwpMaxStages) scheduleFound = false; - DEBUG({ + LLVM_DEBUG({ if (!scheduleFound) dbgs() << "\tCan't schedule\n"; }); @@ -2306,7 +2307,7 @@ bool SwingSchedulerDAG::schedulePipeline(SMSchedule &Schedule) { scheduleFound = Schedule.isValidSchedule(this); } - DEBUG(dbgs() << "Schedule Found? " << scheduleFound << "\n"); + LLVM_DEBUG(dbgs() << "Schedule Found? " << scheduleFound << "\n"); if (scheduleFound) Schedule.finalizeSchedule(this); @@ -2376,7 +2377,7 @@ void SwingSchedulerDAG::generatePipelinedLoop(SMSchedule &Schedule) { generatePhis(KernelBB, PrologBBs.back(), KernelBB, KernelBB, Schedule, VRMap, InstrMap, MaxStageCount, MaxStageCount, false); - DEBUG(dbgs() << "New block\n"; KernelBB->dump();); + LLVM_DEBUG(dbgs() << "New block\n"; KernelBB->dump();); SmallVector<MachineBasicBlock *, 4> EpilogBBs; // Generate the epilog instructions to complete the pipeline. @@ -2445,7 +2446,7 @@ void SwingSchedulerDAG::generateProlog(SMSchedule &Schedule, unsigned LastStage, } } rewritePhiValues(NewBB, i, Schedule, VRMap, InstrMap); - DEBUG({ + LLVM_DEBUG({ dbgs() << "prolog:\n"; NewBB->dump(); }); @@ -2527,7 +2528,7 @@ void SwingSchedulerDAG::generateEpilog(SMSchedule &Schedule, unsigned LastStage, InstrMap, LastStage, EpilogStage, i == 1); PredBB = NewBB; - DEBUG({ + LLVM_DEBUG({ dbgs() << "epilog:\n"; NewBB->dump(); }); @@ -3625,7 +3626,7 @@ bool SMSchedule::insert(SUnit *SU, int StartCycle, int EndCycle, int II) { } if (ST.getInstrInfo()->isZeroCost(SU->getInstr()->getOpcode()) || Resources->canReserveResources(*SU->getInstr())) { - DEBUG({ + LLVM_DEBUG({ dbgs() << "\tinsert at cycle " << curCycle << " "; SU->getInstr()->dump(); }); @@ -3638,7 +3639,7 @@ bool SMSchedule::insert(SUnit *SU, int StartCycle, int EndCycle, int II) { FirstCycle = curCycle; return true; } - DEBUG({ + LLVM_DEBUG({ dbgs() << "\tfailed to insert at cycle " << curCycle << " "; SU->getInstr()->dump(); }); @@ -4034,18 +4035,19 @@ void SwingSchedulerDAG::checkValidNodeOrder(const NodeSetType &Circuits) const { Circuits.begin(), Circuits.end(), [SU](const NodeSet &Circuit) { return Circuit.count(SU); }); if (InCircuit) - DEBUG(dbgs() << "In a circuit, predecessor ";); + LLVM_DEBUG(dbgs() << "In a circuit, predecessor ";); else { Valid = false; NumNodeOrderIssues++; - DEBUG(dbgs() << "Predecessor ";); + LLVM_DEBUG(dbgs() << "Predecessor ";); } - DEBUG(dbgs() << Pred->NodeNum << " and successor " << Succ->NodeNum - << " are scheduled before node " << SU->NodeNum << "\n";); + LLVM_DEBUG(dbgs() << Pred->NodeNum << " and successor " << Succ->NodeNum + << " are scheduled before node " << SU->NodeNum + << "\n";); } } - DEBUG({ + LLVM_DEBUG({ if (!Valid) dbgs() << "Invalid node order found!\n"; }); @@ -4188,7 +4190,7 @@ void SMSchedule::finalizeSchedule(SwingSchedulerDAG *SSD) { SSD->fixupRegisterOverlaps(cycleInstrs); } - DEBUG(dump();); + LLVM_DEBUG(dump();); } #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) diff --git a/llvm/lib/CodeGen/MachineRegionInfo.cpp b/llvm/lib/CodeGen/MachineRegionInfo.cpp index 88fb7e1dde3..2619d8f7827 100644 --- a/llvm/lib/CodeGen/MachineRegionInfo.cpp +++ b/llvm/lib/CodeGen/MachineRegionInfo.cpp @@ -90,7 +90,7 @@ bool MachineRegionInfoPass::runOnMachineFunction(MachineFunction &F) { RI.recalculate(F, DT, PDT, DF); - DEBUG(RI.dump()); + LLVM_DEBUG(RI.dump()); return false; } diff --git a/llvm/lib/CodeGen/MachineSSAUpdater.cpp b/llvm/lib/CodeGen/MachineSSAUpdater.cpp index 36844e9fb30..773661965f1 100644 --- a/llvm/lib/CodeGen/MachineSSAUpdater.cpp +++ b/llvm/lib/CodeGen/MachineSSAUpdater.cpp @@ -204,7 +204,7 @@ unsigned MachineSSAUpdater::GetValueInMiddleOfBlock(MachineBasicBlock *BB) { // If the client wants to know about all new instructions, tell it. if (InsertedPHIs) InsertedPHIs->push_back(InsertedPHI); - DEBUG(dbgs() << " Inserted PHI: " << *InsertedPHI << "\n"); + LLVM_DEBUG(dbgs() << " Inserted PHI: " << *InsertedPHI << "\n"); return InsertedPHI->getOperand(0).getReg(); } diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp index cee87be9249..c2c0d347f5e 100644 --- a/llvm/lib/CodeGen/MachineScheduler.cpp +++ b/llvm/lib/CodeGen/MachineScheduler.cpp @@ -361,7 +361,7 @@ bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) { } else if (!mf.getSubtarget().enableMachineScheduler()) return false; - DEBUG(dbgs() << "Before MISched:\n"; mf.print(dbgs())); + LLVM_DEBUG(dbgs() << "Before MISched:\n"; mf.print(dbgs())); // Initialize the context of the pass. MF = &mf; @@ -373,7 +373,7 @@ bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) { LIS = &getAnalysis<LiveIntervals>(); if (VerifyScheduling) { - DEBUG(LIS->dump()); + LLVM_DEBUG(LIS->dump()); MF->verify(this, "Before machine scheduling."); } RegClassInfo->runOnMachineFunction(*MF); @@ -383,7 +383,7 @@ bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) { std::unique_ptr<ScheduleDAGInstrs> Scheduler(createMachineScheduler()); scheduleRegions(*Scheduler, false); - DEBUG(LIS->dump()); + LLVM_DEBUG(LIS->dump()); if (VerifyScheduling) MF->verify(this, "After machine scheduling."); return true; @@ -397,10 +397,10 @@ bool PostMachineScheduler::runOnMachineFunction(MachineFunction &mf) { if (!EnablePostRAMachineSched) return false; } else if (!mf.getSubtarget().enablePostRAScheduler()) { - DEBUG(dbgs() << "Subtarget disables post-MI-sched.\n"); + LLVM_DEBUG(dbgs() << "Subtarget disables post-MI-sched.\n"); return false; } - DEBUG(dbgs() << "Before post-MI-sched:\n"; mf.print(dbgs())); + LLVM_DEBUG(dbgs() << "Before post-MI-sched:\n"; mf.print(dbgs())); // Initialize the context of the pass. MF = &mf; @@ -548,12 +548,13 @@ void MachineSchedulerBase::scheduleRegions(ScheduleDAGInstrs &Scheduler, Scheduler.exitRegion(); continue; } - DEBUG(dbgs() << "********** MI Scheduling **********\n"); - DEBUG(dbgs() << MF->getName() << ":" << printMBBReference(*MBB) << " " - << MBB->getName() << "\n From: " << *I << " To: "; - if (RegionEnd != MBB->end()) dbgs() << *RegionEnd; - else dbgs() << "End"; - dbgs() << " RegionInstrs: " << NumRegionInstrs << '\n'); + LLVM_DEBUG(dbgs() << "********** MI Scheduling **********\n"); + LLVM_DEBUG(dbgs() << MF->getName() << ":" << printMBBReference(*MBB) + << " " << MBB->getName() << "\n From: " << *I + << " To: "; + if (RegionEnd != MBB->end()) dbgs() << *RegionEnd; + else dbgs() << "End"; + dbgs() << " RegionInstrs: " << NumRegionInstrs << '\n'); if (DumpCriticalPathLength) { errs() << MF->getName(); errs() << ":%bb. " << MBB->getNumber(); @@ -750,8 +751,8 @@ bool ScheduleDAGMI::checkSchedLimit() { /// does not consider liveness or register pressure. It is useful for PostRA /// scheduling and potentially other custom schedulers. void ScheduleDAGMI::schedule() { - DEBUG(dbgs() << "ScheduleDAGMI::schedule starting\n"); - DEBUG(SchedImpl->dumpPolicy()); + LLVM_DEBUG(dbgs() << "ScheduleDAGMI::schedule starting\n"); + LLVM_DEBUG(SchedImpl->dumpPolicy()); // Build the DAG. buildSchedGraph(AA); @@ -763,14 +764,10 @@ void ScheduleDAGMI::schedule() { SmallVector<SUnit*, 8> TopRoots, BotRoots; findRootsAndBiasEdges(TopRoots, BotRoots); - DEBUG( - if (EntrySU.getInstr() != nullptr) - EntrySU.dumpAll(this); - for (const SUnit &SU : SUnits) - SU.dumpAll(this); - if (ExitSU.getInstr() != nullptr) - ExitSU.dumpAll(this); - ); + LLVM_DEBUG(if (EntrySU.getInstr() != nullptr) EntrySU.dumpAll(this); + for (const SUnit &SU + : SUnits) SU.dumpAll(this); + if (ExitSU.getInstr() != nullptr) ExitSU.dumpAll(this);); if (ViewMISchedDAGs) viewGraph(); // Initialize the strategy before modifying the DAG. @@ -782,7 +779,7 @@ void ScheduleDAGMI::schedule() { bool IsTopNode = false; while (true) { - DEBUG(dbgs() << "** ScheduleDAGMI::schedule picking next node\n"); + LLVM_DEBUG(dbgs() << "** ScheduleDAGMI::schedule picking next node\n"); SUnit *SU = SchedImpl->pickNode(IsTopNode); if (!SU) break; @@ -822,7 +819,7 @@ void ScheduleDAGMI::schedule() { placeDebugValues(); - DEBUG({ + LLVM_DEBUG({ dbgs() << "*** Final schedule for " << printMBBReference(*begin()->getParent()) << " ***\n"; dumpSchedule(); @@ -1017,7 +1014,7 @@ void ScheduleDAGMILive::initRegPressure() { // Close the RPTracker to finalize live ins. RPTracker.closeRegion(); - DEBUG(RPTracker.dump()); + LLVM_DEBUG(RPTracker.dump()); // Initialize the live ins and live outs. TopRPTracker.addLiveRegs(RPTracker.getPressure().LiveInRegs); @@ -1032,8 +1029,8 @@ void ScheduleDAGMILive::initRegPressure() { BotRPTracker.initLiveThru(RPTracker); if (!BotRPTracker.getLiveThru().empty()) { TopRPTracker.initLiveThru(BotRPTracker.getLiveThru()); - DEBUG(dbgs() << "Live Thru: "; - dumpRegSetPressure(BotRPTracker.getLiveThru(), TRI)); + LLVM_DEBUG(dbgs() << "Live Thru: "; + dumpRegSetPressure(BotRPTracker.getLiveThru(), TRI)); }; // For each live out vreg reduce the pressure change associated with other @@ -1047,12 +1044,10 @@ void ScheduleDAGMILive::initRegPressure() { updatePressureDiffs(LiveUses); } - DEBUG( - dbgs() << "Top Pressure:\n"; - dumpRegSetPressure(TopRPTracker.getRegSetPressureAtPos(), TRI); - dbgs() << "Bottom Pressure:\n"; - dumpRegSetPressure(BotRPTracker.getRegSetPressureAtPos(), TRI); - ); + LLVM_DEBUG(dbgs() << "Top Pressure:\n"; + dumpRegSetPressure(TopRPTracker.getRegSetPressureAtPos(), TRI); + dbgs() << "Bottom Pressure:\n"; + dumpRegSetPressure(BotRPTracker.getRegSetPressureAtPos(), TRI);); assert((BotRPTracker.getPos() == RegionEnd || (RegionEnd->isDebugInstr() && @@ -1067,17 +1062,16 @@ void ScheduleDAGMILive::initRegPressure() { for (unsigned i = 0, e = RegionPressure.size(); i < e; ++i) { unsigned Limit = RegClassInfo->getRegPressureSetLimit(i); if (RegionPressure[i] > Limit) { - DEBUG(dbgs() << TRI->getRegPressureSetName(i) - << " Limit " << Limit - << " Actual " << RegionPressure[i] << "\n"); + LLVM_DEBUG(dbgs() << TRI->getRegPressureSetName(i) << " Limit " << Limit + << " Actual " << RegionPressure[i] << "\n"); RegionCriticalPSets.push_back(PressureChange(i)); } } - DEBUG(dbgs() << "Excess PSets: "; - for (const PressureChange &RCPS : RegionCriticalPSets) - dbgs() << TRI->getRegPressureSetName( - RCPS.getPSet()) << " "; - dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "Excess PSets: "; + for (const PressureChange &RCPS + : RegionCriticalPSets) dbgs() + << TRI->getRegPressureSetName(RCPS.getPSet()) << " "; + dbgs() << "\n"); } void ScheduleDAGMILive:: @@ -1098,10 +1092,11 @@ updateScheduledPressure(const SUnit *SU, } unsigned Limit = RegClassInfo->getRegPressureSetLimit(ID); if (NewMaxPressure[ID] >= Limit - 2) { - DEBUG(dbgs() << " " << TRI->getRegPressureSetName(ID) << ": " - << NewMaxPressure[ID] - << ((NewMaxPressure[ID] > Limit) ? " > " : " <= ") << Limit - << "(+ " << BotRPTracker.getLiveThru()[ID] << " livethru)\n"); + LLVM_DEBUG(dbgs() << " " << TRI->getRegPressureSetName(ID) << ": " + << NewMaxPressure[ID] + << ((NewMaxPressure[ID] > Limit) ? " > " : " <= ") + << Limit << "(+ " << BotRPTracker.getLiveThru()[ID] + << " livethru)\n"); } } } @@ -1131,17 +1126,14 @@ void ScheduleDAGMILive::updatePressureDiffs( PressureDiff &PDiff = getPressureDiff(&SU); PDiff.addPressureChange(Reg, Decrement, &MRI); - DEBUG( - dbgs() << " UpdateRegP: SU(" << SU.NodeNum << ") " - << printReg(Reg, TRI) << ':' << PrintLaneMask(P.LaneMask) - << ' ' << *SU.getInstr(); - dbgs() << " to "; - PDiff.dump(*TRI); - ); + LLVM_DEBUG(dbgs() << " UpdateRegP: SU(" << SU.NodeNum << ") " + << printReg(Reg, TRI) << ':' + << PrintLaneMask(P.LaneMask) << ' ' << *SU.getInstr(); + dbgs() << " to "; PDiff.dump(*TRI);); } } else { assert(P.LaneMask.any()); - DEBUG(dbgs() << " LiveReg: " << printVRegOrUnit(Reg, TRI) << "\n"); + LLVM_DEBUG(dbgs() << " LiveReg: " << printVRegOrUnit(Reg, TRI) << "\n"); // This may be called before CurrentBottom has been initialized. However, // BotRPTracker must have a valid position. We want the value live into the // instruction or live out of the block, so ask for the previous @@ -1169,12 +1161,9 @@ void ScheduleDAGMILive::updatePressureDiffs( if (LRQ.valueIn() == VNI) { PressureDiff &PDiff = getPressureDiff(SU); PDiff.addPressureChange(Reg, true, &MRI); - DEBUG( - dbgs() << " UpdateRegP: SU(" << SU->NodeNum << ") " - << *SU->getInstr(); - dbgs() << " to "; - PDiff.dump(*TRI); - ); + LLVM_DEBUG(dbgs() << " UpdateRegP: SU(" << SU->NodeNum << ") " + << *SU->getInstr(); + dbgs() << " to "; PDiff.dump(*TRI);); } } } @@ -1193,8 +1182,8 @@ void ScheduleDAGMILive::updatePressureDiffs( /// ScheduleDAGMILive then it will want to override this virtual method in order /// to update any specialized state. void ScheduleDAGMILive::schedule() { - DEBUG(dbgs() << "ScheduleDAGMILive::schedule starting\n"); - DEBUG(SchedImpl->dumpPolicy()); + LLVM_DEBUG(dbgs() << "ScheduleDAGMILive::schedule starting\n"); + LLVM_DEBUG(SchedImpl->dumpPolicy()); buildDAGWithRegPressure(); Topo.InitDAGTopologicalSorting(); @@ -1208,26 +1197,22 @@ void ScheduleDAGMILive::schedule() { // This may initialize a DFSResult to be used for queue priority. SchedImpl->initialize(this); - DEBUG( - if (EntrySU.getInstr() != nullptr) - EntrySU.dumpAll(this); - for (const SUnit &SU : SUnits) { - SU.dumpAll(this); - if (ShouldTrackPressure) { - dbgs() << " Pressure Diff : "; - getPressureDiff(&SU).dump(*TRI); - } - dbgs() << " Single Issue : "; - if (SchedModel.mustBeginGroup(SU.getInstr()) && - SchedModel.mustEndGroup(SU.getInstr())) - dbgs() << "true;"; - else - dbgs() << "false;"; - dbgs() << '\n'; - } - if (ExitSU.getInstr() != nullptr) - ExitSU.dumpAll(this); - ); + LLVM_DEBUG(if (EntrySU.getInstr() != nullptr) EntrySU.dumpAll(this); + for (const SUnit &SU + : SUnits) { + SU.dumpAll(this); + if (ShouldTrackPressure) { + dbgs() << " Pressure Diff : "; + getPressureDiff(&SU).dump(*TRI); + } + dbgs() << " Single Issue : "; + if (SchedModel.mustBeginGroup(SU.getInstr()) && + SchedModel.mustEndGroup(SU.getInstr())) + dbgs() << "true;"; + else + dbgs() << "false;"; + dbgs() << '\n'; + } if (ExitSU.getInstr() != nullptr) ExitSU.dumpAll(this);); if (ViewMISchedDAGs) viewGraph(); // Initialize ready queues now that the DAG and priority data are finalized. @@ -1235,7 +1220,7 @@ void ScheduleDAGMILive::schedule() { bool IsTopNode = false; while (true) { - DEBUG(dbgs() << "** ScheduleDAGMILive::schedule picking next node\n"); + LLVM_DEBUG(dbgs() << "** ScheduleDAGMILive::schedule picking next node\n"); SUnit *SU = SchedImpl->pickNode(IsTopNode); if (!SU) break; @@ -1263,7 +1248,7 @@ void ScheduleDAGMILive::schedule() { placeDebugValues(); - DEBUG({ + LLVM_DEBUG({ dbgs() << "*** Final schedule for " << printMBBReference(*begin()->getParent()) << " ***\n"; dumpSchedule(); @@ -1380,13 +1365,13 @@ unsigned ScheduleDAGMILive::computeCyclicCriticalPath() { } else CyclicLatency = 0; - DEBUG(dbgs() << "Cyclic Path: SU(" << DefSU->NodeNum << ") -> SU(" - << SU->NodeNum << ") = " << CyclicLatency << "c\n"); + LLVM_DEBUG(dbgs() << "Cyclic Path: SU(" << DefSU->NodeNum << ") -> SU(" + << SU->NodeNum << ") = " << CyclicLatency << "c\n"); if (CyclicLatency > MaxCyclicLatency) MaxCyclicLatency = CyclicLatency; } } - DEBUG(dbgs() << "Cyclic Critical Path: " << MaxCyclicLatency << "c\n"); + LLVM_DEBUG(dbgs() << "Cyclic Critical Path: " << MaxCyclicLatency << "c\n"); return MaxCyclicLatency; } @@ -1430,10 +1415,8 @@ void ScheduleDAGMILive::scheduleMI(SUnit *SU, bool IsTopNode) { TopRPTracker.advance(RegOpers); assert(TopRPTracker.getPos() == CurrentTop && "out of sync"); - DEBUG( - dbgs() << "Top Pressure:\n"; - dumpRegSetPressure(TopRPTracker.getRegSetPressureAtPos(), TRI); - ); + LLVM_DEBUG(dbgs() << "Top Pressure:\n"; dumpRegSetPressure( + TopRPTracker.getRegSetPressureAtPos(), TRI);); updateScheduledPressure(SU, TopRPTracker.getPressure().MaxSetPressure); } @@ -1469,10 +1452,8 @@ void ScheduleDAGMILive::scheduleMI(SUnit *SU, bool IsTopNode) { SmallVector<RegisterMaskPair, 8> LiveUses; BotRPTracker.recede(RegOpers, &LiveUses); assert(BotRPTracker.getPos() == CurrentBottom && "out of sync"); - DEBUG( - dbgs() << "Bottom Pressure:\n"; - dumpRegSetPressure(BotRPTracker.getRegSetPressureAtPos(), TRI); - ); + LLVM_DEBUG(dbgs() << "Bottom Pressure:\n"; dumpRegSetPressure( + BotRPTracker.getRegSetPressureAtPos(), TRI);); updateScheduledPressure(SU, BotRPTracker.getPressure().MaxSetPressure); updatePressureDiffs(LiveUses); @@ -1572,8 +1553,8 @@ void BaseMemOpClusterMutation::clusterNeighboringMemOps( *SUb->getInstr(), MemOpRecords[Idx+1].BaseReg, ClusterLength) && DAG->addEdge(SUb, SDep(SUa, SDep::Cluster))) { - DEBUG(dbgs() << "Cluster ld/st SU(" << SUa->NodeNum << ") - SU(" - << SUb->NodeNum << ")\n"); + LLVM_DEBUG(dbgs() << "Cluster ld/st SU(" << SUa->NodeNum << ") - SU(" + << SUb->NodeNum << ")\n"); // Copy successor edges from SUa to SUb. Interleaving computation // dependent on SUa can prevent load combining due to register reuse. // Predecessor edges do not need to be copied from SUb to SUa since nearby @@ -1581,7 +1562,8 @@ void BaseMemOpClusterMutation::clusterNeighboringMemOps( for (const SDep &Succ : SUa->Succs) { if (Succ.getSUnit() == SUb) continue; - DEBUG(dbgs() << " Copy Succ SU(" << Succ.getSUnit()->NodeNum << ")\n"); + LLVM_DEBUG(dbgs() << " Copy Succ SU(" << Succ.getSUnit()->NodeNum + << ")\n"); DAG->addEdge(Succ.getSUnit(), SDep(SUb, SDep::Artificial)); } ++ClusterLength; @@ -1790,18 +1772,18 @@ void CopyConstrain::constrainLocalCopy(SUnit *CopySU, ScheduleDAGMILive *DAG) { return; GlobalUses.push_back(Pred.getSUnit()); } - DEBUG(dbgs() << "Constraining copy SU(" << CopySU->NodeNum << ")\n"); + LLVM_DEBUG(dbgs() << "Constraining copy SU(" << CopySU->NodeNum << ")\n"); // Add the weak edges. for (SmallVectorImpl<SUnit*>::const_iterator I = LocalUses.begin(), E = LocalUses.end(); I != E; ++I) { - DEBUG(dbgs() << " Local use SU(" << (*I)->NodeNum << ") -> SU(" - << GlobalSU->NodeNum << ")\n"); + LLVM_DEBUG(dbgs() << " Local use SU(" << (*I)->NodeNum << ") -> SU(" + << GlobalSU->NodeNum << ")\n"); DAG->addEdge(GlobalSU, SDep(*I, SDep::Weak)); } for (SmallVectorImpl<SUnit*>::const_iterator I = GlobalUses.begin(), E = GlobalUses.end(); I != E; ++I) { - DEBUG(dbgs() << " Global use SU(" << (*I)->NodeNum << ") -> SU(" - << FirstLocalSU->NodeNum << ")\n"); + LLVM_DEBUG(dbgs() << " Global use SU(" << (*I)->NodeNum << ") -> SU(" + << FirstLocalSU->NodeNum << ")\n"); DAG->addEdge(FirstLocalSU, SDep(*I, SDep::Weak)); } } @@ -1959,16 +1941,16 @@ bool SchedBoundary::checkHazard(SUnit *SU) { unsigned uops = SchedModel->getNumMicroOps(SU->getInstr()); if ((CurrMOps > 0) && (CurrMOps + uops > SchedModel->getIssueWidth())) { - DEBUG(dbgs() << " SU(" << SU->NodeNum << ") uops=" - << SchedModel->getNumMicroOps(SU->getInstr()) << '\n'); + LLVM_DEBUG(dbgs() << " SU(" << SU->NodeNum << ") uops=" + << SchedModel->getNumMicroOps(SU->getInstr()) << '\n'); return true; } if (CurrMOps > 0 && ((isTop() && SchedModel->mustBeginGroup(SU->getInstr())) || (!isTop() && SchedModel->mustEndGroup(SU->getInstr())))) { - DEBUG(dbgs() << " hazard: SU(" << SU->NodeNum << ") must " - << (isTop()? "begin" : "end") << " group\n"); + LLVM_DEBUG(dbgs() << " hazard: SU(" << SU->NodeNum << ") must " + << (isTop() ? "begin" : "end") << " group\n"); return true; } @@ -1984,9 +1966,9 @@ bool SchedBoundary::checkHazard(SUnit *SU) { #ifndef NDEBUG MaxObservedStall = std::max(Cycles, MaxObservedStall); #endif - DEBUG(dbgs() << " SU(" << SU->NodeNum << ") " - << SchedModel->getResourceName(ResIdx) - << "=" << NRCycle << "c\n"); + LLVM_DEBUG(dbgs() << " SU(" << SU->NodeNum << ") " + << SchedModel->getResourceName(ResIdx) << "=" + << NRCycle << "c\n"); return true; } } @@ -2007,8 +1989,8 @@ findMaxLatency(ArrayRef<SUnit*> ReadySUs) { } } if (LateSU) { - DEBUG(dbgs() << Available.getName() << " RemLatency SU(" - << LateSU->NodeNum << ") " << RemLatency << "c\n"); + LLVM_DEBUG(dbgs() << Available.getName() << " RemLatency SU(" + << LateSU->NodeNum << ") " << RemLatency << "c\n"); } return RemLatency; } @@ -2024,8 +2006,8 @@ getOtherResourceCount(unsigned &OtherCritIdx) { unsigned OtherCritCount = Rem->RemIssueCount + (RetiredMOps * SchedModel->getMicroOpFactor()); - DEBUG(dbgs() << " " << Available.getName() << " + Remain MOps: " - << OtherCritCount / SchedModel->getMicroOpFactor() << '\n'); + LLVM_DEBUG(dbgs() << " " << Available.getName() << " + Remain MOps: " + << OtherCritCount / SchedModel->getMicroOpFactor() << '\n'); for (unsigned PIdx = 1, PEnd = SchedModel->getNumProcResourceKinds(); PIdx != PEnd; ++PIdx) { unsigned OtherCount = getResourceCount(PIdx) + Rem->RemainingCounts[PIdx]; @@ -2035,9 +2017,10 @@ getOtherResourceCount(unsigned &OtherCritIdx) { } } if (OtherCritIdx) { - DEBUG(dbgs() << " " << Available.getName() << " + Remain CritRes: " - << OtherCritCount / SchedModel->getResourceFactor(OtherCritIdx) - << " " << SchedModel->getResourceName(OtherCritIdx) << "\n"); + LLVM_DEBUG( + dbgs() << " " << Available.getName() << " + Remain CritRes: " + << OtherCritCount / SchedModel->getResourceFactor(OtherCritIdx) + << " " << SchedModel->getResourceName(OtherCritIdx) << "\n"); } return OtherCritCount; } @@ -2101,7 +2084,8 @@ void SchedBoundary::bumpCycle(unsigned NextCycle) { checkResourceLimit(SchedModel->getLatencyFactor(), getCriticalCount(), getScheduledLatency()); - DEBUG(dbgs() << "Cycle: " << CurrCycle << ' ' << Available.getName() << '\n'); + LLVM_DEBUG(dbgs() << "Cycle: " << CurrCycle << ' ' << Available.getName() + << '\n'); } void SchedBoundary::incExecutedResources(unsigned PIdx, unsigned Count) { @@ -2121,8 +2105,8 @@ unsigned SchedBoundary:: countResource(unsigned PIdx, unsigned Cycles, unsigned NextCycle) { unsigned Factor = SchedModel->getResourceFactor(PIdx); unsigned Count = Factor * Cycles; - DEBUG(dbgs() << " " << SchedModel->getResourceName(PIdx) - << " +" << Cycles << "x" << Factor << "u\n"); + LLVM_DEBUG(dbgs() << " " << SchedModel->getResourceName(PIdx) << " +" + << Cycles << "x" << Factor << "u\n"); // Update Executed resources counts. incExecutedResources(PIdx, Count); @@ -2133,16 +2117,17 @@ countResource(unsigned PIdx, unsigned Cycles, unsigned NextCycle) { // becomes the critical resource. if (ZoneCritResIdx != PIdx && (getResourceCount(PIdx) > getCriticalCount())) { ZoneCritResIdx = PIdx; - DEBUG(dbgs() << " *** Critical resource " - << SchedModel->getResourceName(PIdx) << ": " - << getResourceCount(PIdx) / SchedModel->getLatencyFactor() << "c\n"); + LLVM_DEBUG(dbgs() << " *** Critical resource " + << SchedModel->getResourceName(PIdx) << ": " + << getResourceCount(PIdx) / SchedModel->getLatencyFactor() + << "c\n"); } // For reserved resources, record the highest cycle using the resource. unsigned NextAvailable = getNextResourceCycle(PIdx, Cycles); if (NextAvailable > CurrCycle) { - DEBUG(dbgs() << " Resource conflict: " - << SchedModel->getProcResource(PIdx)->Name << " reserved until @" - << NextAvailable << "\n"); + LLVM_DEBUG(dbgs() << " Resource conflict: " + << SchedModel->getProcResource(PIdx)->Name + << " reserved until @" << NextAvailable << "\n"); } return NextAvailable; } @@ -2167,7 +2152,7 @@ void SchedBoundary::bumpNode(SUnit *SU) { "Cannot schedule this instruction's MicroOps in the current cycle."); unsigned ReadyCycle = (isTop() ? SU->TopReadyCycle : SU->BotReadyCycle); - DEBUG(dbgs() << " Ready @" << ReadyCycle << "c\n"); + LLVM_DEBUG(dbgs() << " Ready @" << ReadyCycle << "c\n"); unsigned NextCycle = CurrCycle; switch (SchedModel->getMicroOpBufferSize()) { @@ -2177,7 +2162,7 @@ void SchedBoundary::bumpNode(SUnit *SU) { case 1: if (ReadyCycle > NextCycle) { NextCycle = ReadyCycle; - DEBUG(dbgs() << " *** Stall until: " << ReadyCycle << "\n"); + LLVM_DEBUG(dbgs() << " *** Stall until: " << ReadyCycle << "\n"); } break; default: @@ -2206,8 +2191,9 @@ void SchedBoundary::bumpNode(SUnit *SU) { if ((int)(ScaledMOps - getResourceCount(ZoneCritResIdx)) >= (int)SchedModel->getLatencyFactor()) { ZoneCritResIdx = 0; - DEBUG(dbgs() << " *** Critical resource NumMicroOps: " - << ScaledMOps / SchedModel->getLatencyFactor() << "c\n"); + LLVM_DEBUG(dbgs() << " *** Critical resource NumMicroOps: " + << ScaledMOps / SchedModel->getLatencyFactor() + << "c\n"); } } for (TargetSchedModel::ProcResIter @@ -2243,13 +2229,13 @@ void SchedBoundary::bumpNode(SUnit *SU) { unsigned &BotLatency = isTop() ? DependentLatency : ExpectedLatency; if (SU->getDepth() > TopLatency) { TopLatency = SU->getDepth(); - DEBUG(dbgs() << " " << Available.getName() - << " TopLatency SU(" << SU->NodeNum << ") " << TopLatency << "c\n"); + LLVM_DEBUG(dbgs() << " " << Available.getName() << " TopLatency SU(" + << SU->NodeNum << ") " << TopLatency << "c\n"); } if (SU->getHeight() > BotLatency) { BotLatency = SU->getHeight(); - DEBUG(dbgs() << " " << Available.getName() - << " BotLatency SU(" << SU->NodeNum << ") " << BotLatency << "c\n"); + LLVM_DEBUG(dbgs() << " " << Available.getName() << " BotLatency SU(" + << SU->NodeNum << ") " << BotLatency << "c\n"); } // If we stall for any reason, bump the cycle. if (NextCycle > CurrCycle) @@ -2273,17 +2259,17 @@ void SchedBoundary::bumpNode(SUnit *SU) { // currCycle to X. if ((isTop() && SchedModel->mustEndGroup(SU->getInstr())) || (!isTop() && SchedModel->mustBeginGroup(SU->getInstr()))) { - DEBUG(dbgs() << " Bump cycle to " - << (isTop() ? "end" : "begin") << " group\n"); + LLVM_DEBUG(dbgs() << " Bump cycle to " << (isTop() ? "end" : "begin") + << " group\n"); bumpCycle(++NextCycle); } while (CurrMOps >= SchedModel->getIssueWidth()) { - DEBUG(dbgs() << " *** Max MOps " << CurrMOps - << " at cycle " << CurrCycle << '\n'); + LLVM_DEBUG(dbgs() << " *** Max MOps " << CurrMOps << " at cycle " + << CurrCycle << '\n'); bumpCycle(++NextCycle); } - DEBUG(dumpScheduledState()); + LLVM_DEBUG(dumpScheduledState()); } /// Release pending ready nodes in to the available queue. This makes them @@ -2356,8 +2342,8 @@ SUnit *SchedBoundary::pickOnlyChoice() { releasePending(); } - DEBUG(Pending.dump()); - DEBUG(Available.dump()); + LLVM_DEBUG(Pending.dump()); + LLVM_DEBUG(Available.dump()); if (Available.size() == 1) return *Available.begin(); @@ -2455,27 +2441,24 @@ void GenericSchedulerBase::setPolicy(CandPolicy &Policy, bool IsPostRA, if (!OtherResLimited) { if (IsPostRA || (RemLatency + CurrZone.getCurrCycle() > Rem.CriticalPath)) { Policy.ReduceLatency |= true; - DEBUG(dbgs() << " " << CurrZone.Available.getName() - << " RemainingLatency " << RemLatency << " + " - << CurrZone.getCurrCycle() << "c > CritPath " - << Rem.CriticalPath << "\n"); + LLVM_DEBUG(dbgs() << " " << CurrZone.Available.getName() + << " RemainingLatency " << RemLatency << " + " + << CurrZone.getCurrCycle() << "c > CritPath " + << Rem.CriticalPath << "\n"); } } // If the same resource is limiting inside and outside the zone, do nothing. if (CurrZone.getZoneCritResIdx() == OtherCritIdx) return; - DEBUG( - if (CurrZone.isResourceLimited()) { - dbgs() << " " << CurrZone.Available.getName() << " ResourceLimited: " - << SchedModel->getResourceName(CurrZone.getZoneCritResIdx()) - << "\n"; - } - if (OtherResLimited) - dbgs() << " RemainingLimit: " - << SchedModel->getResourceName(OtherCritIdx) << "\n"; - if (!CurrZone.isResourceLimited() && !OtherResLimited) - dbgs() << " Latency limited both directions.\n"); + LLVM_DEBUG(if (CurrZone.isResourceLimited()) { + dbgs() << " " << CurrZone.Available.getName() << " ResourceLimited: " + << SchedModel->getResourceName(CurrZone.getZoneCritResIdx()) << "\n"; + } if (OtherResLimited) dbgs() + << " RemainingLimit: " + << SchedModel->getResourceName(OtherCritIdx) << "\n"; + if (!CurrZone.isResourceLimited() && !OtherResLimited) dbgs() + << " Latency limited both directions.\n"); if (CurrZone.isResourceLimited() && !Policy.ReduceResIdx) Policy.ReduceResIdx = CurrZone.getZoneCritResIdx(); @@ -2623,8 +2606,8 @@ bool tryLatency(GenericSchedulerBase::SchedCandidate &TryCand, } // end namespace llvm static void tracePick(GenericSchedulerBase::CandReason Reason, bool IsTop) { - DEBUG(dbgs() << "Pick " << (IsTop ? "Top " : "Bot ") - << GenericSchedulerBase::getReasonStr(Reason) << '\n'); + LLVM_DEBUG(dbgs() << "Pick " << (IsTop ? "Top " : "Bot ") + << GenericSchedulerBase::getReasonStr(Reason) << '\n'); } static void tracePick(const GenericSchedulerBase::SchedCandidate &Cand) { @@ -2746,14 +2729,14 @@ void GenericScheduler::checkAcyclicLatency() { Rem.IsAcyclicLatencyLimited = InFlightCount > BufferLimit; - DEBUG(dbgs() << "IssueCycles=" - << Rem.RemIssueCount / SchedModel->getLatencyFactor() << "c " - << "IterCycles=" << IterCount / SchedModel->getLatencyFactor() - << "c NumIters=" << (AcyclicCount + IterCount-1) / IterCount - << " InFlight=" << InFlightCount / SchedModel->getMicroOpFactor() - << "m BufferLim=" << SchedModel->getMicroOpBufferSize() << "m\n"; - if (Rem.IsAcyclicLatencyLimited) - dbgs() << " ACYCLIC LATENCY LIMIT\n"); + LLVM_DEBUG( + dbgs() << "IssueCycles=" + << Rem.RemIssueCount / SchedModel->getLatencyFactor() << "c " + << "IterCycles=" << IterCount / SchedModel->getLatencyFactor() + << "c NumIters=" << (AcyclicCount + IterCount - 1) / IterCount + << " InFlight=" << InFlightCount / SchedModel->getMicroOpFactor() + << "m BufferLim=" << SchedModel->getMicroOpBufferSize() << "m\n"; + if (Rem.IsAcyclicLatencyLimited) dbgs() << " ACYCLIC LATENCY LIMIT\n"); } void GenericScheduler::registerRoots() { @@ -2764,7 +2747,7 @@ void GenericScheduler::registerRoots() { if (SU->getDepth() > Rem.CriticalPath) Rem.CriticalPath = SU->getDepth(); } - DEBUG(dbgs() << "Critical Path(GS-RR ): " << Rem.CriticalPath << '\n'); + LLVM_DEBUG(dbgs() << "Critical Path(GS-RR ): " << Rem.CriticalPath << '\n'); if (DumpCriticalPathLength) { errs() << "Critical Path(GS-RR ): " << Rem.CriticalPath << " \n"; } @@ -2879,10 +2862,10 @@ void GenericScheduler::initCandidate(SchedCandidate &Cand, SUnit *SU, } } } - DEBUG(if (Cand.RPDelta.Excess.isValid()) - dbgs() << " Try SU(" << Cand.SU->NodeNum << ") " - << TRI->getRegPressureSetName(Cand.RPDelta.Excess.getPSet()) - << ":" << Cand.RPDelta.Excess.getUnitInc() << "\n"); + LLVM_DEBUG(if (Cand.RPDelta.Excess.isValid()) dbgs() + << " Try SU(" << Cand.SU->NodeNum << ") " + << TRI->getRegPressureSetName(Cand.RPDelta.Excess.getPSet()) << ":" + << Cand.RPDelta.Excess.getUnitInc() << "\n"); } /// Apply a set of heursitics to a new candidate. Heuristics are currently @@ -3023,7 +3006,7 @@ void GenericScheduler::pickNodeFromQueue(SchedBoundary &Zone, if (TryCand.ResDelta == SchedResourceDelta()) TryCand.initResourceDelta(DAG, SchedModel); Cand.setBest(TryCand); - DEBUG(traceCandidate(Cand)); + LLVM_DEBUG(traceCandidate(Cand)); } } } @@ -3052,14 +3035,14 @@ SUnit *GenericScheduler::pickNodeBidirectional(bool &IsTopNode) { setPolicy(TopPolicy, /*IsPostRA=*/false, Top, &Bot); // See if BotCand is still valid (because we previously scheduled from Top). - DEBUG(dbgs() << "Picking from Bot:\n"); + LLVM_DEBUG(dbgs() << "Picking from Bot:\n"); if (!BotCand.isValid() || BotCand.SU->isScheduled || BotCand.Policy != BotPolicy) { BotCand.reset(CandPolicy()); pickNodeFromQueue(Bot, BotPolicy, DAG->getBotRPTracker(), BotCand); assert(BotCand.Reason != NoCand && "failed to find the first candidate"); } else { - DEBUG(traceCandidate(BotCand)); + LLVM_DEBUG(traceCandidate(BotCand)); #ifndef NDEBUG if (VerifyScheduling) { SchedCandidate TCand; @@ -3072,14 +3055,14 @@ SUnit *GenericScheduler::pickNodeBidirectional(bool &IsTopNode) { } // Check if the top Q has a better candidate. - DEBUG(dbgs() << "Picking from Top:\n"); + LLVM_DEBUG(dbgs() << "Picking from Top:\n"); if (!TopCand.isValid() || TopCand.SU->isScheduled || TopCand.Policy != TopPolicy) { TopCand.reset(CandPolicy()); pickNodeFromQueue(Top, TopPolicy, DAG->getTopRPTracker(), TopCand); assert(TopCand.Reason != NoCand && "failed to find the first candidate"); } else { - DEBUG(traceCandidate(TopCand)); + LLVM_DEBUG(traceCandidate(TopCand)); #ifndef NDEBUG if (VerifyScheduling) { SchedCandidate TCand; @@ -3099,7 +3082,7 @@ SUnit *GenericScheduler::pickNodeBidirectional(bool &IsTopNode) { tryCandidate(Cand, TopCand, nullptr); if (TopCand.Reason != NoCand) { Cand.setBest(TopCand); - DEBUG(traceCandidate(Cand)); + LLVM_DEBUG(traceCandidate(Cand)); } IsTopNode = Cand.AtTop; @@ -3148,7 +3131,8 @@ SUnit *GenericScheduler::pickNode(bool &IsTopNode) { if (SU->isBottomReady()) Bot.removeReady(SU); - DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") " << *SU->getInstr()); + LLVM_DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") " + << *SU->getInstr()); return SU; } @@ -3169,8 +3153,8 @@ void GenericScheduler::reschedulePhysRegCopies(SUnit *SU, bool isTop) { MachineInstr *Copy = DepSU->getInstr(); if (!Copy->isCopy()) continue; - DEBUG(dbgs() << " Rescheduling physreg copy "; - Dep.getSUnit()->dump(DAG)); + LLVM_DEBUG(dbgs() << " Rescheduling physreg copy "; + Dep.getSUnit()->dump(DAG)); DAG->moveInstruction(Copy, InsertPos); } } @@ -3249,7 +3233,7 @@ void PostGenericScheduler::registerRoots() { if (SU->getDepth() > Rem.CriticalPath) Rem.CriticalPath = SU->getDepth(); } - DEBUG(dbgs() << "Critical Path: (PGS-RR) " << Rem.CriticalPath << '\n'); + LLVM_DEBUG(dbgs() << "Critical Path: (PGS-RR) " << Rem.CriticalPath << '\n'); if (DumpCriticalPathLength) { errs() << "Critical Path(PGS-RR ): " << Rem.CriticalPath << " \n"; } @@ -3307,7 +3291,7 @@ void PostGenericScheduler::pickNodeFromQueue(SchedCandidate &Cand) { tryCandidate(Cand, TryCand); if (TryCand.Reason != NoCand) { Cand.setBest(TryCand); - DEBUG(traceCandidate(Cand)); + LLVM_DEBUG(traceCandidate(Cand)); } } } @@ -3339,7 +3323,8 @@ SUnit *PostGenericScheduler::pickNode(bool &IsTopNode) { IsTopNode = true; Top.removeReady(SU); - DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") " << *SU->getInstr()); + LLVM_DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") " + << *SU->getInstr()); return SU; } @@ -3428,12 +3413,15 @@ public: SUnit *SU = ReadyQ.back(); ReadyQ.pop_back(); IsTopNode = false; - DEBUG(dbgs() << "Pick node " << "SU(" << SU->NodeNum << ") " - << " ILP: " << DAG->getDFSResult()->getILP(SU) - << " Tree: " << DAG->getDFSResult()->getSubtreeID(SU) << " @" - << DAG->getDFSResult()->getSubtreeLevel( - DAG->getDFSResult()->getSubtreeID(SU)) << '\n' - << "Scheduling " << *SU->getInstr()); + LLVM_DEBUG(dbgs() << "Pick node " + << "SU(" << SU->NodeNum << ") " + << " ILP: " << DAG->getDFSResult()->getILP(SU) + << " Tree: " << DAG->getDFSResult()->getSubtreeID(SU) + << " @" + << DAG->getDFSResult()->getSubtreeLevel( + DAG->getDFSResult()->getSubtreeID(SU)) + << '\n' + << "Scheduling " << *SU->getInstr()); return SU; } diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp index 0d43b10cc84..c09539d9903 100644 --- a/llvm/lib/CodeGen/MachineSink.cpp +++ b/llvm/lib/CodeGen/MachineSink.cpp @@ -211,8 +211,8 @@ bool MachineSinking::PerformTrivialForwardCoalescing(MachineInstr &MI, MachineInstr *DefMI = MRI->getVRegDef(SrcReg); if (DefMI->isCopyLike()) return false; - DEBUG(dbgs() << "Coalescing: " << *DefMI); - DEBUG(dbgs() << "*** to: " << MI); + LLVM_DEBUG(dbgs() << "Coalescing: " << *DefMI); + LLVM_DEBUG(dbgs() << "*** to: " << MI); MRI->replaceRegWith(DstReg, SrcReg); MI.eraseFromParent(); @@ -296,7 +296,7 @@ bool MachineSinking::runOnMachineFunction(MachineFunction &MF) { if (skipFunction(MF.getFunction())) return false; - DEBUG(dbgs() << "******** Machine Sinking ********\n"); + LLVM_DEBUG(dbgs() << "******** Machine Sinking ********\n"); TII = MF.getSubtarget().getInstrInfo(); TRI = MF.getSubtarget().getRegisterInfo(); @@ -323,14 +323,14 @@ bool MachineSinking::runOnMachineFunction(MachineFunction &MF) { for (auto &Pair : ToSplit) { auto NewSucc = Pair.first->SplitCriticalEdge(Pair.second, *this); if (NewSucc != nullptr) { - DEBUG(dbgs() << " *** Splitting critical edge: " - << printMBBReference(*Pair.first) << " -- " - << printMBBReference(*NewSucc) << " -- " - << printMBBReference(*Pair.second) << '\n'); + LLVM_DEBUG(dbgs() << " *** Splitting critical edge: " + << printMBBReference(*Pair.first) << " -- " + << printMBBReference(*NewSucc) << " -- " + << printMBBReference(*Pair.second) << '\n'); MadeChange = true; ++NumSplit; } else - DEBUG(dbgs() << " *** Not legal to break critical edge\n"); + LLVM_DEBUG(dbgs() << " *** Not legal to break critical edge\n"); } // If this iteration over the code changed anything, keep iterating. if (!MadeChange) break; @@ -804,7 +804,7 @@ bool MachineSinking::SinkInstruction(MachineInstr &MI, bool &SawStore, return false; } - DEBUG(dbgs() << "Sink instr " << MI << "\tinto block " << *SuccToSinkTo); + LLVM_DEBUG(dbgs() << "Sink instr " << MI << "\tinto block " << *SuccToSinkTo); // If the block has multiple predecessors, this is a critical edge. // Decide if we can sink along it or need to break the edge. @@ -814,26 +814,26 @@ bool MachineSinking::SinkInstruction(MachineInstr &MI, bool &SawStore, bool TryBreak = false; bool store = true; if (!MI.isSafeToMove(AA, store)) { - DEBUG(dbgs() << " *** NOTE: Won't sink load along critical edge.\n"); + LLVM_DEBUG(dbgs() << " *** NOTE: Won't sink load along critical edge.\n"); TryBreak = true; } // We don't want to sink across a critical edge if we don't dominate the // successor. We could be introducing calculations to new code paths. if (!TryBreak && !DT->dominates(ParentBlock, SuccToSinkTo)) { - DEBUG(dbgs() << " *** NOTE: Critical edge found\n"); + LLVM_DEBUG(dbgs() << " *** NOTE: Critical edge found\n"); TryBreak = true; } // Don't sink instructions into a loop. if (!TryBreak && LI->isLoopHeader(SuccToSinkTo)) { - DEBUG(dbgs() << " *** NOTE: Loop header found\n"); + LLVM_DEBUG(dbgs() << " *** NOTE: Loop header found\n"); TryBreak = true; } // Otherwise we are OK with sinking along a critical edge. if (!TryBreak) - DEBUG(dbgs() << "Sinking along critical edge.\n"); + LLVM_DEBUG(dbgs() << "Sinking along critical edge.\n"); else { // Mark this edge as to be split. // If the edge can actually be split, the next iteration of the main loop @@ -841,8 +841,8 @@ bool MachineSinking::SinkInstruction(MachineInstr &MI, bool &SawStore, bool Status = PostponeSplitCriticalEdge(MI, ParentBlock, SuccToSinkTo, BreakPHIEdge); if (!Status) - DEBUG(dbgs() << " *** PUNTING: Not legal or profitable to " - "break critical edge\n"); + LLVM_DEBUG(dbgs() << " *** PUNTING: Not legal or profitable to " + "break critical edge\n"); // The instruction will not be sunk this time. return false; } @@ -855,8 +855,8 @@ bool MachineSinking::SinkInstruction(MachineInstr &MI, bool &SawStore, bool Status = PostponeSplitCriticalEdge(MI, ParentBlock, SuccToSinkTo, BreakPHIEdge); if (!Status) - DEBUG(dbgs() << " *** PUNTING: Not legal or profitable to " - "break critical edge\n"); + LLVM_DEBUG(dbgs() << " *** PUNTING: Not legal or profitable to " + "break critical edge\n"); // The instruction will not be sunk this time. return false; } diff --git a/llvm/lib/CodeGen/MachineTraceMetrics.cpp b/llvm/lib/CodeGen/MachineTraceMetrics.cpp index f4aebca3f47..b444cd31eba 100644 --- a/llvm/lib/CodeGen/MachineTraceMetrics.cpp +++ b/llvm/lib/CodeGen/MachineTraceMetrics.cpp @@ -396,8 +396,8 @@ MachineTraceMetrics::getEnsemble(MachineTraceMetrics::Strategy strategy) { } void MachineTraceMetrics::invalidate(const MachineBasicBlock *MBB) { - DEBUG(dbgs() << "Invalidate traces through " << printMBBReference(*MBB) - << '\n'); + LLVM_DEBUG(dbgs() << "Invalidate traces through " << printMBBReference(*MBB) + << '\n'); BlockInfo[MBB->getNumber()].invalidate(); for (unsigned i = 0; i != TS_NumStrategies; ++i) if (Ensembles[i]) @@ -477,8 +477,8 @@ public: /// Compute the trace through MBB. void MachineTraceMetrics::Ensemble::computeTrace(const MachineBasicBlock *MBB) { - DEBUG(dbgs() << "Computing " << getName() << " trace through " - << printMBBReference(*MBB) << '\n'); + LLVM_DEBUG(dbgs() << "Computing " << getName() << " trace through " + << printMBBReference(*MBB) << '\n'); // Set up loop bounds for the backwards post-order traversal. LoopBounds Bounds(BlockInfo, MTM.Loops); @@ -486,11 +486,11 @@ void MachineTraceMetrics::Ensemble::computeTrace(const MachineBasicBlock *MBB) { Bounds.Downward = false; Bounds.Visited.clear(); for (auto I : inverse_post_order_ext(MBB, Bounds)) { - DEBUG(dbgs() << " pred for " << printMBBReference(*I) << ": "); + LLVM_DEBUG(dbgs() << " pred for " << printMBBReference(*I) << ": "); TraceBlockInfo &TBI = BlockInfo[I->getNumber()]; // All the predecessors have been visited, pick the preferred one. TBI.Pred = pickTracePred(I); - DEBUG({ + LLVM_DEBUG({ if (TBI.Pred) dbgs() << printMBBReference(*TBI.Pred) << '\n'; else @@ -504,11 +504,11 @@ void MachineTraceMetrics::Ensemble::computeTrace(const MachineBasicBlock *MBB) { Bounds.Downward = true; Bounds.Visited.clear(); for (auto I : post_order_ext(MBB, Bounds)) { - DEBUG(dbgs() << " succ for " << printMBBReference(*I) << ": "); + LLVM_DEBUG(dbgs() << " succ for " << printMBBReference(*I) << ": "); TraceBlockInfo &TBI = BlockInfo[I->getNumber()]; // All the successors have been visited, pick the preferred one. TBI.Succ = pickTraceSucc(I); - DEBUG({ + LLVM_DEBUG({ if (TBI.Succ) dbgs() << printMBBReference(*TBI.Succ) << '\n'; else @@ -531,8 +531,8 @@ MachineTraceMetrics::Ensemble::invalidate(const MachineBasicBlock *BadMBB) { WorkList.push_back(BadMBB); do { const MachineBasicBlock *MBB = WorkList.pop_back_val(); - DEBUG(dbgs() << "Invalidate " << printMBBReference(*MBB) << ' ' - << getName() << " height.\n"); + LLVM_DEBUG(dbgs() << "Invalidate " << printMBBReference(*MBB) << ' ' + << getName() << " height.\n"); // Find any MBB predecessors that have MBB as their preferred successor. // They are the only ones that need to be invalidated. for (const MachineBasicBlock *Pred : MBB->predecessors()) { @@ -556,8 +556,8 @@ MachineTraceMetrics::Ensemble::invalidate(const MachineBasicBlock *BadMBB) { WorkList.push_back(BadMBB); do { const MachineBasicBlock *MBB = WorkList.pop_back_val(); - DEBUG(dbgs() << "Invalidate " << printMBBReference(*MBB) << ' ' - << getName() << " depth.\n"); + LLVM_DEBUG(dbgs() << "Invalidate " << printMBBReference(*MBB) << ' ' + << getName() << " depth.\n"); // Find any MBB successors that have MBB as their preferred predecessor. // They are the only ones that need to be invalidated. for (const MachineBasicBlock *Succ : MBB->successors()) { @@ -813,9 +813,9 @@ updateDepth(MachineTraceMetrics::TraceBlockInfo &TBI, const MachineInstr &UseMI, if (TBI.HasValidInstrHeights) { // Update critical path length. TBI.CriticalPath = std::max(TBI.CriticalPath, Cycle + MICycles.Height); - DEBUG(dbgs() << TBI.CriticalPath << '\t' << Cycle << '\t' << UseMI); + LLVM_DEBUG(dbgs() << TBI.CriticalPath << '\t' << Cycle << '\t' << UseMI); } else { - DEBUG(dbgs() << Cycle << '\t' << UseMI); + LLVM_DEBUG(dbgs() << Cycle << '\t' << UseMI); } } @@ -860,13 +860,13 @@ computeInstrDepths(const MachineBasicBlock *MBB) { // Go through trace blocks in top-down order, stopping after the center block. while (!Stack.empty()) { MBB = Stack.pop_back_val(); - DEBUG(dbgs() << "\nDepths for " << printMBBReference(*MBB) << ":\n"); + LLVM_DEBUG(dbgs() << "\nDepths for " << printMBBReference(*MBB) << ":\n"); TraceBlockInfo &TBI = BlockInfo[MBB->getNumber()]; TBI.HasValidInstrDepths = true; TBI.CriticalPath = 0; // Print out resource depths here as well. - DEBUG({ + LLVM_DEBUG({ dbgs() << format("%7u Instructions\n", TBI.InstrDepth); ArrayRef<unsigned> PRDepths = getProcResourceDepths(MBB->getNumber()); for (unsigned K = 0; K != PRDepths.size(); ++K) @@ -1045,12 +1045,12 @@ computeInstrHeights(const MachineBasicBlock *MBB) { SmallVector<DataDep, 8> Deps; for (;!Stack.empty(); Stack.pop_back()) { MBB = Stack.back(); - DEBUG(dbgs() << "Heights for " << printMBBReference(*MBB) << ":\n"); + LLVM_DEBUG(dbgs() << "Heights for " << printMBBReference(*MBB) << ":\n"); TraceBlockInfo &TBI = BlockInfo[MBB->getNumber()]; TBI.HasValidInstrHeights = true; TBI.CriticalPath = 0; - DEBUG({ + LLVM_DEBUG({ dbgs() << format("%7u Instructions\n", TBI.InstrHeight); ArrayRef<unsigned> PRHeights = getProcResourceHeights(MBB->getNumber()); for (unsigned K = 0; K != PRHeights.size(); ++K) @@ -1081,7 +1081,7 @@ computeInstrHeights(const MachineBasicBlock *MBB) { if (!Deps.empty()) { // Loop header PHI heights are all 0. unsigned Height = TBI.Succ ? Cycles.lookup(&PHI).Height : 0; - DEBUG(dbgs() << "pred\t" << Height << '\t' << PHI); + LLVM_DEBUG(dbgs() << "pred\t" << Height << '\t' << PHI); if (pushDepHeight(Deps.front(), PHI, Height, Heights, MTM.SchedModel, MTM.TII)) addLiveIns(Deps.front().DefMI, Deps.front().DefOp, Stack); @@ -1122,38 +1122,38 @@ computeInstrHeights(const MachineBasicBlock *MBB) { InstrCycles &MICycles = Cycles[&MI]; MICycles.Height = Cycle; if (!TBI.HasValidInstrDepths) { - DEBUG(dbgs() << Cycle << '\t' << MI); + LLVM_DEBUG(dbgs() << Cycle << '\t' << MI); continue; } // Update critical path length. TBI.CriticalPath = std::max(TBI.CriticalPath, Cycle + MICycles.Depth); - DEBUG(dbgs() << TBI.CriticalPath << '\t' << Cycle << '\t' << MI); + LLVM_DEBUG(dbgs() << TBI.CriticalPath << '\t' << Cycle << '\t' << MI); } // Update virtual live-in heights. They were added by addLiveIns() with a 0 // height because the final height isn't known until now. - DEBUG(dbgs() << printMBBReference(*MBB) << " Live-ins:"); + LLVM_DEBUG(dbgs() << printMBBReference(*MBB) << " Live-ins:"); for (LiveInReg &LIR : TBI.LiveIns) { const MachineInstr *DefMI = MTM.MRI->getVRegDef(LIR.Reg); LIR.Height = Heights.lookup(DefMI); - DEBUG(dbgs() << ' ' << printReg(LIR.Reg) << '@' << LIR.Height); + LLVM_DEBUG(dbgs() << ' ' << printReg(LIR.Reg) << '@' << LIR.Height); } // Transfer the live regunits to the live-in list. for (SparseSet<LiveRegUnit>::const_iterator RI = RegUnits.begin(), RE = RegUnits.end(); RI != RE; ++RI) { TBI.LiveIns.push_back(LiveInReg(RI->RegUnit, RI->Cycle)); - DEBUG(dbgs() << ' ' << printRegUnit(RI->RegUnit, MTM.TRI) - << '@' << RI->Cycle); + LLVM_DEBUG(dbgs() << ' ' << printRegUnit(RI->RegUnit, MTM.TRI) << '@' + << RI->Cycle); } - DEBUG(dbgs() << '\n'); + LLVM_DEBUG(dbgs() << '\n'); if (!TBI.HasValidInstrDepths) continue; // Add live-ins to the critical path length. TBI.CriticalPath = std::max(TBI.CriticalPath, computeCrossBlockCriticalPath(TBI)); - DEBUG(dbgs() << "Critical path: " << TBI.CriticalPath << '\n'); + LLVM_DEBUG(dbgs() << "Critical path: " << TBI.CriticalPath << '\n'); } } diff --git a/llvm/lib/CodeGen/MacroFusion.cpp b/llvm/lib/CodeGen/MacroFusion.cpp index 5b3523be635..2df72d83aaf 100644 --- a/llvm/lib/CodeGen/MacroFusion.cpp +++ b/llvm/lib/CodeGen/MacroFusion.cpp @@ -66,11 +66,11 @@ static bool fuseInstructionPair(ScheduleDAGMI &DAG, SUnit &FirstSU, if (SI.getSUnit() == &FirstSU) SI.setLatency(0); - DEBUG(dbgs() << "Macro fuse: "; - FirstSU.print(dbgs(), &DAG); dbgs() << " - "; - SecondSU.print(dbgs(), &DAG); dbgs() << " / "; - dbgs() << DAG.TII->getName(FirstSU.getInstr()->getOpcode()) << " - " << - DAG.TII->getName(SecondSU.getInstr()->getOpcode()) << '\n'; ); + LLVM_DEBUG( + dbgs() << "Macro fuse: "; FirstSU.print(dbgs(), &DAG); dbgs() << " - "; + SecondSU.print(dbgs(), &DAG); dbgs() << " / "; + dbgs() << DAG.TII->getName(FirstSU.getInstr()->getOpcode()) << " - " + << DAG.TII->getName(SecondSU.getInstr()->getOpcode()) << '\n';); // Make data dependencies from the FirstSU also dependent on the SecondSU to // prevent them from being scheduled between the FirstSU and the SecondSU. @@ -80,9 +80,8 @@ static bool fuseInstructionPair(ScheduleDAGMI &DAG, SUnit &FirstSU, if (SI.isWeak() || isHazard(SI) || SU == &DAG.ExitSU || SU == &SecondSU || SU->isPred(&SecondSU)) continue; - DEBUG(dbgs() << " Bind "; - SecondSU.print(dbgs(), &DAG); dbgs() << " - "; - SU->print(dbgs(), &DAG); dbgs() << '\n';); + LLVM_DEBUG(dbgs() << " Bind "; SecondSU.print(dbgs(), &DAG); + dbgs() << " - "; SU->print(dbgs(), &DAG); dbgs() << '\n';); DAG.addEdge(SU, SDep(&SecondSU, SDep::Artificial)); } @@ -93,9 +92,8 @@ static bool fuseInstructionPair(ScheduleDAGMI &DAG, SUnit &FirstSU, SUnit *SU = SI.getSUnit(); if (SI.isWeak() || isHazard(SI) || &FirstSU == SU || FirstSU.isSucc(SU)) continue; - DEBUG(dbgs() << " Bind "; - SU->print(dbgs(), &DAG); dbgs() << " - "; - FirstSU.print(dbgs(), &DAG); dbgs() << '\n';); + LLVM_DEBUG(dbgs() << " Bind "; SU->print(dbgs(), &DAG); dbgs() << " - "; + FirstSU.print(dbgs(), &DAG); dbgs() << '\n';); DAG.addEdge(&FirstSU, SDep(SU, SDep::Artificial)); } diff --git a/llvm/lib/CodeGen/PHIElimination.cpp b/llvm/lib/CodeGen/PHIElimination.cpp index 6a73708b9a8..b7a5a6d4755 100644 --- a/llvm/lib/CodeGen/PHIElimination.cpp +++ b/llvm/lib/CodeGen/PHIElimination.cpp @@ -270,7 +270,8 @@ void PHIElimination::LowerPHINode(MachineBasicBlock &MBB, IncomingReg = entry; reusedIncoming = true; ++NumReused; - DEBUG(dbgs() << "Reusing " << printReg(IncomingReg) << " for " << *MPhi); + LLVM_DEBUG(dbgs() << "Reusing " << printReg(IncomingReg) << " for " + << *MPhi); } else { const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg); entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC); @@ -295,9 +296,9 @@ void PHIElimination::LowerPHINode(MachineBasicBlock &MBB, // AfterPHIsIt, so it appears before the current PHICopy. if (reusedIncoming) if (MachineInstr *OldKill = VI.findKill(&MBB)) { - DEBUG(dbgs() << "Remove old kill from " << *OldKill); + LLVM_DEBUG(dbgs() << "Remove old kill from " << *OldKill); LV->removeVirtualRegisterKilled(IncomingReg, *OldKill); - DEBUG(MBB.dump()); + LLVM_DEBUG(MBB.dump()); } // Add information to LiveVariables to know that the incoming value is @@ -593,9 +594,9 @@ bool PHIElimination::SplitPHIEdges(MachineFunction &MF, if (!ShouldSplit && !NoPhiElimLiveOutEarlyExit) continue; if (ShouldSplit) { - DEBUG(dbgs() << printReg(Reg) << " live-out before critical edge " - << printMBBReference(*PreMBB) << " -> " - << printMBBReference(MBB) << ": " << *BBI); + LLVM_DEBUG(dbgs() << printReg(Reg) << " live-out before critical edge " + << printMBBReference(*PreMBB) << " -> " + << printMBBReference(MBB) << ": " << *BBI); } // If Reg is not live-in to MBB, it means it must be live-in to some @@ -610,10 +611,12 @@ bool PHIElimination::SplitPHIEdges(MachineFunction &MF, // Check for a loop exiting edge. if (!ShouldSplit && CurLoop != PreLoop) { - DEBUG({ + LLVM_DEBUG({ dbgs() << "Split wouldn't help, maybe avoid loop copies?\n"; - if (PreLoop) dbgs() << "PreLoop: " << *PreLoop; - if (CurLoop) dbgs() << "CurLoop: " << *CurLoop; + if (PreLoop) + dbgs() << "PreLoop: " << *PreLoop; + if (CurLoop) + dbgs() << "CurLoop: " << *CurLoop; }); // This edge could be entering a loop, exiting a loop, or it could be // both: Jumping directly form one loop to the header of a sibling @@ -624,7 +627,7 @@ bool PHIElimination::SplitPHIEdges(MachineFunction &MF, if (!ShouldSplit && !SplitAllCriticalEdges) continue; if (!PreMBB->SplitCriticalEdge(&MBB, *this)) { - DEBUG(dbgs() << "Failed to split critical edge.\n"); + LLVM_DEBUG(dbgs() << "Failed to split critical edge.\n"); continue; } Changed = true; diff --git a/llvm/lib/CodeGen/PeepholeOptimizer.cpp b/llvm/lib/CodeGen/PeepholeOptimizer.cpp index d7d792e58bf..1d058ccfb63 100644 --- a/llvm/lib/CodeGen/PeepholeOptimizer.cpp +++ b/llvm/lib/CodeGen/PeepholeOptimizer.cpp @@ -696,7 +696,8 @@ bool PeepholeOptimizer::findNextSource(RegSubRegPair RegSubReg, // An existent entry with multiple sources is a PHI cycle we must avoid. // Otherwise it's an entry with a valid next source we already found. if (CurSrcRes.getNumSources() > 1) { - DEBUG(dbgs() << "findNextSource: found PHI cycle, aborting...\n"); + LLVM_DEBUG(dbgs() + << "findNextSource: found PHI cycle, aborting...\n"); return false; } break; @@ -709,7 +710,7 @@ bool PeepholeOptimizer::findNextSource(RegSubRegPair RegSubReg, if (NumSrcs > 1) { PHICount++; if (PHICount >= RewritePHILimit) { - DEBUG(dbgs() << "findNextSource: PHI limit reached\n"); + LLVM_DEBUG(dbgs() << "findNextSource: PHI limit reached\n"); return false; } @@ -1143,9 +1144,9 @@ getNewSource(MachineRegisterInfo *MRI, const TargetInstrInfo *TII, // Build the new PHI node and return its def register as the new source. MachineInstr &OrigPHI = const_cast<MachineInstr &>(*Res.getInst()); MachineInstr &NewPHI = insertPHI(*MRI, *TII, NewPHISrcs, OrigPHI); - DEBUG(dbgs() << "-- getNewSource\n"); - DEBUG(dbgs() << " Replacing: " << OrigPHI); - DEBUG(dbgs() << " With: " << NewPHI); + LLVM_DEBUG(dbgs() << "-- getNewSource\n"); + LLVM_DEBUG(dbgs() << " Replacing: " << OrigPHI); + LLVM_DEBUG(dbgs() << " With: " << NewPHI); const MachineOperand &MODef = NewPHI.getOperand(0); return RegSubRegPair(MODef.getReg(), MODef.getSubReg()); } @@ -1241,9 +1242,9 @@ PeepholeOptimizer::rewriteSource(MachineInstr &CopyLike, NewCopy->getOperand(0).setIsUndef(); } - DEBUG(dbgs() << "-- RewriteSource\n"); - DEBUG(dbgs() << " Replacing: " << CopyLike); - DEBUG(dbgs() << " With: " << *NewCopy); + LLVM_DEBUG(dbgs() << "-- RewriteSource\n"); + LLVM_DEBUG(dbgs() << " Replacing: " << CopyLike); + LLVM_DEBUG(dbgs() << " With: " << *NewCopy); MRI->replaceRegWith(Def.Reg, NewVReg); MRI->clearKillFlags(NewVReg); @@ -1462,7 +1463,8 @@ bool PeepholeOptimizer::foldRedundantNAPhysCopy( if (PrevCopy == NAPhysToVirtMIs.end()) { // We can't remove the copy: there was an intervening clobber of the // non-allocatable physical register after the copy to virtual. - DEBUG(dbgs() << "NAPhysCopy: intervening clobber forbids erasing " << MI); + LLVM_DEBUG(dbgs() << "NAPhysCopy: intervening clobber forbids erasing " + << MI); return false; } @@ -1470,7 +1472,7 @@ bool PeepholeOptimizer::foldRedundantNAPhysCopy( if (PrevDstReg == SrcReg) { // Remove the virt->phys copy: we saw the virtual register definition, and // the non-allocatable physical register's state hasn't changed since then. - DEBUG(dbgs() << "NAPhysCopy: erasing " << MI); + LLVM_DEBUG(dbgs() << "NAPhysCopy: erasing " << MI); ++NumNAPhysCopies; return true; } @@ -1479,7 +1481,7 @@ bool PeepholeOptimizer::foldRedundantNAPhysCopy( // register get a copy of the non-allocatable physical register, and we only // track one such copy. Avoid getting confused by this new non-allocatable // physical register definition, and remove it from the tracked copies. - DEBUG(dbgs() << "NAPhysCopy: missed opportunity " << MI); + LLVM_DEBUG(dbgs() << "NAPhysCopy: missed opportunity " << MI); NAPhysToVirtMIs.erase(PrevCopy); return false; } @@ -1575,15 +1577,15 @@ bool PeepholeOptimizer::optimizeRecurrence(MachineInstr &PHI) { if (findTargetRecurrence(PHI.getOperand(0).getReg(), TargetRegs, RC)) { // Commutes operands of instructions in RC if necessary so that the copy to // be generated from PHI can be coalesced. - DEBUG(dbgs() << "Optimize recurrence chain from " << PHI); + LLVM_DEBUG(dbgs() << "Optimize recurrence chain from " << PHI); for (auto &RI : RC) { - DEBUG(dbgs() << "\tInst: " << *(RI.getMI())); + LLVM_DEBUG(dbgs() << "\tInst: " << *(RI.getMI())); auto CP = RI.getCommutePair(); if (CP) { Changed = true; TII->commuteInstruction(*(RI.getMI()), false, (*CP).first, (*CP).second); - DEBUG(dbgs() << "\t\tCommuted: " << *(RI.getMI())); + LLVM_DEBUG(dbgs() << "\t\tCommuted: " << *(RI.getMI())); } } } @@ -1595,8 +1597,8 @@ bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) { if (skipFunction(MF.getFunction())) return false; - DEBUG(dbgs() << "********** PEEPHOLE OPTIMIZER **********\n"); - DEBUG(dbgs() << "********** Function: " << MF.getName() << '\n'); + LLVM_DEBUG(dbgs() << "********** PEEPHOLE OPTIMIZER **********\n"); + LLVM_DEBUG(dbgs() << "********** Function: " << MF.getName() << '\n'); if (DisablePeephole) return false; @@ -1667,7 +1669,8 @@ bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) { if (Def != NAPhysToVirtMIs.end()) { // A new definition of the non-allocatable physical register // invalidates previous copies. - DEBUG(dbgs() << "NAPhysCopy: invalidating because of " << *MI); + LLVM_DEBUG(dbgs() + << "NAPhysCopy: invalidating because of " << *MI); NAPhysToVirtMIs.erase(Def); } } @@ -1676,7 +1679,8 @@ bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) { for (auto &RegMI : NAPhysToVirtMIs) { unsigned Def = RegMI.first; if (MachineOperand::clobbersPhysReg(RegMask, Def)) { - DEBUG(dbgs() << "NAPhysCopy: invalidating because of " << *MI); + LLVM_DEBUG(dbgs() + << "NAPhysCopy: invalidating because of " << *MI); NAPhysToVirtMIs.erase(Def); } } @@ -1692,7 +1696,8 @@ bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) { // don't know what's correct anymore. // // FIXME: handle explicit asm clobbers. - DEBUG(dbgs() << "NAPhysCopy: blowing away all info due to " << *MI); + LLVM_DEBUG(dbgs() << "NAPhysCopy: blowing away all info due to " + << *MI); NAPhysToVirtMIs.clear(); } @@ -1768,8 +1773,8 @@ bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) { TII->optimizeLoadInstr(*MI, MRI, FoldAsLoadDefReg, DefMI)) { // Update LocalMIs since we replaced MI with FoldMI and deleted // DefMI. - DEBUG(dbgs() << "Replacing: " << *MI); - DEBUG(dbgs() << " With: " << *FoldMI); + LLVM_DEBUG(dbgs() << "Replacing: " << *MI); + LLVM_DEBUG(dbgs() << " With: " << *FoldMI); LocalMIs.erase(MI); LocalMIs.erase(DefMI); LocalMIs.insert(FoldMI); @@ -1791,7 +1796,7 @@ bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) { // the load candidates. Note: We might be able to fold *into* this // instruction, so this needs to be after the folding logic. if (MI->isLoadFoldBarrier()) { - DEBUG(dbgs() << "Encountered load fold barrier on " << *MI); + LLVM_DEBUG(dbgs() << "Encountered load fold barrier on " << *MI); FoldAsLoadDefCandidates.clear(); } } diff --git a/llvm/lib/CodeGen/PostRASchedulerList.cpp b/llvm/lib/CodeGen/PostRASchedulerList.cpp index 2e5e6754bd2..215da630caf 100644 --- a/llvm/lib/CodeGen/PostRASchedulerList.cpp +++ b/llvm/lib/CodeGen/PostRASchedulerList.cpp @@ -243,11 +243,11 @@ void SchedulePostRATDList::enterRegion(MachineBasicBlock *bb, /// Print the schedule before exiting the region. void SchedulePostRATDList::exitRegion() { - DEBUG({ - dbgs() << "*** Final schedule ***\n"; - dumpSchedule(); - dbgs() << '\n'; - }); + LLVM_DEBUG({ + dbgs() << "*** Final schedule ***\n"; + dumpSchedule(); + dbgs() << '\n'; + }); ScheduleDAGInstrs::exitRegion(); } @@ -309,7 +309,7 @@ bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) { : TargetSubtargetInfo::ANTIDEP_NONE); } - DEBUG(dbgs() << "PostRAScheduler\n"); + LLVM_DEBUG(dbgs() << "PostRAScheduler\n"); SchedulePostRATDList Scheduler(Fn, MLI, AA, RegClassInfo, AntiDepMode, CriticalPathRCs); @@ -413,13 +413,12 @@ void SchedulePostRATDList::schedule() { postprocessDAG(); - DEBUG(dbgs() << "********** List Scheduling **********\n"); - DEBUG( - for (const SUnit &SU : SUnits) { - SU.dumpAll(this); - dbgs() << '\n'; - } - ); + LLVM_DEBUG(dbgs() << "********** List Scheduling **********\n"); + LLVM_DEBUG(for (const SUnit &SU + : SUnits) { + SU.dumpAll(this); + dbgs() << '\n'; + }); AvailableQueue.initNodes(SUnits); ListScheduleTopDown(); @@ -502,8 +501,8 @@ void SchedulePostRATDList::ReleaseSuccessors(SUnit *SU) { /// count of its successors. If a successor pending count is zero, add it to /// the Available queue. void SchedulePostRATDList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) { - DEBUG(dbgs() << "*** Scheduling [" << CurCycle << "]: "); - DEBUG(SU->dump(this)); + LLVM_DEBUG(dbgs() << "*** Scheduling [" << CurCycle << "]: "); + LLVM_DEBUG(SU->dump(this)); Sequence.push_back(SU); assert(CurCycle >= SU->getDepth() && @@ -517,7 +516,7 @@ void SchedulePostRATDList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) { /// emitNoop - Add a noop to the current instruction sequence. void SchedulePostRATDList::emitNoop(unsigned CurCycle) { - DEBUG(dbgs() << "*** Emitting noop in cycle " << CurCycle << '\n'); + LLVM_DEBUG(dbgs() << "*** Emitting noop in cycle " << CurCycle << '\n'); HazardRec->EmitNoop(); Sequence.push_back(nullptr); // NULL here means noop ++NumNoops; @@ -569,7 +568,8 @@ void SchedulePostRATDList::ListScheduleTopDown() { MinDepth = PendingQueue[i]->getDepth(); } - DEBUG(dbgs() << "\n*** Examining Available\n"; AvailableQueue.dump(this)); + LLVM_DEBUG(dbgs() << "\n*** Examining Available\n"; + AvailableQueue.dump(this)); SUnit *FoundSUnit = nullptr, *NotPreferredSUnit = nullptr; bool HasNoopHazards = false; @@ -605,7 +605,8 @@ void SchedulePostRATDList::ListScheduleTopDown() { // non-preferred node. if (NotPreferredSUnit) { if (!FoundSUnit) { - DEBUG(dbgs() << "*** Will schedule a non-preferred instruction...\n"); + LLVM_DEBUG( + dbgs() << "*** Will schedule a non-preferred instruction...\n"); FoundSUnit = NotPreferredSUnit; } else { AvailableQueue.push(NotPreferredSUnit); @@ -632,19 +633,20 @@ void SchedulePostRATDList::ListScheduleTopDown() { HazardRec->EmitInstruction(FoundSUnit); CycleHasInsts = true; if (HazardRec->atIssueLimit()) { - DEBUG(dbgs() << "*** Max instructions per cycle " << CurCycle << '\n'); + LLVM_DEBUG(dbgs() << "*** Max instructions per cycle " << CurCycle + << '\n'); HazardRec->AdvanceCycle(); ++CurCycle; CycleHasInsts = false; } } else { if (CycleHasInsts) { - DEBUG(dbgs() << "*** Finished cycle " << CurCycle << '\n'); + LLVM_DEBUG(dbgs() << "*** Finished cycle " << CurCycle << '\n'); HazardRec->AdvanceCycle(); } else if (!HasNoopHazards) { // Otherwise, we have a pipeline stall, but no other problem, // just advance the current cycle and try again. - DEBUG(dbgs() << "*** Stall in cycle " << CurCycle << '\n'); + LLVM_DEBUG(dbgs() << "*** Stall in cycle " << CurCycle << '\n'); HazardRec->AdvanceCycle(); ++NumStalls; } else { diff --git a/llvm/lib/CodeGen/ProcessImplicitDefs.cpp b/llvm/lib/CodeGen/ProcessImplicitDefs.cpp index 48b48c5f649..3bc5809090f 100644 --- a/llvm/lib/CodeGen/ProcessImplicitDefs.cpp +++ b/llvm/lib/CodeGen/ProcessImplicitDefs.cpp @@ -73,7 +73,7 @@ bool ProcessImplicitDefs::canTurnIntoImplicitDef(MachineInstr *MI) { } void ProcessImplicitDefs::processImplicitDef(MachineInstr *MI) { - DEBUG(dbgs() << "Processing " << *MI); + LLVM_DEBUG(dbgs() << "Processing " << *MI); unsigned Reg = MI->getOperand(0).getReg(); if (TargetRegisterInfo::isVirtualRegister(Reg)) { @@ -84,7 +84,7 @@ void ProcessImplicitDefs::processImplicitDef(MachineInstr *MI) { MachineInstr *UserMI = MO.getParent(); if (!canTurnIntoImplicitDef(UserMI)) continue; - DEBUG(dbgs() << "Converting to IMPLICIT_DEF: " << *UserMI); + LLVM_DEBUG(dbgs() << "Converting to IMPLICIT_DEF: " << *UserMI); UserMI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF)); WorkList.insert(UserMI); } @@ -116,7 +116,7 @@ void ProcessImplicitDefs::processImplicitDef(MachineInstr *MI) { // If we found the using MI, we can erase the IMPLICIT_DEF. if (Found) { - DEBUG(dbgs() << "Physreg user: " << *UserMI); + LLVM_DEBUG(dbgs() << "Physreg user: " << *UserMI); MI->eraseFromParent(); return; } @@ -125,15 +125,15 @@ void ProcessImplicitDefs::processImplicitDef(MachineInstr *MI) { // Leave the physreg IMPLICIT_DEF, but trim any extra operands. for (unsigned i = MI->getNumOperands() - 1; i; --i) MI->RemoveOperand(i); - DEBUG(dbgs() << "Keeping physreg: " << *MI); + LLVM_DEBUG(dbgs() << "Keeping physreg: " << *MI); } /// processImplicitDefs - Process IMPLICIT_DEF instructions and turn them into /// <undef> operands. bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &MF) { - DEBUG(dbgs() << "********** PROCESS IMPLICIT DEFS **********\n" - << "********** Function: " << MF.getName() << '\n'); + LLVM_DEBUG(dbgs() << "********** PROCESS IMPLICIT DEFS **********\n" + << "********** Function: " << MF.getName() << '\n'); bool Changed = false; @@ -154,8 +154,8 @@ bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &MF) { if (WorkList.empty()) continue; - DEBUG(dbgs() << printMBBReference(*MFI) << " has " << WorkList.size() - << " implicit defs.\n"); + LLVM_DEBUG(dbgs() << printMBBReference(*MFI) << " has " << WorkList.size() + << " implicit defs.\n"); Changed = true; // Drain the WorkList to recursively process any new implicit defs. diff --git a/llvm/lib/CodeGen/PrologEpilogInserter.cpp b/llvm/lib/CodeGen/PrologEpilogInserter.cpp index 5e431f9761a..e2ee4e501a0 100644 --- a/llvm/lib/CodeGen/PrologEpilogInserter.cpp +++ b/llvm/lib/CodeGen/PrologEpilogInserter.cpp @@ -564,10 +564,12 @@ AdjustStackOffset(MachineFrameInfo &MFI, int FrameIdx, Offset = alignTo(Offset, Align, Skew); if (StackGrowsDown) { - DEBUG(dbgs() << "alloc FI(" << FrameIdx << ") at SP[" << -Offset << "]\n"); + LLVM_DEBUG(dbgs() << "alloc FI(" << FrameIdx << ") at SP[" << -Offset + << "]\n"); MFI.setObjectOffset(FrameIdx, -Offset); // Set the computed offset } else { - DEBUG(dbgs() << "alloc FI(" << FrameIdx << ") at SP[" << Offset << "]\n"); + LLVM_DEBUG(dbgs() << "alloc FI(" << FrameIdx << ") at SP[" << Offset + << "]\n"); MFI.setObjectOffset(FrameIdx, Offset); Offset += MFI.getObjectSize(FrameIdx); } @@ -660,12 +662,12 @@ static inline bool scavengeStackSlot(MachineFrameInfo &MFI, int FrameIdx, if (StackGrowsDown) { int ObjStart = -(FreeStart + ObjSize); - DEBUG(dbgs() << "alloc FI(" << FrameIdx << ") scavenged at SP[" << ObjStart - << "]\n"); + LLVM_DEBUG(dbgs() << "alloc FI(" << FrameIdx << ") scavenged at SP[" + << ObjStart << "]\n"); MFI.setObjectOffset(FrameIdx, ObjStart); } else { - DEBUG(dbgs() << "alloc FI(" << FrameIdx << ") scavenged at SP[" << FreeStart - << "]\n"); + LLVM_DEBUG(dbgs() << "alloc FI(" << FrameIdx << ") scavenged at SP[" + << FreeStart << "]\n"); MFI.setObjectOffset(FrameIdx, FreeStart); } @@ -745,7 +747,7 @@ void PEI::calculateFrameObjectOffsets(MachineFunction &Fn) { // Adjust to alignment boundary Offset = alignTo(Offset, Align, Skew); - DEBUG(dbgs() << "alloc FI(" << i << ") at SP[" << -Offset << "]\n"); + LLVM_DEBUG(dbgs() << "alloc FI(" << i << ") at SP[" << -Offset << "]\n"); MFI.setObjectOffset(i, -Offset); // Set the computed offset } } else if (MaxCSFrameIndex >= MinCSFrameIndex) { @@ -758,7 +760,7 @@ void PEI::calculateFrameObjectOffsets(MachineFunction &Fn) { // Adjust to alignment boundary Offset = alignTo(Offset, Align, Skew); - DEBUG(dbgs() << "alloc FI(" << i << ") at SP[" << Offset << "]\n"); + LLVM_DEBUG(dbgs() << "alloc FI(" << i << ") at SP[" << Offset << "]\n"); MFI.setObjectOffset(i, Offset); Offset += MFI.getObjectSize(i); } @@ -795,14 +797,14 @@ void PEI::calculateFrameObjectOffsets(MachineFunction &Fn) { // Adjust to alignment boundary. Offset = alignTo(Offset, Align, Skew); - DEBUG(dbgs() << "Local frame base offset: " << Offset << "\n"); + LLVM_DEBUG(dbgs() << "Local frame base offset: " << Offset << "\n"); // Resolve offsets for objects in the local block. for (unsigned i = 0, e = MFI.getLocalFrameObjectCount(); i != e; ++i) { std::pair<int, int64_t> Entry = MFI.getLocalFrameObjectMap(i); int64_t FIOffset = (StackGrowsDown ? -Offset : Offset) + Entry.second; - DEBUG(dbgs() << "alloc FI(" << Entry.first << ") at SP[" << - FIOffset << "]\n"); + LLVM_DEBUG(dbgs() << "alloc FI(" << Entry.first << ") at SP[" << FIOffset + << "]\n"); MFI.setObjectOffset(Entry.first, FIOffset); } // Allocate the local block diff --git a/llvm/lib/CodeGen/ReachingDefAnalysis.cpp b/llvm/lib/CodeGen/ReachingDefAnalysis.cpp index 31eb8c9b264..050fef5d25e 100644 --- a/llvm/lib/CodeGen/ReachingDefAnalysis.cpp +++ b/llvm/lib/CodeGen/ReachingDefAnalysis.cpp @@ -47,7 +47,7 @@ void ReachingDefAnalysis::enterBasicBlock( MBBReachingDefs[MBBNumber][*Unit].push_back(LiveRegs[*Unit]); } } - DEBUG(dbgs() << printMBBReference(*MBB) << ": entry\n"); + LLVM_DEBUG(dbgs() << printMBBReference(*MBB) << ": entry\n"); return; } @@ -69,9 +69,9 @@ void ReachingDefAnalysis::enterBasicBlock( } } - DEBUG(dbgs() << printMBBReference(*MBB) - << (!TraversedMBB.IsDone ? ": incomplete\n" - : ": all preds known\n")); + LLVM_DEBUG(dbgs() << printMBBReference(*MBB) + << (!TraversedMBB.IsDone ? ": incomplete\n" + : ": all preds known\n")); } void ReachingDefAnalysis::leaveBasicBlock( @@ -109,8 +109,8 @@ void ReachingDefAnalysis::processDefs(MachineInstr *MI) { continue; for (MCRegUnitIterator Unit(MO.getReg(), TRI); Unit.isValid(); ++Unit) { // This instruction explicitly defines the current reg unit. - DEBUG(dbgs() << printReg(MO.getReg(), TRI) << ":\t" << CurInstr << '\t' - << *MI); + LLVM_DEBUG(dbgs() << printReg(MO.getReg(), TRI) << ":\t" << CurInstr + << '\t' << *MI); // How many instructions since this reg unit was last written? LiveRegs[*Unit] = CurInstr; @@ -142,7 +142,7 @@ bool ReachingDefAnalysis::runOnMachineFunction(MachineFunction &mf) { MBBReachingDefs.resize(mf.getNumBlockIDs()); - DEBUG(dbgs() << "********** REACHING DEFINITION ANALYSIS **********\n"); + LLVM_DEBUG(dbgs() << "********** REACHING DEFINITION ANALYSIS **********\n"); // Initialize the MBBOutRegsInfos MBBOutRegsInfos.resize(mf.getNumBlockIDs()); diff --git a/llvm/lib/CodeGen/RegAllocBase.cpp b/llvm/lib/CodeGen/RegAllocBase.cpp index 74c1592634a..bc28a054c68 100644 --- a/llvm/lib/CodeGen/RegAllocBase.cpp +++ b/llvm/lib/CodeGen/RegAllocBase.cpp @@ -91,7 +91,7 @@ void RegAllocBase::allocatePhysRegs() { // Unused registers can appear when the spiller coalesces snippets. if (MRI->reg_nodbg_empty(VirtReg->reg)) { - DEBUG(dbgs() << "Dropping unused " << *VirtReg << '\n'); + LLVM_DEBUG(dbgs() << "Dropping unused " << *VirtReg << '\n'); aboutToRemoveInterval(*VirtReg); LIS->removeInterval(VirtReg->reg); continue; @@ -103,9 +103,9 @@ void RegAllocBase::allocatePhysRegs() { // selectOrSplit requests the allocator to return an available physical // register if possible and populate a list of new live intervals that // result from splitting. - DEBUG(dbgs() << "\nselectOrSplit " - << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg)) - << ':' << *VirtReg << " w=" << VirtReg->weight << '\n'); + LLVM_DEBUG(dbgs() << "\nselectOrSplit " + << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg)) + << ':' << *VirtReg << " w=" << VirtReg->weight << '\n'); using VirtRegVec = SmallVector<unsigned, 4>; @@ -145,12 +145,12 @@ void RegAllocBase::allocatePhysRegs() { assert(!VRM->hasPhys(SplitVirtReg->reg) && "Register already assigned"); if (MRI->reg_nodbg_empty(SplitVirtReg->reg)) { assert(SplitVirtReg->empty() && "Non-empty but used interval"); - DEBUG(dbgs() << "not queueing unused " << *SplitVirtReg << '\n'); + LLVM_DEBUG(dbgs() << "not queueing unused " << *SplitVirtReg << '\n'); aboutToRemoveInterval(*SplitVirtReg); LIS->removeInterval(SplitVirtReg->reg); continue; } - DEBUG(dbgs() << "queuing new interval: " << *SplitVirtReg << "\n"); + LLVM_DEBUG(dbgs() << "queuing new interval: " << *SplitVirtReg << "\n"); assert(TargetRegisterInfo::isVirtualRegister(SplitVirtReg->reg) && "expect split value in virtual register"); enqueue(SplitVirtReg); diff --git a/llvm/lib/CodeGen/RegAllocBasic.cpp b/llvm/lib/CodeGen/RegAllocBasic.cpp index 1125d2c62be..daeff3fc396 100644 --- a/llvm/lib/CodeGen/RegAllocBasic.cpp +++ b/llvm/lib/CodeGen/RegAllocBasic.cpp @@ -219,8 +219,8 @@ bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, Intfs.push_back(Intf); } } - DEBUG(dbgs() << "spilling " << printReg(PhysReg, TRI) - << " interferences with " << VirtReg << "\n"); + LLVM_DEBUG(dbgs() << "spilling " << printReg(PhysReg, TRI) + << " interferences with " << VirtReg << "\n"); assert(!Intfs.empty() && "expected interference"); // Spill each interfering vreg allocated to PhysReg or an alias. @@ -292,7 +292,7 @@ unsigned RABasic::selectOrSplit(LiveInterval &VirtReg, } // No other spill candidates were found, so spill the current VirtReg. - DEBUG(dbgs() << "spilling: " << VirtReg << '\n'); + LLVM_DEBUG(dbgs() << "spilling: " << VirtReg << '\n'); if (!VirtReg.isSpillable()) return ~0u; LiveRangeEdit LRE(&VirtReg, SplitVRegs, *MF, *LIS, VRM, this, &DeadRemats); @@ -304,9 +304,8 @@ unsigned RABasic::selectOrSplit(LiveInterval &VirtReg, } bool RABasic::runOnMachineFunction(MachineFunction &mf) { - DEBUG(dbgs() << "********** BASIC REGISTER ALLOCATION **********\n" - << "********** Function: " - << mf.getName() << '\n'); + LLVM_DEBUG(dbgs() << "********** BASIC REGISTER ALLOCATION **********\n" + << "********** Function: " << mf.getName() << '\n'); MF = &mf; RegAllocBase::init(getAnalysis<VirtRegMap>(), @@ -323,7 +322,7 @@ bool RABasic::runOnMachineFunction(MachineFunction &mf) { postOptimization(); // Diagnostic output before rewriting - DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *VRM << "\n"); + LLVM_DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *VRM << "\n"); releaseMemory(); return true; diff --git a/llvm/lib/CodeGen/RegAllocFast.cpp b/llvm/lib/CodeGen/RegAllocFast.cpp index 241f680e2e8..e2980d175e7 100644 --- a/llvm/lib/CodeGen/RegAllocFast.cpp +++ b/llvm/lib/CodeGen/RegAllocFast.cpp @@ -322,11 +322,11 @@ void RegAllocFast::spillVirtReg(MachineBasicBlock::iterator MI, // instruction, not on the spill. bool SpillKill = MachineBasicBlock::iterator(LR.LastUse) != MI; LR.Dirty = false; - DEBUG(dbgs() << "Spilling " << printReg(LRI->VirtReg, TRI) - << " in " << printReg(LR.PhysReg, TRI)); + LLVM_DEBUG(dbgs() << "Spilling " << printReg(LRI->VirtReg, TRI) << " in " + << printReg(LR.PhysReg, TRI)); const TargetRegisterClass &RC = *MRI->getRegClass(LRI->VirtReg); int FI = getStackSpaceFor(LRI->VirtReg, RC); - DEBUG(dbgs() << " to stack slot #" << FI << "\n"); + LLVM_DEBUG(dbgs() << " to stack slot #" << FI << "\n"); TII->storeRegToStackSlot(*MBB, MI, LR.PhysReg, SpillKill, FI, &RC, TRI); ++NumStores; // Update statistics @@ -339,7 +339,9 @@ void RegAllocFast::spillVirtReg(MachineBasicBlock::iterator MI, MachineInstr *NewDV = buildDbgValueForSpill(*MBB, MI, *DBG, FI); assert(NewDV->getParent() == MBB && "dangling parent pointer"); (void)NewDV; - DEBUG(dbgs() << "Inserting debug info due to spill:" << "\n" << *NewDV); + LLVM_DEBUG(dbgs() << "Inserting debug info due to spill:" + << "\n" + << *NewDV); } // Now this register is spilled there is should not be any DBG_VALUE // pointing to this register because they are all pointing to spilled value @@ -476,7 +478,8 @@ void RegAllocFast::definePhysReg(MachineBasicBlock::iterator MI, /// \returns spillImpossible when PhysReg or an alias can't be spilled. unsigned RegAllocFast::calcSpillCost(MCPhysReg PhysReg) const { if (isRegUsedInInstr(PhysReg)) { - DEBUG(dbgs() << printReg(PhysReg, TRI) << " is already used in instr.\n"); + LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) + << " is already used in instr.\n"); return spillImpossible; } switch (unsigned VirtReg = PhysRegState[PhysReg]) { @@ -485,8 +488,8 @@ unsigned RegAllocFast::calcSpillCost(MCPhysReg PhysReg) const { case regFree: return 0; case regReserved: - DEBUG(dbgs() << printReg(VirtReg, TRI) << " corresponding " - << printReg(PhysReg, TRI) << " is reserved already.\n"); + LLVM_DEBUG(dbgs() << printReg(VirtReg, TRI) << " corresponding " + << printReg(PhysReg, TRI) << " is reserved already.\n"); return spillImpossible; default: { LiveRegMap::const_iterator I = findLiveVirtReg(VirtReg); @@ -496,7 +499,7 @@ unsigned RegAllocFast::calcSpillCost(MCPhysReg PhysReg) const { } // This is a disabled register, add up cost of aliases. - DEBUG(dbgs() << printReg(PhysReg, TRI) << " is disabled.\n"); + LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << " is disabled.\n"); unsigned Cost = 0; for (MCRegAliasIterator AI(PhysReg, TRI, false); AI.isValid(); ++AI) { MCPhysReg Alias = *AI; @@ -523,8 +526,8 @@ unsigned RegAllocFast::calcSpillCost(MCPhysReg PhysReg) const { /// proper container for VirtReg now. The physical register must not be used /// for anything else when this is called. void RegAllocFast::assignVirtToPhysReg(LiveReg &LR, MCPhysReg PhysReg) { - DEBUG(dbgs() << "Assigning " << printReg(LR.VirtReg, TRI) << " to " - << printReg(PhysReg, TRI) << "\n"); + LLVM_DEBUG(dbgs() << "Assigning " << printReg(LR.VirtReg, TRI) << " to " + << printReg(PhysReg, TRI) << "\n"); PhysRegState[PhysReg] = LR.VirtReg; assert(!LR.PhysReg && "Already assigned a physreg"); LR.PhysReg = PhysReg; @@ -570,16 +573,16 @@ RegAllocFast::LiveRegMap::iterator RegAllocFast::allocVirtReg(MachineInstr &MI, } } - DEBUG(dbgs() << "Allocating " << printReg(VirtReg) << " from " - << TRI->getRegClassName(&RC) << "\n"); + LLVM_DEBUG(dbgs() << "Allocating " << printReg(VirtReg) << " from " + << TRI->getRegClassName(&RC) << "\n"); unsigned BestReg = 0; unsigned BestCost = spillImpossible; for (MCPhysReg PhysReg : AO) { unsigned Cost = calcSpillCost(PhysReg); - DEBUG(dbgs() << "\tRegister: " << printReg(PhysReg, TRI) << "\n"); - DEBUG(dbgs() << "\tCost: " << Cost << "\n"); - DEBUG(dbgs() << "\tBestCost: " << BestCost << "\n"); + LLVM_DEBUG(dbgs() << "\tRegister: " << printReg(PhysReg, TRI) << "\n"); + LLVM_DEBUG(dbgs() << "\tCost: " << Cost << "\n"); + LLVM_DEBUG(dbgs() << "\tBestCost: " << BestCost << "\n"); // Cost is 0 when all aliases are already disabled. if (Cost == 0) { assignVirtToPhysReg(*LRI, PhysReg); @@ -654,22 +657,22 @@ RegAllocFast::LiveRegMap::iterator RegAllocFast::reloadVirtReg(MachineInstr &MI, LRI = allocVirtReg(MI, LRI, Hint); const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); int FrameIndex = getStackSpaceFor(VirtReg, RC); - DEBUG(dbgs() << "Reloading " << printReg(VirtReg, TRI) << " into " - << printReg(LRI->PhysReg, TRI) << "\n"); + LLVM_DEBUG(dbgs() << "Reloading " << printReg(VirtReg, TRI) << " into " + << printReg(LRI->PhysReg, TRI) << "\n"); TII->loadRegFromStackSlot(*MBB, MI, LRI->PhysReg, FrameIndex, &RC, TRI); ++NumLoads; } else if (LRI->Dirty) { if (isLastUseOfLocalReg(MO)) { - DEBUG(dbgs() << "Killing last use: " << MO << "\n"); + LLVM_DEBUG(dbgs() << "Killing last use: " << MO << "\n"); if (MO.isUse()) MO.setIsKill(); else MO.setIsDead(); } else if (MO.isKill()) { - DEBUG(dbgs() << "Clearing dubious kill: " << MO << "\n"); + LLVM_DEBUG(dbgs() << "Clearing dubious kill: " << MO << "\n"); MO.setIsKill(false); } else if (MO.isDead()) { - DEBUG(dbgs() << "Clearing dubious dead: " << MO << "\n"); + LLVM_DEBUG(dbgs() << "Clearing dubious dead: " << MO << "\n"); MO.setIsDead(false); } } else if (MO.isKill()) { @@ -677,10 +680,10 @@ RegAllocFast::LiveRegMap::iterator RegAllocFast::reloadVirtReg(MachineInstr &MI, // register would be killed immediately, and there might be a second use: // %foo = OR killed %x, %x // This would cause a second reload of %x into a different register. - DEBUG(dbgs() << "Clearing clean kill: " << MO << "\n"); + LLVM_DEBUG(dbgs() << "Clearing clean kill: " << MO << "\n"); MO.setIsKill(false); } else if (MO.isDead()) { - DEBUG(dbgs() << "Clearing clean dead: " << MO << "\n"); + LLVM_DEBUG(dbgs() << "Clearing clean dead: " << MO << "\n"); MO.setIsDead(false); } assert(LRI->PhysReg && "Register not assigned"); @@ -727,7 +730,7 @@ bool RegAllocFast::setPhysReg(MachineInstr &MI, unsigned OpNum, // there are additional physreg defines. void RegAllocFast::handleThroughOperands(MachineInstr &MI, SmallVectorImpl<unsigned> &VirtDead) { - DEBUG(dbgs() << "Scanning for through registers:"); + LLVM_DEBUG(dbgs() << "Scanning for through registers:"); SmallSet<unsigned, 8> ThroughRegs; for (const MachineOperand &MO : MI.operands()) { if (!MO.isReg()) continue; @@ -737,13 +740,13 @@ void RegAllocFast::handleThroughOperands(MachineInstr &MI, if (MO.isEarlyClobber() || (MO.isUse() && MO.isTied()) || (MO.getSubReg() && MI.readsVirtualRegister(Reg))) { if (ThroughRegs.insert(Reg).second) - DEBUG(dbgs() << ' ' << printReg(Reg)); + LLVM_DEBUG(dbgs() << ' ' << printReg(Reg)); } } // If any physreg defines collide with preallocated through registers, // we must spill and reallocate. - DEBUG(dbgs() << "\nChecking for physdef collisions.\n"); + LLVM_DEBUG(dbgs() << "\nChecking for physdef collisions.\n"); for (const MachineOperand &MO : MI.operands()) { if (!MO.isReg() || !MO.isDef()) continue; unsigned Reg = MO.getReg(); @@ -756,7 +759,7 @@ void RegAllocFast::handleThroughOperands(MachineInstr &MI, } SmallVector<unsigned, 8> PartialDefs; - DEBUG(dbgs() << "Allocating tied uses.\n"); + LLVM_DEBUG(dbgs() << "Allocating tied uses.\n"); for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) { const MachineOperand &MO = MI.getOperand(I); if (!MO.isReg()) continue; @@ -764,15 +767,16 @@ void RegAllocFast::handleThroughOperands(MachineInstr &MI, if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue; if (MO.isUse()) { if (!MO.isTied()) continue; - DEBUG(dbgs() << "Operand " << I << "("<< MO << ") is tied to operand " - << MI.findTiedOperandIdx(I) << ".\n"); + LLVM_DEBUG(dbgs() << "Operand " << I << "(" << MO + << ") is tied to operand " << MI.findTiedOperandIdx(I) + << ".\n"); LiveRegMap::iterator LRI = reloadVirtReg(MI, I, Reg, 0); MCPhysReg PhysReg = LRI->PhysReg; setPhysReg(MI, I, PhysReg); // Note: we don't update the def operand yet. That would cause the normal // def-scan to attempt spilling. } else if (MO.getSubReg() && MI.readsVirtualRegister(Reg)) { - DEBUG(dbgs() << "Partial redefine: " << MO << "\n"); + LLVM_DEBUG(dbgs() << "Partial redefine: " << MO << "\n"); // Reload the register, but don't assign to the operand just yet. // That would confuse the later phys-def processing pass. LiveRegMap::iterator LRI = reloadVirtReg(MI, I, Reg, 0); @@ -780,7 +784,7 @@ void RegAllocFast::handleThroughOperands(MachineInstr &MI, } } - DEBUG(dbgs() << "Allocating early clobbers.\n"); + LLVM_DEBUG(dbgs() << "Allocating early clobbers.\n"); for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) { const MachineOperand &MO = MI.getOperand(I); if (!MO.isReg()) continue; @@ -801,8 +805,8 @@ void RegAllocFast::handleThroughOperands(MachineInstr &MI, if (!MO.isReg() || (MO.isDef() && !MO.isEarlyClobber())) continue; unsigned Reg = MO.getReg(); if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue; - DEBUG(dbgs() << "\tSetting " << printReg(Reg, TRI) - << " as used in instr\n"); + LLVM_DEBUG(dbgs() << "\tSetting " << printReg(Reg, TRI) + << " as used in instr\n"); markRegUsedInInstr(Reg); } @@ -848,7 +852,7 @@ void RegAllocFast::dumpState() { void RegAllocFast::allocateBasicBlock(MachineBasicBlock &MBB) { this->MBB = &MBB; - DEBUG(dbgs() << "\nAllocating " << MBB); + LLVM_DEBUG(dbgs() << "\nAllocating " << MBB); PhysRegState.assign(TRI->getNumRegs(), regDisabled); assert(LiveVirtRegs.empty() && "Mapping not cleared from last block?"); @@ -866,10 +870,7 @@ void RegAllocFast::allocateBasicBlock(MachineBasicBlock &MBB) { // Otherwise, sequentially allocate each instruction in the MBB. for (MachineInstr &MI : MBB) { const MCInstrDesc &MCID = MI.getDesc(); - DEBUG( - dbgs() << "\n>> " << MI << "Regs:"; - dumpState() - ); + LLVM_DEBUG(dbgs() << "\n>> " << MI << "Regs:"; dumpState()); // Debug values are not allowed to change codegen in any way. if (MI.isDebugValue()) { @@ -894,13 +895,13 @@ void RegAllocFast::allocateBasicBlock(MachineBasicBlock &MBB) { if (SS != -1) { // Modify DBG_VALUE now that the value is in a spill slot. updateDbgValueForSpill(*DebugMI, SS); - DEBUG(dbgs() << "Modifying debug info due to spill:" - << "\t" << *DebugMI); + LLVM_DEBUG(dbgs() << "Modifying debug info due to spill:" + << "\t" << *DebugMI); continue; } // We can't allocate a physreg for a DebugValue, sorry! - DEBUG(dbgs() << "Unable to allocate vreg used by DBG_VALUE"); + LLVM_DEBUG(dbgs() << "Unable to allocate vreg used by DBG_VALUE"); MO.setReg(0); } @@ -1028,7 +1029,7 @@ void RegAllocFast::allocateBasicBlock(MachineBasicBlock &MBB) { // as call-clobbered, this is not correct because some of those // definitions may be used later on and we do not want to reuse // those for virtual registers in between. - DEBUG(dbgs() << " Spilling remaining registers before call.\n"); + LLVM_DEBUG(dbgs() << " Spilling remaining registers before call.\n"); spillAll(MI); } @@ -1063,15 +1064,15 @@ void RegAllocFast::allocateBasicBlock(MachineBasicBlock &MBB) { VirtDead.clear(); if (CopyDstReg && CopyDstReg == CopySrcReg && CopyDstSub == CopySrcSub) { - DEBUG(dbgs() << "-- coalescing: " << MI); + LLVM_DEBUG(dbgs() << "-- coalescing: " << MI); Coalesced.push_back(&MI); } else { - DEBUG(dbgs() << "<< " << MI); + LLVM_DEBUG(dbgs() << "<< " << MI); } } // Spill all physical registers holding virtual registers now. - DEBUG(dbgs() << "Spilling live registers at end of block.\n"); + LLVM_DEBUG(dbgs() << "Spilling live registers at end of block.\n"); spillAll(MBB.getFirstTerminator()); // Erase all the coalesced copies. We are delaying it until now because @@ -1080,13 +1081,13 @@ void RegAllocFast::allocateBasicBlock(MachineBasicBlock &MBB) { MBB.erase(MI); NumCopies += Coalesced.size(); - DEBUG(MBB.dump()); + LLVM_DEBUG(MBB.dump()); } /// Allocates registers for a function. bool RegAllocFast::runOnMachineFunction(MachineFunction &MF) { - DEBUG(dbgs() << "********** FAST REGISTER ALLOCATION **********\n" - << "********** Function: " << MF.getName() << '\n'); + LLVM_DEBUG(dbgs() << "********** FAST REGISTER ALLOCATION **********\n" + << "********** Function: " << MF.getName() << '\n'); MRI = &MF.getRegInfo(); const TargetSubtargetInfo &STI = MF.getSubtarget(); TRI = STI.getRegisterInfo(); diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp index 04b5393d79d..182d9665098 100644 --- a/llvm/lib/CodeGen/RegAllocGreedy.cpp +++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp @@ -766,7 +766,7 @@ unsigned RAGreedy::tryAssign(LiveInterval &VirtReg, // preferred register. if (unsigned Hint = MRI->getSimpleHint(VirtReg.reg)) if (Order.isHint(Hint)) { - DEBUG(dbgs() << "missed hint " << printReg(Hint, TRI) << '\n'); + LLVM_DEBUG(dbgs() << "missed hint " << printReg(Hint, TRI) << '\n'); EvictionCost MaxCost; MaxCost.setBrokenHints(1); if (canEvictInterference(VirtReg, Hint, true, MaxCost)) { @@ -785,8 +785,8 @@ unsigned RAGreedy::tryAssign(LiveInterval &VirtReg, if (!Cost) return PhysReg; - DEBUG(dbgs() << printReg(PhysReg, TRI) << " is available at cost " << Cost - << '\n'); + LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << " is available at cost " + << Cost << '\n'); unsigned CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost); return CheapReg ? CheapReg : PhysReg; } @@ -814,9 +814,9 @@ unsigned RAGreedy::canReassign(LiveInterval &VirtReg, unsigned PrevReg) { break; } if (PhysReg) - DEBUG(dbgs() << "can reassign: " << VirtReg << " from " - << printReg(PrevReg, TRI) << " to " << printReg(PhysReg, TRI) - << '\n'); + LLVM_DEBUG(dbgs() << "can reassign: " << VirtReg << " from " + << printReg(PrevReg, TRI) << " to " + << printReg(PhysReg, TRI) << '\n'); return PhysReg; } @@ -843,7 +843,7 @@ bool RAGreedy::shouldEvict(LiveInterval &A, bool IsHint, return true; if (A.weight > B.weight) { - DEBUG(dbgs() << "should evict: " << B << " w= " << B.weight << '\n'); + LLVM_DEBUG(dbgs() << "should evict: " << B << " w= " << B.weight << '\n'); return true; } return false; @@ -1035,8 +1035,8 @@ void RAGreedy::evictInterference(LiveInterval &VirtReg, unsigned PhysReg, if (!Cascade) Cascade = ExtraRegInfo[VirtReg.reg].Cascade = NextCascade++; - DEBUG(dbgs() << "evicting " << printReg(PhysReg, TRI) - << " interference: Cascade " << Cascade << '\n'); + LLVM_DEBUG(dbgs() << "evicting " << printReg(PhysReg, TRI) + << " interference: Cascade " << Cascade << '\n'); // Collect all interfering virtregs first. SmallVector<LiveInterval*, 8> Intfs; @@ -1107,8 +1107,8 @@ unsigned RAGreedy::tryEvict(LiveInterval &VirtReg, const TargetRegisterClass *RC = MRI->getRegClass(VirtReg.reg); unsigned MinCost = RegClassInfo.getMinCost(RC); if (MinCost >= CostPerUseLimit) { - DEBUG(dbgs() << TRI->getRegClassName(RC) << " minimum cost = " << MinCost - << ", no cheaper registers to be found.\n"); + LLVM_DEBUG(dbgs() << TRI->getRegClassName(RC) << " minimum cost = " + << MinCost << ", no cheaper registers to be found.\n"); return 0; } @@ -1116,7 +1116,8 @@ unsigned RAGreedy::tryEvict(LiveInterval &VirtReg, // the same cost. We don't need to look at them if they're too expensive. if (TRI->getCostPerUse(Order.getOrder().back()) >= CostPerUseLimit) { OrderLimit = RegClassInfo.getLastCostChange(RC); - DEBUG(dbgs() << "Only trying the first " << OrderLimit << " regs.\n"); + LLVM_DEBUG(dbgs() << "Only trying the first " << OrderLimit + << " regs.\n"); } } @@ -1127,9 +1128,10 @@ unsigned RAGreedy::tryEvict(LiveInterval &VirtReg, // The first use of a callee-saved register in a function has cost 1. // Don't start using a CSR when the CostPerUseLimit is low. if (CostPerUseLimit == 1 && isUnusedCalleeSavedReg(PhysReg)) { - DEBUG(dbgs() << printReg(PhysReg, TRI) << " would clobber CSR " - << printReg(RegClassInfo.getLastCalleeSavedAlias(PhysReg), TRI) - << '\n'); + LLVM_DEBUG( + dbgs() << printReg(PhysReg, TRI) << " would clobber CSR " + << printReg(RegClassInfo.getLastCalleeSavedAlias(PhysReg), TRI) + << '\n'); continue; } @@ -1316,7 +1318,7 @@ void RAGreedy::growRegion(GlobalSplitCandidate &Cand) { // Perhaps iterating can enable more bundles? SpillPlacer->iterate(); } - DEBUG(dbgs() << ", v=" << Visited); + LLVM_DEBUG(dbgs() << ", v=" << Visited); } /// calcCompactRegion - Compute the set of edge bundles that should be live @@ -1334,7 +1336,7 @@ bool RAGreedy::calcCompactRegion(GlobalSplitCandidate &Cand) { // Compact regions don't correspond to any physreg. Cand.reset(IntfCache, 0); - DEBUG(dbgs() << "Compact region bundles"); + LLVM_DEBUG(dbgs() << "Compact region bundles"); // Use the spill placer to determine the live bundles. GrowRegion pretends // that all the through blocks have interference when PhysReg is unset. @@ -1343,7 +1345,7 @@ bool RAGreedy::calcCompactRegion(GlobalSplitCandidate &Cand) { // The static split cost will be zero since Cand.Intf reports no interference. BlockFrequency Cost; if (!addSplitConstraints(Cand.Intf, Cost)) { - DEBUG(dbgs() << ", none.\n"); + LLVM_DEBUG(dbgs() << ", none.\n"); return false; } @@ -1351,11 +1353,11 @@ bool RAGreedy::calcCompactRegion(GlobalSplitCandidate &Cand) { SpillPlacer->finish(); if (!Cand.LiveBundles.any()) { - DEBUG(dbgs() << ", none.\n"); + LLVM_DEBUG(dbgs() << ", none.\n"); return false; } - DEBUG({ + LLVM_DEBUG({ for (int i : Cand.LiveBundles.set_bits()) dbgs() << " EB#" << i; dbgs() << ".\n"; @@ -1633,7 +1635,8 @@ void RAGreedy::splitAroundRegion(LiveRangeEdit &LREdit, // These are the intervals created for new global ranges. We may create more // intervals for local ranges. const unsigned NumGlobalIntvs = LREdit.size(); - DEBUG(dbgs() << "splitAroundRegion with " << NumGlobalIntvs << " globals.\n"); + LLVM_DEBUG(dbgs() << "splitAroundRegion with " << NumGlobalIntvs + << " globals.\n"); assert(NumGlobalIntvs && "No global intervals configured"); // Isolate even single instructions when dealing with a proper sub-class. @@ -1670,7 +1673,7 @@ void RAGreedy::splitAroundRegion(LiveRangeEdit &LREdit, // Create separate intervals for isolated blocks with multiple uses. if (!IntvIn && !IntvOut) { - DEBUG(dbgs() << printMBBReference(*BI.MBB) << " isolated.\n"); + LLVM_DEBUG(dbgs() << printMBBReference(*BI.MBB) << " isolated.\n"); if (SA->shouldSplitSingleBlock(BI, SingleInstrs)) SE->splitSingleBlock(BI); continue; @@ -1752,8 +1755,8 @@ void RAGreedy::splitAroundRegion(LiveRangeEdit &LREdit, // blocks is strictly decreasing. if (IntvMap[i] < NumGlobalIntvs) { if (SA->countLiveBlocks(&Reg) >= OrigBlocks) { - DEBUG(dbgs() << "Main interval covers the same " << OrigBlocks - << " blocks as original.\n"); + LLVM_DEBUG(dbgs() << "Main interval covers the same " << OrigBlocks + << " blocks as original.\n"); // Don't allow repeated splitting as a safe guard against looping. setStage(Reg, RS_Split2); } @@ -1784,8 +1787,8 @@ unsigned RAGreedy::tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order, // No benefit from the compact region, our fallback will be per-block // splitting. Make sure we find a solution that is cheaper than spilling. BestCost = SpillCost; - DEBUG(dbgs() << "Cost of isolating all blocks = "; - MBFI->printBlockFreq(dbgs(), BestCost) << '\n'); + LLVM_DEBUG(dbgs() << "Cost of isolating all blocks = "; + MBFI->printBlockFreq(dbgs(), BestCost) << '\n'); } bool CanCauseEvictionChain = false; @@ -1848,13 +1851,13 @@ unsigned RAGreedy::calculateRegionSplitCost(LiveInterval &VirtReg, SpillPlacer->prepare(Cand.LiveBundles); BlockFrequency Cost; if (!addSplitConstraints(Cand.Intf, Cost)) { - DEBUG(dbgs() << printReg(PhysReg, TRI) << "\tno positive bundles\n"); + LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << "\tno positive bundles\n"); continue; } - DEBUG(dbgs() << printReg(PhysReg, TRI) << "\tstatic = "; - MBFI->printBlockFreq(dbgs(), Cost)); + LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << "\tstatic = "; + MBFI->printBlockFreq(dbgs(), Cost)); if (Cost >= BestCost) { - DEBUG({ + LLVM_DEBUG({ if (BestCand == NoCand) dbgs() << " worse than no bundles\n"; else @@ -1869,15 +1872,15 @@ unsigned RAGreedy::calculateRegionSplitCost(LiveInterval &VirtReg, // No live bundles, defer to splitSingleBlocks(). if (!Cand.LiveBundles.any()) { - DEBUG(dbgs() << " no bundles.\n"); + LLVM_DEBUG(dbgs() << " no bundles.\n"); continue; } bool HasEvictionChain = false; Cost += calcGlobalSplitCost(Cand, Order, &HasEvictionChain); - DEBUG({ - dbgs() << ", total = "; MBFI->printBlockFreq(dbgs(), Cost) - << " with bundles"; + LLVM_DEBUG({ + dbgs() << ", total = "; + MBFI->printBlockFreq(dbgs(), Cost) << " with bundles"; for (int i : Cand.LiveBundles.set_bits()) dbgs() << " EB#" << i; dbgs() << ".\n"; @@ -1896,11 +1899,11 @@ unsigned RAGreedy::calculateRegionSplitCost(LiveInterval &VirtReg, if (CanCauseEvictionChain && BestCand != NoCand) { // See splitCanCauseEvictionChain for detailed description of bad // eviction chain scenarios. - DEBUG(dbgs() << "Best split candidate of vreg " - << printReg(VirtReg.reg, TRI) << " may "); + LLVM_DEBUG(dbgs() << "Best split candidate of vreg " + << printReg(VirtReg.reg, TRI) << " may "); if (!(*CanCauseEvictionChain)) - DEBUG(dbgs() << "not "); - DEBUG(dbgs() << "cause bad eviction chain\n"); + LLVM_DEBUG(dbgs() << "not "); + LLVM_DEBUG(dbgs() << "cause bad eviction chain\n"); } return BestCand; @@ -1923,8 +1926,8 @@ unsigned RAGreedy::doRegionSplit(LiveInterval &VirtReg, unsigned BestCand, if (unsigned B = Cand.getBundles(BundleCand, BestCand)) { UsedCands.push_back(BestCand); Cand.IntvIdx = SE->openIntv(); - DEBUG(dbgs() << "Split for " << printReg(Cand.PhysReg, TRI) << " in " - << B << " bundles, intv " << Cand.IntvIdx << ".\n"); + LLVM_DEBUG(dbgs() << "Split for " << printReg(Cand.PhysReg, TRI) << " in " + << B << " bundles, intv " << Cand.IntvIdx << ".\n"); (void)B; } } @@ -1936,8 +1939,8 @@ unsigned RAGreedy::doRegionSplit(LiveInterval &VirtReg, unsigned BestCand, if (unsigned B = Cand.getBundles(BundleCand, 0)) { UsedCands.push_back(0); Cand.IntvIdx = SE->openIntv(); - DEBUG(dbgs() << "Split for compact region in " << B << " bundles, intv " - << Cand.IntvIdx << ".\n"); + LLVM_DEBUG(dbgs() << "Split for compact region in " << B + << " bundles, intv " << Cand.IntvIdx << ".\n"); (void)B; } } @@ -2036,7 +2039,8 @@ RAGreedy::tryInstructionSplit(LiveInterval &VirtReg, AllocationOrder &Order, if (Uses.size() <= 1) return 0; - DEBUG(dbgs() << "Split around " << Uses.size() << " individual instrs.\n"); + LLVM_DEBUG(dbgs() << "Split around " << Uses.size() + << " individual instrs.\n"); const TargetRegisterClass *SuperRC = TRI->getLargestLegalSuperClass(CurRC, *MF); @@ -2051,7 +2055,7 @@ RAGreedy::tryInstructionSplit(LiveInterval &VirtReg, AllocationOrder &Order, SuperRCNumAllocatableRegs == getNumAllocatableRegsForConstraints(MI, VirtReg.reg, SuperRC, TII, TRI, RCI)) { - DEBUG(dbgs() << " skip:\t" << Uses[i] << '\t' << *MI); + LLVM_DEBUG(dbgs() << " skip:\t" << Uses[i] << '\t' << *MI); continue; } SE->openIntv(); @@ -2061,7 +2065,7 @@ RAGreedy::tryInstructionSplit(LiveInterval &VirtReg, AllocationOrder &Order, } if (LREdit.empty()) { - DEBUG(dbgs() << "All uses were copies.\n"); + LLVM_DEBUG(dbgs() << "All uses were copies.\n"); return 0; } @@ -2179,7 +2183,7 @@ unsigned RAGreedy::tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order, return 0; const unsigned NumGaps = Uses.size()-1; - DEBUG({ + LLVM_DEBUG({ dbgs() << "tryLocalSplit: "; for (unsigned i = 0, e = Uses.size(); i != e; ++i) dbgs() << ' ' << Uses[i]; @@ -2192,7 +2196,7 @@ unsigned RAGreedy::tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order, if (Matrix->checkRegMaskInterference(VirtReg)) { // Get regmask slots for the whole block. ArrayRef<SlotIndex> RMS = LIS->getRegMaskSlotsInBlock(BI.MBB->getNumber()); - DEBUG(dbgs() << RMS.size() << " regmasks in block:"); + LLVM_DEBUG(dbgs() << RMS.size() << " regmasks in block:"); // Constrain to VirtReg's live range. unsigned ri = std::lower_bound(RMS.begin(), RMS.end(), Uses.front().getRegSlot()) - RMS.begin(); @@ -2206,14 +2210,15 @@ unsigned RAGreedy::tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order, // overlap the live range. if (SlotIndex::isSameInstr(Uses[i+1], RMS[ri]) && i+1 == NumGaps) break; - DEBUG(dbgs() << ' ' << RMS[ri] << ':' << Uses[i] << '-' << Uses[i+1]); + LLVM_DEBUG(dbgs() << ' ' << RMS[ri] << ':' << Uses[i] << '-' + << Uses[i + 1]); RegMaskGaps.push_back(i); // Advance ri to the next gap. A regmask on one of the uses counts in // both gaps. while (ri != re && SlotIndex::isEarlierInstr(RMS[ri], Uses[i+1])) ++ri; } - DEBUG(dbgs() << '\n'); + LLVM_DEBUG(dbgs() << '\n'); } // Since we allow local split results to be split again, there is a risk of @@ -2272,13 +2277,12 @@ unsigned RAGreedy::tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order, const bool LiveBefore = SplitBefore != 0 || BI.LiveIn; const bool LiveAfter = SplitAfter != NumGaps || BI.LiveOut; - DEBUG(dbgs() << printReg(PhysReg, TRI) << ' ' - << Uses[SplitBefore] << '-' << Uses[SplitAfter] - << " i=" << MaxGap); + LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << ' ' << Uses[SplitBefore] + << '-' << Uses[SplitAfter] << " i=" << MaxGap); // Stop before the interval gets so big we wouldn't be making progress. if (!LiveBefore && !LiveAfter) { - DEBUG(dbgs() << " all\n"); + LLVM_DEBUG(dbgs() << " all\n"); break; } // Should the interval be extended or shrunk? @@ -2303,12 +2307,12 @@ unsigned RAGreedy::tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order, 1); // Would this split be possible to allocate? // Never allocate all gaps, we wouldn't be making progress. - DEBUG(dbgs() << " w=" << EstWeight); + LLVM_DEBUG(dbgs() << " w=" << EstWeight); if (EstWeight * Hysteresis >= MaxGap) { Shrink = false; float Diff = EstWeight - MaxGap; if (Diff > BestDiff) { - DEBUG(dbgs() << " (best)"); + LLVM_DEBUG(dbgs() << " (best)"); BestDiff = Hysteresis * Diff; BestBefore = SplitBefore; BestAfter = SplitAfter; @@ -2319,7 +2323,7 @@ unsigned RAGreedy::tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order, // Try to shrink. if (Shrink) { if (++SplitBefore < SplitAfter) { - DEBUG(dbgs() << " shrink\n"); + LLVM_DEBUG(dbgs() << " shrink\n"); // Recompute the max when necessary. if (GapWeight[SplitBefore - 1] >= MaxGap) { MaxGap = GapWeight[SplitBefore]; @@ -2333,11 +2337,11 @@ unsigned RAGreedy::tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order, // Try to extend the interval. if (SplitAfter >= NumGaps) { - DEBUG(dbgs() << " end\n"); + LLVM_DEBUG(dbgs() << " end\n"); break; } - DEBUG(dbgs() << " extend\n"); + LLVM_DEBUG(dbgs() << " extend\n"); MaxGap = std::max(MaxGap, GapWeight[SplitAfter++]); } } @@ -2346,9 +2350,9 @@ unsigned RAGreedy::tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order, if (BestBefore == NumGaps) return 0; - DEBUG(dbgs() << "Best local split range: " << Uses[BestBefore] - << '-' << Uses[BestAfter] << ", " << BestDiff - << ", " << (BestAfter - BestBefore + 1) << " instrs\n"); + LLVM_DEBUG(dbgs() << "Best local split range: " << Uses[BestBefore] << '-' + << Uses[BestAfter] << ", " << BestDiff << ", " + << (BestAfter - BestBefore + 1) << " instrs\n"); LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats); SE->reset(LREdit); @@ -2368,14 +2372,14 @@ unsigned RAGreedy::tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order, bool LiveAfter = BestAfter != NumGaps || BI.LiveOut; unsigned NewGaps = LiveBefore + BestAfter - BestBefore + LiveAfter; if (NewGaps >= NumGaps) { - DEBUG(dbgs() << "Tagging non-progress ranges: "); + LLVM_DEBUG(dbgs() << "Tagging non-progress ranges: "); assert(!ProgressRequired && "Didn't make progress when it was required."); for (unsigned i = 0, e = IntvMap.size(); i != e; ++i) if (IntvMap[i] == 1) { setStage(LIS->getInterval(LREdit.get(i)), RS_Split2); - DEBUG(dbgs() << printReg(LREdit.get(i))); + LLVM_DEBUG(dbgs() << printReg(LREdit.get(i))); } - DEBUG(dbgs() << '\n'); + LLVM_DEBUG(dbgs() << '\n'); } ++NumLocalSplits; @@ -2468,7 +2472,7 @@ RAGreedy::mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg, // chances are one would not be recolorable. if (Q.collectInterferingVRegs(LastChanceRecoloringMaxInterference) >= LastChanceRecoloringMaxInterference && !ExhaustiveSearch) { - DEBUG(dbgs() << "Early abort: too many interferences.\n"); + LLVM_DEBUG(dbgs() << "Early abort: too many interferences.\n"); CutOffInfo |= CO_Interf; return false; } @@ -2482,7 +2486,8 @@ RAGreedy::mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg, MRI->getRegClass(Intf->reg) == CurRC) && !(hasTiedDef(MRI, VirtReg.reg) && !hasTiedDef(MRI, Intf->reg))) || FixedRegisters.count(Intf->reg)) { - DEBUG(dbgs() << "Early abort: the interference is not recolorable.\n"); + LLVM_DEBUG( + dbgs() << "Early abort: the interference is not recolorable.\n"); return false; } RecoloringCandidates.insert(Intf); @@ -2535,7 +2540,7 @@ unsigned RAGreedy::tryLastChanceRecoloring(LiveInterval &VirtReg, SmallVectorImpl<unsigned> &NewVRegs, SmallVirtRegSet &FixedRegisters, unsigned Depth) { - DEBUG(dbgs() << "Try last chance recoloring for " << VirtReg << '\n'); + LLVM_DEBUG(dbgs() << "Try last chance recoloring for " << VirtReg << '\n'); // Ranges must be Done. assert((getStage(VirtReg) >= RS_Done || !VirtReg.isSpillable()) && "Last chance recoloring should really be last chance"); @@ -2544,7 +2549,7 @@ unsigned RAGreedy::tryLastChanceRecoloring(LiveInterval &VirtReg, // for target with hundreds of registers. // Indeed, in that case we may want to cut the search space earlier. if (Depth >= LastChanceRecoloringMaxDepth && !ExhaustiveSearch) { - DEBUG(dbgs() << "Abort because max depth has been reached.\n"); + LLVM_DEBUG(dbgs() << "Abort because max depth has been reached.\n"); CutOffInfo |= CO_Depth; return ~0u; } @@ -2561,8 +2566,8 @@ unsigned RAGreedy::tryLastChanceRecoloring(LiveInterval &VirtReg, Order.rewind(); while (unsigned PhysReg = Order.next()) { - DEBUG(dbgs() << "Try to assign: " << VirtReg << " to " - << printReg(PhysReg, TRI) << '\n'); + LLVM_DEBUG(dbgs() << "Try to assign: " << VirtReg << " to " + << printReg(PhysReg, TRI) << '\n'); RecoloringCandidates.clear(); VirtRegToPhysReg.clear(); CurrentNewVRegs.clear(); @@ -2570,7 +2575,8 @@ unsigned RAGreedy::tryLastChanceRecoloring(LiveInterval &VirtReg, // It is only possible to recolor virtual register interference. if (Matrix->checkInterference(VirtReg, PhysReg) > LiveRegMatrix::IK_VirtReg) { - DEBUG(dbgs() << "Some interferences are not with virtual registers.\n"); + LLVM_DEBUG( + dbgs() << "Some interferences are not with virtual registers.\n"); continue; } @@ -2579,7 +2585,7 @@ unsigned RAGreedy::tryLastChanceRecoloring(LiveInterval &VirtReg, // the interferences. if (!mayRecolorAllInterferences(PhysReg, VirtReg, RecoloringCandidates, FixedRegisters)) { - DEBUG(dbgs() << "Some interferences cannot be recolored.\n"); + LLVM_DEBUG(dbgs() << "Some interferences cannot be recolored.\n"); continue; } @@ -2621,8 +2627,8 @@ unsigned RAGreedy::tryLastChanceRecoloring(LiveInterval &VirtReg, return PhysReg; } - DEBUG(dbgs() << "Fail to assign: " << VirtReg << " to " - << printReg(PhysReg, TRI) << '\n'); + LLVM_DEBUG(dbgs() << "Fail to assign: " << VirtReg << " to " + << printReg(PhysReg, TRI) << '\n'); // The recoloring attempt failed, undo the changes. FixedRegisters = SaveFixedRegisters; @@ -2669,7 +2675,7 @@ bool RAGreedy::tryRecoloringCandidates(PQueue &RecoloringQueue, unsigned Depth) { while (!RecoloringQueue.empty()) { LiveInterval *LI = dequeue(RecoloringQueue); - DEBUG(dbgs() << "Try to recolor: " << *LI << '\n'); + LLVM_DEBUG(dbgs() << "Try to recolor: " << *LI << '\n'); unsigned PhysReg; PhysReg = selectOrSplitImpl(*LI, NewVRegs, FixedRegisters, Depth + 1); // When splitting happens, the live-range may actually be empty. @@ -2681,11 +2687,12 @@ bool RAGreedy::tryRecoloringCandidates(PQueue &RecoloringQueue, if (!PhysReg) { assert(LI->empty() && "Only empty live-range do not require a register"); - DEBUG(dbgs() << "Recoloring of " << *LI << " succeeded. Empty LI.\n"); + LLVM_DEBUG(dbgs() << "Recoloring of " << *LI + << " succeeded. Empty LI.\n"); continue; } - DEBUG(dbgs() << "Recoloring of " << *LI - << " succeeded with: " << printReg(PhysReg, TRI) << '\n'); + LLVM_DEBUG(dbgs() << "Recoloring of " << *LI + << " succeeded with: " << printReg(PhysReg, TRI) << '\n'); Matrix->assign(*LI, PhysReg); FixedRegisters.insert(LI->reg); @@ -2852,8 +2859,8 @@ void RAGreedy::tryHintRecoloring(LiveInterval &VirtReg) { Visited.insert(Reg); RecoloringCandidates.push_back(Reg); - DEBUG(dbgs() << "Trying to reconcile hints for: " << printReg(Reg, TRI) << '(' - << printReg(PhysReg, TRI) << ")\n"); + LLVM_DEBUG(dbgs() << "Trying to reconcile hints for: " << printReg(Reg, TRI) + << '(' << printReg(PhysReg, TRI) << ")\n"); do { Reg = RecoloringCandidates.pop_back_val(); @@ -2874,8 +2881,8 @@ void RAGreedy::tryHintRecoloring(LiveInterval &VirtReg) { Matrix->checkInterference(LI, PhysReg))) continue; - DEBUG(dbgs() << printReg(Reg, TRI) << '(' << printReg(CurrPhys, TRI) - << ") is recolorable.\n"); + LLVM_DEBUG(dbgs() << printReg(Reg, TRI) << '(' << printReg(CurrPhys, TRI) + << ") is recolorable.\n"); // Gather the hint info. Info.clear(); @@ -2883,19 +2890,20 @@ void RAGreedy::tryHintRecoloring(LiveInterval &VirtReg) { // Check if recoloring the live-range will increase the cost of the // non-identity copies. if (CurrPhys != PhysReg) { - DEBUG(dbgs() << "Checking profitability:\n"); + LLVM_DEBUG(dbgs() << "Checking profitability:\n"); BlockFrequency OldCopiesCost = getBrokenHintFreq(Info, CurrPhys); BlockFrequency NewCopiesCost = getBrokenHintFreq(Info, PhysReg); - DEBUG(dbgs() << "Old Cost: " << OldCopiesCost.getFrequency() - << "\nNew Cost: " << NewCopiesCost.getFrequency() << '\n'); + LLVM_DEBUG(dbgs() << "Old Cost: " << OldCopiesCost.getFrequency() + << "\nNew Cost: " << NewCopiesCost.getFrequency() + << '\n'); if (OldCopiesCost < NewCopiesCost) { - DEBUG(dbgs() << "=> Not profitable.\n"); + LLVM_DEBUG(dbgs() << "=> Not profitable.\n"); continue; } // At this point, the cost is either cheaper or equal. If it is // equal, we consider this is profitable because it may expose // more recoloring opportunities. - DEBUG(dbgs() << "=> Profitable.\n"); + LLVM_DEBUG(dbgs() << "=> Profitable.\n"); // Recolor the live-range. Matrix->unassign(LI); Matrix->assign(LI, PhysReg); @@ -2983,8 +2991,8 @@ unsigned RAGreedy::selectOrSplitImpl(LiveInterval &VirtReg, } LiveRangeStage Stage = getStage(VirtReg); - DEBUG(dbgs() << StageName[Stage] - << " Cascade " << ExtraRegInfo[VirtReg.reg].Cascade << '\n'); + LLVM_DEBUG(dbgs() << StageName[Stage] << " Cascade " + << ExtraRegInfo[VirtReg.reg].Cascade << '\n'); // Try to evict a less worthy live range, but only for ranges from the primary // queue. The RS_Split ranges already failed to do this, and they should not @@ -3013,7 +3021,7 @@ unsigned RAGreedy::selectOrSplitImpl(LiveInterval &VirtReg, // This gives a better picture of the interference to split around. if (Stage < RS_Split) { setStage(VirtReg, RS_Split); - DEBUG(dbgs() << "wait for second round\n"); + LLVM_DEBUG(dbgs() << "wait for second round\n"); NewVRegs.push_back(VirtReg.reg); return 0; } @@ -3042,7 +3050,7 @@ unsigned RAGreedy::selectOrSplitImpl(LiveInterval &VirtReg, // We would need a deep integration with the spiller to do the // right thing here. Anyway, that is still good for early testing. setStage(VirtReg, RS_Memory); - DEBUG(dbgs() << "Do as if this register is in memory\n"); + LLVM_DEBUG(dbgs() << "Do as if this register is in memory\n"); NewVRegs.push_back(VirtReg.reg); } else { NamedRegionTimer T("spill", "Spiller", TimerGroupName, @@ -3128,8 +3136,8 @@ void RAGreedy::reportNumberOfSplillsReloads(MachineLoop *L, unsigned &Reloads, } bool RAGreedy::runOnMachineFunction(MachineFunction &mf) { - DEBUG(dbgs() << "********** GREEDY REGISTER ALLOCATION **********\n" - << "********** Function: " << mf.getName() << '\n'); + LLVM_DEBUG(dbgs() << "********** GREEDY REGISTER ALLOCATION **********\n" + << "********** Function: " << mf.getName() << '\n'); MF = &mf; TRI = MF->getSubtarget().getRegisterInfo(); @@ -3164,7 +3172,7 @@ bool RAGreedy::runOnMachineFunction(MachineFunction &mf) { calculateSpillWeightsAndHints(*LIS, mf, VRM, *Loops, *MBFI); - DEBUG(LIS->dump()); + LLVM_DEBUG(LIS->dump()); SA.reset(new SplitAnalysis(*VRM, *LIS, *Loops)); SE.reset(new SplitEditor(*SA, *AA, *LIS, *VRM, *DomTree, *MBFI)); diff --git a/llvm/lib/CodeGen/RegAllocPBQP.cpp b/llvm/lib/CodeGen/RegAllocPBQP.cpp index 879330a0b4d..c19001c8403 100644 --- a/llvm/lib/CodeGen/RegAllocPBQP.cpp +++ b/llvm/lib/CodeGen/RegAllocPBQP.cpp @@ -685,8 +685,8 @@ void RegAllocPBQP::spillVReg(unsigned VReg, const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); (void)TRI; - DEBUG(dbgs() << "VREG " << printReg(VReg, &TRI) << " -> SPILLED (Cost: " - << LRE.getParent().weight << ", New vregs: "); + LLVM_DEBUG(dbgs() << "VREG " << printReg(VReg, &TRI) << " -> SPILLED (Cost: " + << LRE.getParent().weight << ", New vregs: "); // Copy any newly inserted live intervals into the list of regs to // allocate. @@ -694,11 +694,11 @@ void RegAllocPBQP::spillVReg(unsigned VReg, I != E; ++I) { const LiveInterval &LI = LIS.getInterval(*I); assert(!LI.empty() && "Empty spill range."); - DEBUG(dbgs() << printReg(LI.reg, &TRI) << " "); + LLVM_DEBUG(dbgs() << printReg(LI.reg, &TRI) << " "); VRegsToAlloc.insert(LI.reg); } - DEBUG(dbgs() << ")\n"); + LLVM_DEBUG(dbgs() << ")\n"); } bool RegAllocPBQP::mapPBQPToRegAlloc(const PBQPRAGraph &G, @@ -724,8 +724,8 @@ bool RegAllocPBQP::mapPBQPToRegAlloc(const PBQPRAGraph &G, if (AllocOption != PBQP::RegAlloc::getSpillOptionIdx()) { unsigned PReg = G.getNodeMetadata(NId).getAllowedRegs()[AllocOption - 1]; - DEBUG(dbgs() << "VREG " << printReg(VReg, &TRI) << " -> " - << TRI.getName(PReg) << "\n"); + LLVM_DEBUG(dbgs() << "VREG " << printReg(VReg, &TRI) << " -> " + << TRI.getName(PReg) << "\n"); assert(PReg != 0 && "Invalid preg selected."); VRM.assignVirt2Phys(VReg, PReg); } else { @@ -801,7 +801,7 @@ bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) { MF.getRegInfo().freezeReservedRegs(MF); - DEBUG(dbgs() << "PBQP Register Allocating for " << MF.getName() << "\n"); + LLVM_DEBUG(dbgs() << "PBQP Register Allocating for " << MF.getName() << "\n"); // Allocator main loop: // @@ -836,7 +836,7 @@ bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) { unsigned Round = 0; while (!PBQPAllocComplete) { - DEBUG(dbgs() << " PBQP Regalloc round " << Round << ":\n"); + LLVM_DEBUG(dbgs() << " PBQP Regalloc round " << Round << ":\n"); PBQPRAGraph G(PBQPRAGraph::GraphMetadata(MF, LIS, MBFI)); initializeGraph(G, VRM, *VRegSpiller); @@ -850,8 +850,8 @@ bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) { ".pbqpgraph"; std::error_code EC; raw_fd_ostream OS(GraphFileName, EC, sys::fs::F_Text); - DEBUG(dbgs() << "Dumping graph for round " << Round << " to \"" - << GraphFileName << "\"\n"); + LLVM_DEBUG(dbgs() << "Dumping graph for round " << Round << " to \"" + << GraphFileName << "\"\n"); G.dump(OS); } #endif @@ -868,7 +868,7 @@ bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) { VRegsToAlloc.clear(); EmptyIntervalVRegs.clear(); - DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << VRM << "\n"); + LLVM_DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << VRM << "\n"); return true; } diff --git a/llvm/lib/CodeGen/RegUsageInfoCollector.cpp b/llvm/lib/CodeGen/RegUsageInfoCollector.cpp index d934fa9f57d..6a0f26b346c 100644 --- a/llvm/lib/CodeGen/RegUsageInfoCollector.cpp +++ b/llvm/lib/CodeGen/RegUsageInfoCollector.cpp @@ -83,9 +83,9 @@ bool RegUsageInfoCollector::runOnMachineFunction(MachineFunction &MF) { const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); const TargetMachine &TM = MF.getTarget(); - DEBUG(dbgs() << " -------------------- " << getPassName() - << " -------------------- \n"); - DEBUG(dbgs() << "Function Name : " << MF.getName() << "\n"); + LLVM_DEBUG(dbgs() << " -------------------- " << getPassName() + << " -------------------- \n"); + LLVM_DEBUG(dbgs() << "Function Name : " << MF.getName() << "\n"); std::vector<uint32_t> RegMask; @@ -101,7 +101,7 @@ bool RegUsageInfoCollector::runOnMachineFunction(MachineFunction &MF) { PRUI->setTargetMachine(&TM); - DEBUG(dbgs() << "Clobbered Registers: "); + LLVM_DEBUG(dbgs() << "Clobbered Registers: "); const BitVector &UsedPhysRegsMask = MRI->getUsedPhysRegsMask(); auto SetRegAsDefined = [&RegMask] (unsigned Reg) { @@ -134,15 +134,15 @@ bool RegUsageInfoCollector::runOnMachineFunction(MachineFunction &MF) { } } else { ++NumCSROpt; - DEBUG(dbgs() << MF.getName() - << " function optimized for not having CSR.\n"); + LLVM_DEBUG(dbgs() << MF.getName() + << " function optimized for not having CSR.\n"); } for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) if (MachineOperand::clobbersPhysReg(&(RegMask[0]), PReg)) - DEBUG(dbgs() << printReg(PReg, TRI) << " "); + LLVM_DEBUG(dbgs() << printReg(PReg, TRI) << " "); - DEBUG(dbgs() << " \n----------------------------------------\n"); + LLVM_DEBUG(dbgs() << " \n----------------------------------------\n"); PRUI->storeUpdateRegUsageInfo(&F, std::move(RegMask)); diff --git a/llvm/lib/CodeGen/RegUsageInfoPropagate.cpp b/llvm/lib/CodeGen/RegUsageInfoPropagate.cpp index 5b12d00e126..7eaeea2eb2c 100644 --- a/llvm/lib/CodeGen/RegUsageInfoPropagate.cpp +++ b/llvm/lib/CodeGen/RegUsageInfoPropagate.cpp @@ -105,9 +105,9 @@ bool RegUsageInfoPropagationPass::runOnMachineFunction(MachineFunction &MF) { const Module *M = MF.getFunction().getParent(); PhysicalRegisterUsageInfo *PRUI = &getAnalysis<PhysicalRegisterUsageInfo>(); - DEBUG(dbgs() << " ++++++++++++++++++++ " << getPassName() - << " ++++++++++++++++++++ \n"); - DEBUG(dbgs() << "MachineFunction : " << MF.getName() << "\n"); + LLVM_DEBUG(dbgs() << " ++++++++++++++++++++ " << getPassName() + << " ++++++++++++++++++++ \n"); + LLVM_DEBUG(dbgs() << "MachineFunction : " << MF.getName() << "\n"); const MachineFrameInfo &MFI = MF.getFrameInfo(); if (!MFI.hasCalls() && !MFI.hasTailCall()) @@ -119,9 +119,10 @@ bool RegUsageInfoPropagationPass::runOnMachineFunction(MachineFunction &MF) { for (MachineInstr &MI : MBB) { if (!MI.isCall()) continue; - DEBUG(dbgs() - << "Call Instruction Before Register Usage Info Propagation : \n"); - DEBUG(dbgs() << MI << "\n"); + LLVM_DEBUG( + dbgs() + << "Call Instruction Before Register Usage Info Propagation : \n"); + LLVM_DEBUG(dbgs() << MI << "\n"); auto UpdateRegMask = [&](const Function *F) { const auto *RegMask = PRUI->getRegUsageInfo(F); @@ -134,15 +135,17 @@ bool RegUsageInfoPropagationPass::runOnMachineFunction(MachineFunction &MF) { if (const Function *F = findCalledFunction(*M, MI)) { UpdateRegMask(F); } else { - DEBUG(dbgs() << "Failed to find call target function\n"); + LLVM_DEBUG(dbgs() << "Failed to find call target function\n"); } - DEBUG(dbgs() << "Call Instruction After Register Usage Info Propagation : " - << MI << '\n'); + LLVM_DEBUG( + dbgs() << "Call Instruction After Register Usage Info Propagation : " + << MI << '\n'); } } - DEBUG(dbgs() << " +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++" - "++++++ \n"); + LLVM_DEBUG( + dbgs() << " +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++" + "++++++ \n"); return Changed; } diff --git a/llvm/lib/CodeGen/RegisterClassInfo.cpp b/llvm/lib/CodeGen/RegisterClassInfo.cpp index 5df32db4d99..add8faec97d 100644 --- a/llvm/lib/CodeGen/RegisterClassInfo.cpp +++ b/llvm/lib/CodeGen/RegisterClassInfo.cpp @@ -151,7 +151,7 @@ void RegisterClassInfo::compute(const TargetRegisterClass *RC) const { RCI.MinCost = uint8_t(MinCost); RCI.LastCostChange = LastCostChange; - DEBUG({ + LLVM_DEBUG({ dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ") = ["; for (unsigned I = 0; I != RCI.NumRegs; ++I) dbgs() << ' ' << printReg(RCI.Order[I], TRI); diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp index a9565fae8f1..db5258e6270 100644 --- a/llvm/lib/CodeGen/RegisterCoalescer.cpp +++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp @@ -568,7 +568,7 @@ bool RegisterCoalescer::adjustCopiesBackFrom(const CoalescerPair &CP, // in IntB, we can merge them. if (ValS+1 != BS) return false; - DEBUG(dbgs() << "Extending: " << printReg(IntB.reg, TRI)); + LLVM_DEBUG(dbgs() << "Extending: " << printReg(IntB.reg, TRI)); SlotIndex FillerStart = ValS->end, FillerEnd = BS->start; // We are about to delete CopyMI, so need to remove it as the 'instruction @@ -594,7 +594,7 @@ bool RegisterCoalescer::adjustCopiesBackFrom(const CoalescerPair &CP, S.MergeValueNumberInto(SubBValNo, SubValSNo); } - DEBUG(dbgs() << " result = " << IntB << '\n'); + LLVM_DEBUG(dbgs() << " result = " << IntB << '\n'); // If the source instruction was killing the source register before the // merge, unset the isKill marker given the live range has been extended. @@ -742,8 +742,8 @@ bool RegisterCoalescer::removeCopyByCommutingDef(const CoalescerPair &CP, return false; } - DEBUG(dbgs() << "\tremoveCopyByCommutingDef: " << AValNo->def << '\t' - << *DefMI); + LLVM_DEBUG(dbgs() << "\tremoveCopyByCommutingDef: " << AValNo->def << '\t' + << *DefMI); // At this point we have decided that it is legal to do this // transformation. Start by commuting the instruction. @@ -812,7 +812,7 @@ bool RegisterCoalescer::removeCopyByCommutingDef(const CoalescerPair &CP, VNInfo *DVNI = IntB.getVNInfoAt(DefIdx); if (!DVNI) continue; - DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI); + LLVM_DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI); assert(DVNI->def == DefIdx); BValNo = IntB.MergeValueNumberInto(DVNI, BValNo); for (LiveInterval::SubRange &S : IntB.subranges()) { @@ -853,11 +853,11 @@ bool RegisterCoalescer::removeCopyByCommutingDef(const CoalescerPair &CP, BValNo->def = AValNo->def; addSegmentsWithValNo(IntB, BValNo, IntA, AValNo); - DEBUG(dbgs() << "\t\textended: " << IntB << '\n'); + LLVM_DEBUG(dbgs() << "\t\textended: " << IntB << '\n'); LIS->removeVRegDefAt(IntA, AValNo->def); - DEBUG(dbgs() << "\t\ttrimmed: " << IntA << '\n'); + LLVM_DEBUG(dbgs() << "\t\ttrimmed: " << IntA << '\n'); ++numCommutes; return true; } @@ -1003,8 +1003,8 @@ bool RegisterCoalescer::removePartialRedundancy(const CoalescerPair &CP, return false; } - DEBUG(dbgs() << "\tremovePartialRedundancy: Move the copy to " - << printMBBReference(*CopyLeftBB) << '\t' << CopyMI); + LLVM_DEBUG(dbgs() << "\tremovePartialRedundancy: Move the copy to " + << printMBBReference(*CopyLeftBB) << '\t' << CopyMI); // Insert new copy to CopyLeftBB. MachineInstr *NewCopyMI = BuildMI(*CopyLeftBB, InsPos, CopyMI.getDebugLoc(), @@ -1021,8 +1021,8 @@ bool RegisterCoalescer::removePartialRedundancy(const CoalescerPair &CP, // the deleted list. ErasedInstrs.erase(NewCopyMI); } else { - DEBUG(dbgs() << "\tremovePartialRedundancy: Remove the copy from " - << printMBBReference(MBB) << '\t' << CopyMI); + LLVM_DEBUG(dbgs() << "\tremovePartialRedundancy: Remove the copy from " + << printMBBReference(MBB) << '\t' << CopyMI); } // Remove CopyMI. @@ -1277,8 +1277,9 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP, bool UpdatedSubRanges = false; for (LiveInterval::SubRange &SR : DstInt.subranges()) { if ((SR.LaneMask & DstMask).none()) { - DEBUG(dbgs() << "Removing undefined SubRange " - << PrintLaneMask(SR.LaneMask) << " : " << SR << "\n"); + LLVM_DEBUG(dbgs() + << "Removing undefined SubRange " + << PrintLaneMask(SR.LaneMask) << " : " << SR << "\n"); // VNI is in ValNo - remove any segments in this SubRange that have this ValNo if (VNInfo *RmValNo = SR.getVNInfoAt(CurrIdx.getRegSlot())) { SR.removeValNo(RmValNo); @@ -1335,7 +1336,7 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP, LR->createDeadDef(NewMIIdx.getRegSlot(), LIS->getVNInfoAllocator()); } - DEBUG(dbgs() << "Remat: " << NewMI); + LLVM_DEBUG(dbgs() << "Remat: " << NewMI); ++NumReMats; // The source interval can become smaller because we removed a use. @@ -1350,7 +1351,7 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP, // Move the debug value directly after the def of the rematerialized // value in DstReg. MBB->splice(std::next(NewMI.getIterator()), UseMI->getParent(), UseMI); - DEBUG(dbgs() << "\t\tupdated: " << *UseMI); + LLVM_DEBUG(dbgs() << "\t\tupdated: " << *UseMI); } } eliminateDeadDefs(); @@ -1388,7 +1389,7 @@ bool RegisterCoalescer::eliminateUndefCopy(MachineInstr *CopyMI) { } else if (SrcLI.liveAt(Idx)) return false; - DEBUG(dbgs() << "\tEliminating copy of <undef> value\n"); + LLVM_DEBUG(dbgs() << "\tEliminating copy of <undef> value\n"); // Remove any DstReg segments starting at the instruction. LiveInterval &DstLI = LIS->getInterval(DstReg); @@ -1435,7 +1436,7 @@ bool RegisterCoalescer::eliminateUndefCopy(MachineInstr *CopyMI) { if (isLive) continue; MO.setIsUndef(true); - DEBUG(dbgs() << "\tnew undef: " << UseIdx << '\t' << MI); + LLVM_DEBUG(dbgs() << "\tnew undef: " << UseIdx << '\t' << MI); } // A def of a subregister may be a use of the other subregisters, so @@ -1550,12 +1551,12 @@ void RegisterCoalescer::updateRegDefsUses(unsigned SrcReg, MO.substVirtReg(DstReg, SubIdx, *TRI); } - DEBUG({ - dbgs() << "\t\tupdated: "; - if (!UseMI->isDebugValue()) - dbgs() << LIS->getInstructionIndex(*UseMI) << "\t"; - dbgs() << *UseMI; - }); + LLVM_DEBUG({ + dbgs() << "\t\tupdated: "; + if (!UseMI->isDebugValue()) + dbgs() << LIS->getInstructionIndex(*UseMI) << "\t"; + dbgs() << *UseMI; + }); } } @@ -1564,7 +1565,7 @@ bool RegisterCoalescer::canJoinPhys(const CoalescerPair &CP) { // reserved register. This doesn't increase register pressure, so it is // always beneficial. if (!MRI->isReserved(CP.getDstReg())) { - DEBUG(dbgs() << "\tCan only merge into reserved registers.\n"); + LLVM_DEBUG(dbgs() << "\tCan only merge into reserved registers.\n"); return false; } @@ -1572,17 +1573,18 @@ bool RegisterCoalescer::canJoinPhys(const CoalescerPair &CP) { if (JoinVInt.containsOneValue()) return true; - DEBUG(dbgs() << "\tCannot join complex intervals into reserved register.\n"); + LLVM_DEBUG( + dbgs() << "\tCannot join complex intervals into reserved register.\n"); return false; } bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) { Again = false; - DEBUG(dbgs() << LIS->getInstructionIndex(*CopyMI) << '\t' << *CopyMI); + LLVM_DEBUG(dbgs() << LIS->getInstructionIndex(*CopyMI) << '\t' << *CopyMI); CoalescerPair CP(*TRI); if (!CP.setRegisters(CopyMI)) { - DEBUG(dbgs() << "\tNot coalescable.\n"); + LLVM_DEBUG(dbgs() << "\tNot coalescable.\n"); return false; } @@ -1597,7 +1599,7 @@ bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) { } if (!TRI->shouldCoalesce(CopyMI, SrcRC, SrcIdx, DstRC, DstIdx, CP.getNewRC(), *LIS)) { - DEBUG(dbgs() << "\tSubtarget bailed on coalescing.\n"); + LLVM_DEBUG(dbgs() << "\tSubtarget bailed on coalescing.\n"); return false; } } @@ -1606,7 +1608,7 @@ bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) { // sometimes dead copies slip through, and we can't generate invalid live // ranges. if (!CP.isPhys() && CopyMI->allDefsAreDead()) { - DEBUG(dbgs() << "\tCopy is dead.\n"); + LLVM_DEBUG(dbgs() << "\tCopy is dead.\n"); DeadDefs.push_back(CopyMI); eliminateDeadDefs(); return true; @@ -1623,7 +1625,7 @@ bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) { // When that happens, just join the values and remove the copy. if (CP.getSrcReg() == CP.getDstReg()) { LiveInterval &LI = LIS->getInterval(CP.getSrcReg()); - DEBUG(dbgs() << "\tCopy already coalesced: " << LI << '\n'); + LLVM_DEBUG(dbgs() << "\tCopy already coalesced: " << LI << '\n'); const SlotIndex CopyIdx = LIS->getInstructionIndex(*CopyMI); LiveQueryResult LRQ = LI.Query(CopyIdx); if (VNInfo *DefVNI = LRQ.valueDefined()) { @@ -1640,7 +1642,7 @@ bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) { S.MergeValueNumberInto(SDefVNI, SReadVNI); } } - DEBUG(dbgs() << "\tMerged values: " << LI << '\n'); + LLVM_DEBUG(dbgs() << "\tMerged values: " << LI << '\n'); } deleteInstr(CopyMI); return true; @@ -1648,9 +1650,9 @@ bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) { // Enforce policies. if (CP.isPhys()) { - DEBUG(dbgs() << "\tConsidering merging " << printReg(CP.getSrcReg(), TRI) - << " with " << printReg(CP.getDstReg(), TRI, CP.getSrcIdx()) - << '\n'); + LLVM_DEBUG(dbgs() << "\tConsidering merging " + << printReg(CP.getSrcReg(), TRI) << " with " + << printReg(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n'); if (!canJoinPhys(CP)) { // Before giving up coalescing, if definition of source is defined by // trivial computation, try rematerializing it. @@ -1667,7 +1669,7 @@ bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) { LIS->getInterval(CP.getDstReg()).size()) CP.flip(); - DEBUG({ + LLVM_DEBUG({ dbgs() << "\tConsidering merging to " << TRI->getRegClassName(CP.getNewRC()) << " with "; if (CP.getDstIdx() && CP.getSrcIdx()) @@ -1703,7 +1705,7 @@ bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) { if (adjustCopiesBackFrom(CP, CopyMI) || removeCopyByCommutingDef(CP, CopyMI)) { deleteInstr(CopyMI); - DEBUG(dbgs() << "\tTrivial!\n"); + LLVM_DEBUG(dbgs() << "\tTrivial!\n"); return true; } } @@ -1715,7 +1717,7 @@ bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) { return true; // Otherwise, we are unable to join the intervals. - DEBUG(dbgs() << "\tInterference!\n"); + LLVM_DEBUG(dbgs() << "\tInterference!\n"); Again = true; // May be possible to coalesce later. return false; } @@ -1749,8 +1751,8 @@ bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) { for (LiveInterval::SubRange &S : LI.subranges()) { if ((S.LaneMask & ShrinkMask).none()) continue; - DEBUG(dbgs() << "Shrink LaneUses (Lane " << PrintLaneMask(S.LaneMask) - << ")\n"); + LLVM_DEBUG(dbgs() << "Shrink LaneUses (Lane " << PrintLaneMask(S.LaneMask) + << ")\n"); LIS->shrinkToUses(S, LI.reg); } LI.removeEmptySubRanges(); @@ -1767,7 +1769,7 @@ bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) { // Update regalloc hint. TRI->updateRegAllocHint(CP.getSrcReg(), CP.getDstReg(), *MF); - DEBUG({ + LLVM_DEBUG({ dbgs() << "\tSuccess: " << printReg(CP.getSrcReg(), TRI, CP.getSrcIdx()) << " -> " << printReg(CP.getDstReg(), TRI, CP.getDstIdx()) << '\n'; dbgs() << "\tResult = "; @@ -1788,7 +1790,7 @@ bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) { assert(CP.isPhys() && "Must be a physreg copy"); assert(MRI->isReserved(DstReg) && "Not a reserved register"); LiveInterval &RHS = LIS->getInterval(SrcReg); - DEBUG(dbgs() << "\t\tRHS = " << RHS << '\n'); + LLVM_DEBUG(dbgs() << "\t\tRHS = " << RHS << '\n'); assert(RHS.containsOneValue() && "Invalid join with reserved register"); @@ -1807,7 +1809,8 @@ bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) { return false; } if (RHS.overlaps(LIS->getRegUnit(*UI))) { - DEBUG(dbgs() << "\t\tInterference: " << printRegUnit(*UI, TRI) << '\n'); + LLVM_DEBUG(dbgs() << "\t\tInterference: " << printRegUnit(*UI, TRI) + << '\n'); return false; } } @@ -1816,7 +1819,7 @@ bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) { BitVector RegMaskUsable; if (LIS->checkRegMaskInterference(RHS, RegMaskUsable) && !RegMaskUsable.test(DstReg)) { - DEBUG(dbgs() << "\t\tRegMask interference\n"); + LLVM_DEBUG(dbgs() << "\t\tRegMask interference\n"); return false; } } @@ -1846,12 +1849,12 @@ bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) { // %y = def // ... if (!MRI->hasOneNonDBGUse(SrcReg)) { - DEBUG(dbgs() << "\t\tMultiple vreg uses!\n"); + LLVM_DEBUG(dbgs() << "\t\tMultiple vreg uses!\n"); return false; } if (!LIS->intervalIsInOneMBB(RHS)) { - DEBUG(dbgs() << "\t\tComplex control flow!\n"); + LLVM_DEBUG(dbgs() << "\t\tComplex control flow!\n"); return false; } @@ -1869,7 +1872,7 @@ bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) { SI != CopyRegIdx; SI = Indexes->getNextNonNullIndex(SI)) { MachineInstr *MI = LIS->getInstructionFromIndex(SI); if (MI->readsRegister(DstReg, TRI)) { - DEBUG(dbgs() << "\t\tInterference (read): " << *MI); + LLVM_DEBUG(dbgs() << "\t\tInterference (read): " << *MI); return false; } } @@ -1877,8 +1880,8 @@ bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) { // We're going to remove the copy which defines a physical reserved // register, so remove its valno, etc. - DEBUG(dbgs() << "\t\tRemoving phys reg def of " << printReg(DstReg, TRI) - << " at " << CopyRegIdx << "\n"); + LLVM_DEBUG(dbgs() << "\t\tRemoving phys reg def of " + << printReg(DstReg, TRI) << " at " << CopyRegIdx << "\n"); LIS->removePhysRegDefAt(DstReg, CopyRegIdx); // Create a new dead def at the new def location. @@ -2386,9 +2389,10 @@ JoinVals::analyzeValue(unsigned ValNo, JoinVals &Other) { // to erase the IMPLICIT_DEF instruction. if (OtherV.ErasableImplicitDef && DefMI && DefMI->getParent() != Indexes->getMBBFromIndex(V.OtherVNI->def)) { - DEBUG(dbgs() << "IMPLICIT_DEF defined at " << V.OtherVNI->def - << " extends into " << printMBBReference(*DefMI->getParent()) - << ", keeping it.\n"); + LLVM_DEBUG(dbgs() << "IMPLICIT_DEF defined at " << V.OtherVNI->def + << " extends into " + << printMBBReference(*DefMI->getParent()) + << ", keeping it.\n"); OtherV.ErasableImplicitDef = false; } @@ -2498,11 +2502,11 @@ void JoinVals::computeAssignment(unsigned ValNo, JoinVals &Other) { assert(V.OtherVNI && "OtherVNI not assigned, can't merge."); assert(Other.Vals[V.OtherVNI->id].isAnalyzed() && "Missing recursion"); Assignments[ValNo] = Other.Assignments[V.OtherVNI->id]; - DEBUG(dbgs() << "\t\tmerge " << printReg(Reg) << ':' << ValNo << '@' - << LR.getValNumInfo(ValNo)->def << " into " - << printReg(Other.Reg) << ':' << V.OtherVNI->id << '@' - << V.OtherVNI->def << " --> @" - << NewVNInfo[Assignments[ValNo]]->def << '\n'); + LLVM_DEBUG(dbgs() << "\t\tmerge " << printReg(Reg) << ':' << ValNo << '@' + << LR.getValNumInfo(ValNo)->def << " into " + << printReg(Other.Reg) << ':' << V.OtherVNI->id << '@' + << V.OtherVNI->def << " --> @" + << NewVNInfo[Assignments[ValNo]]->def << '\n'); break; case CR_Replace: case CR_Unresolved: { @@ -2528,8 +2532,8 @@ bool JoinVals::mapValues(JoinVals &Other) { for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) { computeAssignment(i, Other); if (Vals[i].Resolution == CR_Impossible) { - DEBUG(dbgs() << "\t\tinterference at " << printReg(Reg) << ':' << i - << '@' << LR.getValNumInfo(i)->def << '\n'); + LLVM_DEBUG(dbgs() << "\t\tinterference at " << printReg(Reg) << ':' << i + << '@' << LR.getValNumInfo(i)->def << '\n'); return false; } } @@ -2551,13 +2555,13 @@ taintExtent(unsigned ValNo, LaneBitmask TaintedLanes, JoinVals &Other, // lanes escape the block. SlotIndex End = OtherI->end; if (End >= MBBEnd) { - DEBUG(dbgs() << "\t\ttaints global " << printReg(Other.Reg) << ':' - << OtherI->valno->id << '@' << OtherI->start << '\n'); + LLVM_DEBUG(dbgs() << "\t\ttaints global " << printReg(Other.Reg) << ':' + << OtherI->valno->id << '@' << OtherI->start << '\n'); return false; } - DEBUG(dbgs() << "\t\ttaints local " << printReg(Other.Reg) << ':' - << OtherI->valno->id << '@' << OtherI->start - << " to " << End << '\n'); + LLVM_DEBUG(dbgs() << "\t\ttaints local " << printReg(Other.Reg) << ':' + << OtherI->valno->id << '@' << OtherI->start << " to " + << End << '\n'); // A dead def is not a problem. if (End.isDead()) break; @@ -2598,8 +2602,8 @@ bool JoinVals::resolveConflicts(JoinVals &Other) { assert(V.Resolution != CR_Impossible && "Unresolvable conflict"); if (V.Resolution != CR_Unresolved) continue; - DEBUG(dbgs() << "\t\tconflict at " << printReg(Reg) << ':' << i - << '@' << LR.getValNumInfo(i)->def << '\n'); + LLVM_DEBUG(dbgs() << "\t\tconflict at " << printReg(Reg) << ':' << i << '@' + << LR.getValNumInfo(i)->def << '\n'); if (SubRangeJoin) return false; @@ -2636,7 +2640,7 @@ bool JoinVals::resolveConflicts(JoinVals &Other) { while (true) { assert(MI != MBB->end() && "Bad LastMI"); if (usesLanes(*MI, Other.Reg, Other.SubIdx, TaintedLanes)) { - DEBUG(dbgs() << "\t\ttainted lanes used by: " << *MI); + LLVM_DEBUG(dbgs() << "\t\ttainted lanes used by: " << *MI); return false; } // LastMI is the last instruction to use the current value. @@ -2709,8 +2713,8 @@ void JoinVals::pruneValues(JoinVals &Other, if (!EraseImpDef) EndPoints.push_back(Def); } - DEBUG(dbgs() << "\t\tpruned " << printReg(Other.Reg) << " at " << Def - << ": " << Other.LR << '\n'); + LLVM_DEBUG(dbgs() << "\t\tpruned " << printReg(Other.Reg) << " at " << Def + << ": " << Other.LR << '\n'); break; } case CR_Erase: @@ -2721,8 +2725,8 @@ void JoinVals::pruneValues(JoinVals &Other, // computeAssignment(), the value that was originally copied could have // been replaced. LIS->pruneValue(LR, Def, &EndPoints); - DEBUG(dbgs() << "\t\tpruned all of " << printReg(Reg) << " at " - << Def << ": " << LR << '\n'); + LLVM_DEBUG(dbgs() << "\t\tpruned all of " << printReg(Reg) << " at " + << Def << ": " << LR << '\n'); } break; case CR_Unresolved: @@ -2746,7 +2750,8 @@ void JoinVals::pruneSubRegValues(LiveInterval &LI, LaneBitmask &ShrinkMask) { // Check subranges at the point where the copy will be removed. SlotIndex Def = LR.getValNumInfo(i)->def; // Print message so mismatches with eraseInstrs() can be diagnosed. - DEBUG(dbgs() << "\t\tExpecting instruction removal at " << Def << '\n'); + LLVM_DEBUG(dbgs() << "\t\tExpecting instruction removal at " << Def + << '\n'); for (LiveInterval::SubRange &S : LI.subranges()) { LiveQueryResult Q = S.Query(Def); @@ -2754,8 +2759,8 @@ void JoinVals::pruneSubRegValues(LiveInterval &LI, LaneBitmask &ShrinkMask) { // copied and we must remove that subrange value as well. VNInfo *ValueOut = Q.valueOutOrDead(); if (ValueOut != nullptr && Q.valueIn() == nullptr) { - DEBUG(dbgs() << "\t\tPrune sublane " << PrintLaneMask(S.LaneMask) - << " at " << Def << "\n"); + LLVM_DEBUG(dbgs() << "\t\tPrune sublane " << PrintLaneMask(S.LaneMask) + << " at " << Def << "\n"); LIS->pruneValue(S, Def, nullptr); DidPrune = true; // Mark value number as unused. @@ -2765,8 +2770,9 @@ void JoinVals::pruneSubRegValues(LiveInterval &LI, LaneBitmask &ShrinkMask) { // If a subrange ends at the copy, then a value was copied but only // partially used later. Shrink the subregister range appropriately. if (Q.valueIn() != nullptr && Q.valueOut() == nullptr) { - DEBUG(dbgs() << "\t\tDead uses at sublane " << PrintLaneMask(S.LaneMask) - << " at " << Def << "\n"); + LLVM_DEBUG(dbgs() << "\t\tDead uses at sublane " + << PrintLaneMask(S.LaneMask) << " at " << Def + << "\n"); ShrinkMask |= S.LaneMask; } } @@ -2878,7 +2884,7 @@ void JoinVals::eraseInstrs(SmallPtrSetImpl<MachineInstr*> &ErasedInstrs, std::prev(S)->end = NewEnd; } } - DEBUG({ + LLVM_DEBUG({ dbgs() << "\t\tremoved " << i << '@' << Def << ": " << LR << '\n'; if (LI != nullptr) dbgs() << "\t\t LHS = " << *LI << '\n'; @@ -2896,7 +2902,7 @@ void JoinVals::eraseInstrs(SmallPtrSetImpl<MachineInstr*> &ErasedInstrs, ShrinkRegs.push_back(Reg); } ErasedInstrs.insert(MI); - DEBUG(dbgs() << "\t\terased:\t" << Def << '\t' << *MI); + LLVM_DEBUG(dbgs() << "\t\terased:\t" << Def << '\t' << *MI); LIS->RemoveMachineInstrFromMaps(*MI); MI->eraseFromParent(); break; @@ -2951,13 +2957,13 @@ void RegisterCoalescer::joinSubRegRanges(LiveRange &LRange, LiveRange &RRange, LRange.join(RRange, LHSVals.getAssignments(), RHSVals.getAssignments(), NewVNInfo); - DEBUG(dbgs() << "\t\tjoined lanes: " << LRange << "\n"); + LLVM_DEBUG(dbgs() << "\t\tjoined lanes: " << LRange << "\n"); if (EndPoints.empty()) return; // Recompute the parts of the live range we had to remove because of // CR_Replace conflicts. - DEBUG({ + LLVM_DEBUG({ dbgs() << "\t\trestoring liveness to " << EndPoints.size() << " points: "; for (unsigned i = 0, n = EndPoints.size(); i != n; ++i) { dbgs() << EndPoints[i]; @@ -2996,9 +3002,7 @@ bool RegisterCoalescer::joinVirtRegs(CoalescerPair &CP) { JoinVals LHSVals(LHS, CP.getDstReg(), CP.getDstIdx(), LaneBitmask::getNone(), NewVNInfo, CP, LIS, TRI, false, TrackSubRegLiveness); - DEBUG(dbgs() << "\t\tRHS = " << RHS - << "\n\t\tLHS = " << LHS - << '\n'); + LLVM_DEBUG(dbgs() << "\t\tRHS = " << RHS << "\n\t\tLHS = " << LHS << '\n'); // First compute NewVNInfo and the simple value mappings. // Detect impossible conflicts early. @@ -3029,8 +3033,8 @@ bool RegisterCoalescer::joinVirtRegs(CoalescerPair &CP) { R.LaneMask = Mask; } } - DEBUG(dbgs() << "\t\tLHST = " << printReg(CP.getDstReg()) - << ' ' << LHS << '\n'); + LLVM_DEBUG(dbgs() << "\t\tLHST = " << printReg(CP.getDstReg()) << ' ' << LHS + << '\n'); // Determine lanemasks of RHS in the coalesced register and merge subranges. unsigned SrcIdx = CP.getSrcIdx(); @@ -3045,7 +3049,7 @@ bool RegisterCoalescer::joinVirtRegs(CoalescerPair &CP) { mergeSubRangeInto(LHS, R, Mask, CP); } } - DEBUG(dbgs() << "\tJoined SubRanges " << LHS << "\n"); + LLVM_DEBUG(dbgs() << "\tJoined SubRanges " << LHS << "\n"); // Pruning implicit defs from subranges may result in the main range // having stale segments. @@ -3083,7 +3087,7 @@ bool RegisterCoalescer::joinVirtRegs(CoalescerPair &CP) { if (!EndPoints.empty()) { // Recompute the parts of the live range we had to remove because of // CR_Replace conflicts. - DEBUG({ + LLVM_DEBUG({ dbgs() << "\t\trestoring liveness to " << EndPoints.size() << " points: "; for (unsigned i = 0, n = EndPoints.size(); i != n; ++i) { dbgs() << EndPoints[i]; @@ -3231,7 +3235,8 @@ bool RegisterCoalescer::applyTerminalRule(const MachineInstr &Copy) const { continue; // Check that OtherReg interfere with DstReg. if (LIS->getInterval(OtherReg).overlaps(DstLI)) { - DEBUG(dbgs() << "Apply terminal rule for: " << printReg(DstReg) << '\n'); + LLVM_DEBUG(dbgs() << "Apply terminal rule for: " << printReg(DstReg) + << '\n'); return true; } } @@ -3240,7 +3245,7 @@ bool RegisterCoalescer::applyTerminalRule(const MachineInstr &Copy) const { void RegisterCoalescer::copyCoalesceInMBB(MachineBasicBlock *MBB) { - DEBUG(dbgs() << MBB->getName() << ":\n"); + LLVM_DEBUG(dbgs() << MBB->getName() << ":\n"); // Collect all copy-like instructions in MBB. Don't start coalescing anything // yet, it might invalidate the iterator. @@ -3305,7 +3310,7 @@ void RegisterCoalescer::coalesceLocals() { } void RegisterCoalescer::joinAllIntervals() { - DEBUG(dbgs() << "********** JOINING INTERVALS ***********\n"); + LLVM_DEBUG(dbgs() << "********** JOINING INTERVALS ***********\n"); assert(WorkList.empty() && LocalWorkList.empty() && "Old data still around."); std::vector<MBBPriorityInfo> MBBs; @@ -3361,8 +3366,8 @@ bool RegisterCoalescer::runOnMachineFunction(MachineFunction &fn) { // splitting optimization. JoinSplitEdges = EnableJoinSplits; - DEBUG(dbgs() << "********** SIMPLE REGISTER COALESCING **********\n" - << "********** Function: " << MF->getName() << '\n'); + LLVM_DEBUG(dbgs() << "********** SIMPLE REGISTER COALESCING **********\n" + << "********** Function: " << MF->getName() << '\n'); if (VerifyCoalescing) MF->verify(this, "Before register coalescing"); @@ -3379,14 +3384,15 @@ bool RegisterCoalescer::runOnMachineFunction(MachineFunction &fn) { array_pod_sort(InflateRegs.begin(), InflateRegs.end()); InflateRegs.erase(std::unique(InflateRegs.begin(), InflateRegs.end()), InflateRegs.end()); - DEBUG(dbgs() << "Trying to inflate " << InflateRegs.size() << " regs.\n"); + LLVM_DEBUG(dbgs() << "Trying to inflate " << InflateRegs.size() + << " regs.\n"); for (unsigned i = 0, e = InflateRegs.size(); i != e; ++i) { unsigned Reg = InflateRegs[i]; if (MRI->reg_nodbg_empty(Reg)) continue; if (MRI->recomputeRegClass(Reg)) { - DEBUG(dbgs() << printReg(Reg) << " inflated to " - << TRI->getRegClassName(MRI->getRegClass(Reg)) << '\n'); + LLVM_DEBUG(dbgs() << printReg(Reg) << " inflated to " + << TRI->getRegClassName(MRI->getRegClass(Reg)) << '\n'); ++NumInflated; LiveInterval &LI = LIS->getInterval(Reg); @@ -3409,7 +3415,7 @@ bool RegisterCoalescer::runOnMachineFunction(MachineFunction &fn) { } } - DEBUG(dump()); + LLVM_DEBUG(dump()); if (VerifyCoalescing) MF->verify(this, "After register coalescing"); return true; diff --git a/llvm/lib/CodeGen/RegisterScavenging.cpp b/llvm/lib/CodeGen/RegisterScavenging.cpp index 9fa14c9dc5e..d7cd5a096ef 100644 --- a/llvm/lib/CodeGen/RegisterScavenging.cpp +++ b/llvm/lib/CodeGen/RegisterScavenging.cpp @@ -288,8 +288,8 @@ bool RegScavenger::isRegUsed(unsigned Reg, bool includeReserved) const { unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RC) const { for (unsigned Reg : *RC) { if (!isRegUsed(Reg)) { - DEBUG(dbgs() << "Scavenger found unused reg: " << printReg(Reg, TRI) - << "\n"); + LLVM_DEBUG(dbgs() << "Scavenger found unused reg: " << printReg(Reg, TRI) + << "\n"); return Reg; } } @@ -561,15 +561,15 @@ unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC, // If we found an unused register there is no reason to spill it. if (!isRegUsed(SReg)) { - DEBUG(dbgs() << "Scavenged register: " << printReg(SReg, TRI) << "\n"); + LLVM_DEBUG(dbgs() << "Scavenged register: " << printReg(SReg, TRI) << "\n"); return SReg; } ScavengedInfo &Scavenged = spill(SReg, *RC, SPAdj, I, UseMI); Scavenged.Restore = &*std::prev(UseMI); - DEBUG(dbgs() << "Scavenged register (with spill): " << printReg(SReg, TRI) - << "\n"); + LLVM_DEBUG(dbgs() << "Scavenged register (with spill): " + << printReg(SReg, TRI) << "\n"); return SReg; } @@ -594,14 +594,15 @@ unsigned RegScavenger::scavengeRegisterBackwards(const TargetRegisterClass &RC, MachineBasicBlock::iterator ReloadAfter = RestoreAfter ? std::next(MBBI) : MBBI; MachineBasicBlock::iterator ReloadBefore = std::next(ReloadAfter); - DEBUG(dbgs() << "Reload before: " << *ReloadBefore << '\n'); + LLVM_DEBUG(dbgs() << "Reload before: " << *ReloadBefore << '\n'); ScavengedInfo &Scavenged = spill(Reg, RC, SPAdj, SpillBefore, ReloadBefore); Scavenged.Restore = &*std::prev(SpillBefore); LiveUnits.removeReg(Reg); - DEBUG(dbgs() << "Scavenged register with spill: " << printReg(Reg, TRI) - << " until " << *SpillBefore); + LLVM_DEBUG(dbgs() << "Scavenged register with spill: " << printReg(Reg, TRI) + << " until " << *SpillBefore); } else { - DEBUG(dbgs() << "Scavenged free register: " << printReg(Reg, TRI) << '\n'); + LLVM_DEBUG(dbgs() << "Scavenged free register: " << printReg(Reg, TRI) + << '\n'); } return Reg; } @@ -757,8 +758,8 @@ void llvm::scavengeFrameVirtualRegs(MachineFunction &MF, RegScavenger &RS) { bool Again = scavengeFrameVirtualRegsInBlock(MRI, RS, MBB); if (Again) { - DEBUG(dbgs() << "Warning: Required two scavenging passes for block " - << MBB.getName() << '\n'); + LLVM_DEBUG(dbgs() << "Warning: Required two scavenging passes for block " + << MBB.getName() << '\n'); Again = scavengeFrameVirtualRegsInBlock(MRI, RS, MBB); // The target required a 2nd run (because it created new vregs while // spilling). Refuse to do another pass to keep compiletime in check. diff --git a/llvm/lib/CodeGen/RenameIndependentSubregs.cpp b/llvm/lib/CodeGen/RenameIndependentSubregs.cpp index e25e53a24b5..7305091227d 100644 --- a/llvm/lib/CodeGen/RenameIndependentSubregs.cpp +++ b/llvm/lib/CodeGen/RenameIndependentSubregs.cpp @@ -134,17 +134,17 @@ bool RenameIndependentSubregs::renameComponents(LiveInterval &LI) const { const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); SmallVector<LiveInterval*, 4> Intervals; Intervals.push_back(&LI); - DEBUG(dbgs() << printReg(Reg) << ": Found " << Classes.getNumClasses() - << " equivalence classes.\n"); - DEBUG(dbgs() << printReg(Reg) << ": Splitting into newly created:"); + LLVM_DEBUG(dbgs() << printReg(Reg) << ": Found " << Classes.getNumClasses() + << " equivalence classes.\n"); + LLVM_DEBUG(dbgs() << printReg(Reg) << ": Splitting into newly created:"); for (unsigned I = 1, NumClasses = Classes.getNumClasses(); I < NumClasses; ++I) { unsigned NewVReg = MRI->createVirtualRegister(RegClass); LiveInterval &NewLI = LIS->createEmptyInterval(NewVReg); Intervals.push_back(&NewLI); - DEBUG(dbgs() << ' ' << printReg(NewVReg)); + LLVM_DEBUG(dbgs() << ' ' << printReg(NewVReg)); } - DEBUG(dbgs() << '\n'); + LLVM_DEBUG(dbgs() << '\n'); rewriteOperands(Classes, SubRangeInfos, Intervals); distribute(Classes, SubRangeInfos, Intervals); @@ -376,8 +376,8 @@ bool RenameIndependentSubregs::runOnMachineFunction(MachineFunction &MF) { if (!MRI->subRegLivenessEnabled()) return false; - DEBUG(dbgs() << "Renaming independent subregister live ranges in " - << MF.getName() << '\n'); + LLVM_DEBUG(dbgs() << "Renaming independent subregister live ranges in " + << MF.getName() << '\n'); LIS = &getAnalysis<LiveIntervals>(); TII = MF.getSubtarget().getInstrInfo(); diff --git a/llvm/lib/CodeGen/ResetMachineFunctionPass.cpp b/llvm/lib/CodeGen/ResetMachineFunctionPass.cpp index 72b631baf94..dbc4581c7a9 100644 --- a/llvm/lib/CodeGen/ResetMachineFunctionPass.cpp +++ b/llvm/lib/CodeGen/ResetMachineFunctionPass.cpp @@ -55,7 +55,7 @@ namespace { MachineFunctionProperties::Property::FailedISel)) { if (AbortOnFailedISel) report_fatal_error("Instruction selection failed"); - DEBUG(dbgs() << "Resetting: " << MF.getName() << '\n'); + LLVM_DEBUG(dbgs() << "Resetting: " << MF.getName() << '\n'); ++NumFunctionsReset; MF.reset(); if (EmitFallbackDiag) { diff --git a/llvm/lib/CodeGen/SafeStack.cpp b/llvm/lib/CodeGen/SafeStack.cpp index 3475bae4990..1e8de15efea 100644 --- a/llvm/lib/CodeGen/SafeStack.cpp +++ b/llvm/lib/CodeGen/SafeStack.cpp @@ -242,16 +242,17 @@ bool SafeStack::IsAccessSafe(Value *Addr, uint64_t AccessSize, ConstantRange(APInt(BitWidth, 0), APInt(BitWidth, AllocaSize)); bool Safe = AllocaRange.contains(AccessRange); - DEBUG(dbgs() << "[SafeStack] " - << (isa<AllocaInst>(AllocaPtr) ? "Alloca " : "ByValArgument ") - << *AllocaPtr << "\n" - << " Access " << *Addr << "\n" - << " SCEV " << *Expr - << " U: " << SE.getUnsignedRange(Expr) - << ", S: " << SE.getSignedRange(Expr) << "\n" - << " Range " << AccessRange << "\n" - << " AllocaRange " << AllocaRange << "\n" - << " " << (Safe ? "safe" : "unsafe") << "\n"); + LLVM_DEBUG( + dbgs() << "[SafeStack] " + << (isa<AllocaInst>(AllocaPtr) ? "Alloca " : "ByValArgument ") + << *AllocaPtr << "\n" + << " Access " << *Addr << "\n" + << " SCEV " << *Expr + << " U: " << SE.getUnsignedRange(Expr) + << ", S: " << SE.getSignedRange(Expr) << "\n" + << " Range " << AccessRange << "\n" + << " AllocaRange " << AllocaRange << "\n" + << " " << (Safe ? "safe" : "unsafe") << "\n"); return Safe; } @@ -298,8 +299,9 @@ bool SafeStack::IsSafeStackAlloca(const Value *AllocaPtr, uint64_t AllocaSize) { case Instruction::Store: if (V == I->getOperand(0)) { // Stored the pointer - conservatively assume it may be unsafe. - DEBUG(dbgs() << "[SafeStack] Unsafe alloca: " << *AllocaPtr - << "\n store of address: " << *I << "\n"); + LLVM_DEBUG(dbgs() + << "[SafeStack] Unsafe alloca: " << *AllocaPtr + << "\n store of address: " << *I << "\n"); return false; } @@ -324,9 +326,9 @@ bool SafeStack::IsSafeStackAlloca(const Value *AllocaPtr, uint64_t AllocaSize) { if (const MemIntrinsic *MI = dyn_cast<MemIntrinsic>(I)) { if (!IsMemIntrinsicSafe(MI, UI, AllocaPtr, AllocaSize)) { - DEBUG(dbgs() << "[SafeStack] Unsafe alloca: " << *AllocaPtr - << "\n unsafe memintrinsic: " << *I - << "\n"); + LLVM_DEBUG(dbgs() + << "[SafeStack] Unsafe alloca: " << *AllocaPtr + << "\n unsafe memintrinsic: " << *I << "\n"); return false; } continue; @@ -344,8 +346,8 @@ bool SafeStack::IsSafeStackAlloca(const Value *AllocaPtr, uint64_t AllocaSize) { if (A->get() == V) if (!(CS.doesNotCapture(A - B) && (CS.doesNotAccessMemory(A - B) || CS.doesNotAccessMemory()))) { - DEBUG(dbgs() << "[SafeStack] Unsafe alloca: " << *AllocaPtr - << "\n unsafe call: " << *I << "\n"); + LLVM_DEBUG(dbgs() << "[SafeStack] Unsafe alloca: " << *AllocaPtr + << "\n unsafe call: " << *I << "\n"); return false; } continue; @@ -829,7 +831,7 @@ bool SafeStack::run() { TryInlinePointerAddress(); - DEBUG(dbgs() << "[SafeStack] safestack applied\n"); + LLVM_DEBUG(dbgs() << "[SafeStack] safestack applied\n"); return true; } @@ -850,17 +852,17 @@ public: } bool runOnFunction(Function &F) override { - DEBUG(dbgs() << "[SafeStack] Function: " << F.getName() << "\n"); + LLVM_DEBUG(dbgs() << "[SafeStack] Function: " << F.getName() << "\n"); if (!F.hasFnAttribute(Attribute::SafeStack)) { - DEBUG(dbgs() << "[SafeStack] safestack is not requested" - " for this function\n"); + LLVM_DEBUG(dbgs() << "[SafeStack] safestack is not requested" + " for this function\n"); return false; } if (F.isDeclaration()) { - DEBUG(dbgs() << "[SafeStack] function definition" - " is not available\n"); + LLVM_DEBUG(dbgs() << "[SafeStack] function definition" + " is not available\n"); return false; } diff --git a/llvm/lib/CodeGen/SafeStackColoring.cpp b/llvm/lib/CodeGen/SafeStackColoring.cpp index 35b0736845a..329458778a9 100644 --- a/llvm/lib/CodeGen/SafeStackColoring.cpp +++ b/llvm/lib/CodeGen/SafeStackColoring.cpp @@ -102,10 +102,10 @@ void StackColoring::collectMarkers() { // For each basic block, compute // * the list of markers in the instruction order // * the sets of allocas whose lifetime starts or ends in this BB - DEBUG(dbgs() << "Instructions:\n"); + LLVM_DEBUG(dbgs() << "Instructions:\n"); unsigned InstNo = 0; for (BasicBlock *BB : depth_first(&F)) { - DEBUG(dbgs() << " " << InstNo << ": BB " << BB->getName() << "\n"); + LLVM_DEBUG(dbgs() << " " << InstNo << ": BB " << BB->getName() << "\n"); unsigned BBStart = InstNo++; BlockLifetimeInfo &BlockInfo = BlockLiveness[BB]; @@ -122,9 +122,9 @@ void StackColoring::collectMarkers() { } auto ProcessMarker = [&](Instruction *I, const Marker &M) { - DEBUG(dbgs() << " " << InstNo << ": " - << (M.IsStart ? "start " : "end ") << M.AllocaNo << ", " - << *I << "\n"); + LLVM_DEBUG(dbgs() << " " << InstNo << ": " + << (M.IsStart ? "start " : "end ") << M.AllocaNo + << ", " << *I << "\n"); BBMarkers[BB].push_back({InstNo, M}); @@ -281,7 +281,7 @@ LLVM_DUMP_METHOD void StackColoring::dumpLiveRanges() { #endif void StackColoring::run() { - DEBUG(dumpAllocas()); + LLVM_DEBUG(dumpAllocas()); for (unsigned I = 0; I < NumAllocas; ++I) AllocaNumbering[Allocas[I]] = I; @@ -304,7 +304,7 @@ void StackColoring::run() { LiveRanges[I] = getFullLiveRange(); calculateLocalLiveness(); - DEBUG(dumpBlockLiveness()); + LLVM_DEBUG(dumpBlockLiveness()); calculateLiveIntervals(); - DEBUG(dumpLiveRanges()); + LLVM_DEBUG(dumpLiveRanges()); } diff --git a/llvm/lib/CodeGen/SafeStackLayout.cpp b/llvm/lib/CodeGen/SafeStackLayout.cpp index 68ccdc27766..07b6a5d1883 100644 --- a/llvm/lib/CodeGen/SafeStackLayout.cpp +++ b/llvm/lib/CodeGen/SafeStackLayout.cpp @@ -63,30 +63,30 @@ void StackLayout::layoutObject(StackObject &Obj) { return; } - DEBUG(dbgs() << "Layout: size " << Obj.Size << ", align " << Obj.Alignment - << ", range " << Obj.Range << "\n"); + LLVM_DEBUG(dbgs() << "Layout: size " << Obj.Size << ", align " + << Obj.Alignment << ", range " << Obj.Range << "\n"); assert(Obj.Alignment <= MaxAlignment); unsigned Start = AdjustStackOffset(0, Obj.Size, Obj.Alignment); unsigned End = Start + Obj.Size; - DEBUG(dbgs() << " First candidate: " << Start << " .. " << End << "\n"); + LLVM_DEBUG(dbgs() << " First candidate: " << Start << " .. " << End << "\n"); for (const StackRegion &R : Regions) { - DEBUG(dbgs() << " Examining region: " << R.Start << " .. " << R.End - << ", range " << R.Range << "\n"); + LLVM_DEBUG(dbgs() << " Examining region: " << R.Start << " .. " << R.End + << ", range " << R.Range << "\n"); assert(End >= R.Start); if (Start >= R.End) { - DEBUG(dbgs() << " Does not intersect, skip.\n"); + LLVM_DEBUG(dbgs() << " Does not intersect, skip.\n"); continue; } if (Obj.Range.Overlaps(R.Range)) { // Find the next appropriate location. Start = AdjustStackOffset(R.End, Obj.Size, Obj.Alignment); End = Start + Obj.Size; - DEBUG(dbgs() << " Overlaps. Next candidate: " << Start << " .. " << End - << "\n"); + LLVM_DEBUG(dbgs() << " Overlaps. Next candidate: " << Start << " .. " + << End << "\n"); continue; } if (End <= R.End) { - DEBUG(dbgs() << " Reusing region(s).\n"); + LLVM_DEBUG(dbgs() << " Reusing region(s).\n"); break; } } @@ -95,13 +95,13 @@ void StackLayout::layoutObject(StackObject &Obj) { if (End > LastRegionEnd) { // Insert a new region at the end. Maybe two. if (Start > LastRegionEnd) { - DEBUG(dbgs() << " Creating gap region: " << LastRegionEnd << " .. " - << Start << "\n"); + LLVM_DEBUG(dbgs() << " Creating gap region: " << LastRegionEnd << " .. " + << Start << "\n"); Regions.emplace_back(LastRegionEnd, Start, StackColoring::LiveRange()); LastRegionEnd = Start; } - DEBUG(dbgs() << " Creating new region: " << LastRegionEnd << " .. " << End - << ", range " << Obj.Range << "\n"); + LLVM_DEBUG(dbgs() << " Creating new region: " << LastRegionEnd << " .. " + << End << ", range " << Obj.Range << "\n"); Regions.emplace_back(LastRegionEnd, End, Obj.Range); LastRegionEnd = End; } @@ -150,5 +150,5 @@ void StackLayout::computeLayout() { for (auto &Obj : StackObjects) layoutObject(Obj); - DEBUG(print(dbgs())); + LLVM_DEBUG(print(dbgs())); } diff --git a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp index d08501fa3c4..32c0181a479 100644 --- a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp +++ b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp @@ -849,8 +849,8 @@ void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA, BarrierChain->addPredBarrier(SU); BarrierChain = SU; - DEBUG(dbgs() << "Global memory object and new barrier chain: SU(" - << BarrierChain->NodeNum << ").\n";); + LLVM_DEBUG(dbgs() << "Global memory object and new barrier chain: SU(" + << BarrierChain->NodeNum << ").\n";); // Add dependencies against everything below it and clear maps. addBarrierChain(Stores); @@ -938,11 +938,12 @@ void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA, // Reduce maps if they grow huge. if (Stores.size() + Loads.size() >= HugeRegion) { - DEBUG(dbgs() << "Reducing Stores and Loads maps.\n";); + LLVM_DEBUG(dbgs() << "Reducing Stores and Loads maps.\n";); reduceHugeMemNodeMaps(Stores, Loads, getReductionSize()); } if (NonAliasStores.size() + NonAliasLoads.size() >= HugeRegion) { - DEBUG(dbgs() << "Reducing NonAliasStores and NonAliasLoads maps.\n";); + LLVM_DEBUG( + dbgs() << "Reducing NonAliasStores and NonAliasLoads maps.\n";); reduceHugeMemNodeMaps(NonAliasStores, NonAliasLoads, getReductionSize()); } } @@ -982,10 +983,8 @@ void ScheduleDAGInstrs::Value2SUsMap::dump() { void ScheduleDAGInstrs::reduceHugeMemNodeMaps(Value2SUsMap &stores, Value2SUsMap &loads, unsigned N) { - DEBUG(dbgs() << "Before reduction:\nStoring SUnits:\n"; - stores.dump(); - dbgs() << "Loading SUnits:\n"; - loads.dump()); + LLVM_DEBUG(dbgs() << "Before reduction:\nStoring SUnits:\n"; stores.dump(); + dbgs() << "Loading SUnits:\n"; loads.dump()); // Insert all SU's NodeNums into a vector and sort it. std::vector<unsigned> NodeNums; @@ -1011,12 +1010,12 @@ void ScheduleDAGInstrs::reduceHugeMemNodeMaps(Value2SUsMap &stores, if (newBarrierChain->NodeNum < BarrierChain->NodeNum) { BarrierChain->addPredBarrier(newBarrierChain); BarrierChain = newBarrierChain; - DEBUG(dbgs() << "Inserting new barrier chain: SU(" - << BarrierChain->NodeNum << ").\n";); + LLVM_DEBUG(dbgs() << "Inserting new barrier chain: SU(" + << BarrierChain->NodeNum << ").\n";); } else - DEBUG(dbgs() << "Keeping old barrier chain: SU(" - << BarrierChain->NodeNum << ").\n";); + LLVM_DEBUG(dbgs() << "Keeping old barrier chain: SU(" + << BarrierChain->NodeNum << ").\n";); } else BarrierChain = newBarrierChain; @@ -1024,10 +1023,8 @@ void ScheduleDAGInstrs::reduceHugeMemNodeMaps(Value2SUsMap &stores, insertBarrierChain(stores); insertBarrierChain(loads); - DEBUG(dbgs() << "After reduction:\nStoring SUnits:\n"; - stores.dump(); - dbgs() << "Loading SUnits:\n"; - loads.dump()); + LLVM_DEBUG(dbgs() << "After reduction:\nStoring SUnits:\n"; stores.dump(); + dbgs() << "Loading SUnits:\n"; loads.dump()); } static void toggleKills(const MachineRegisterInfo &MRI, LivePhysRegs &LiveRegs, @@ -1048,7 +1045,7 @@ static void toggleKills(const MachineRegisterInfo &MRI, LivePhysRegs &LiveRegs, } void ScheduleDAGInstrs::fixupKills(MachineBasicBlock &MBB) { - DEBUG(dbgs() << "Fixup kills for " << printMBBReference(MBB) << '\n'); + LLVM_DEBUG(dbgs() << "Fixup kills for " << printMBBReference(MBB) << '\n'); LiveRegs.init(*TRI); LiveRegs.addLiveOuts(MBB); @@ -1249,11 +1246,11 @@ public: } R.SubtreeConnections.resize(SubtreeClasses.getNumClasses()); R.SubtreeConnectLevels.resize(SubtreeClasses.getNumClasses()); - DEBUG(dbgs() << R.getNumSubtrees() << " subtrees:\n"); + LLVM_DEBUG(dbgs() << R.getNumSubtrees() << " subtrees:\n"); for (unsigned Idx = 0, End = R.DFSNodeData.size(); Idx != End; ++Idx) { R.DFSNodeData[Idx].SubtreeID = SubtreeClasses[Idx]; - DEBUG(dbgs() << " SU(" << Idx << ") in tree " - << R.DFSNodeData[Idx].SubtreeID << '\n'); + LLVM_DEBUG(dbgs() << " SU(" << Idx << ") in tree " + << R.DFSNodeData[Idx].SubtreeID << '\n'); } for (const std::pair<const SUnit*, const SUnit*> &P : ConnectionPairs) { unsigned PredTree = SubtreeClasses[P.first->NodeNum]; @@ -1408,8 +1405,8 @@ void SchedDFSResult::scheduleTree(unsigned SubtreeID) { for (const Connection &C : SubtreeConnections[SubtreeID]) { SubtreeConnectLevels[C.TreeID] = std::max(SubtreeConnectLevels[C.TreeID], C.Level); - DEBUG(dbgs() << " Tree: " << C.TreeID - << " @" << SubtreeConnectLevels[C.TreeID] << '\n'); + LLVM_DEBUG(dbgs() << " Tree: " << C.TreeID << " @" + << SubtreeConnectLevels[C.TreeID] << '\n'); } } diff --git a/llvm/lib/CodeGen/ScoreboardHazardRecognizer.cpp b/llvm/lib/CodeGen/ScoreboardHazardRecognizer.cpp index 1364c9d8de8..b8bfe69a76e 100644 --- a/llvm/lib/CodeGen/ScoreboardHazardRecognizer.cpp +++ b/llvm/lib/CodeGen/ScoreboardHazardRecognizer.cpp @@ -69,12 +69,12 @@ ScoreboardHazardRecognizer::ScoreboardHazardRecognizer( // If MaxLookAhead is not set above, then we are not enabled. if (!isEnabled()) - DEBUG(dbgs() << "Disabled scoreboard hazard recognizer\n"); + LLVM_DEBUG(dbgs() << "Disabled scoreboard hazard recognizer\n"); else { // A nonempty itinerary must have a SchedModel. IssueWidth = ItinData->SchedModel.IssueWidth; - DEBUG(dbgs() << "Using scoreboard hazard recognizer: Depth = " - << ScoreboardDepth << '\n'); + LLVM_DEBUG(dbgs() << "Using scoreboard hazard recognizer: Depth = " + << ScoreboardDepth << '\n'); } } @@ -156,9 +156,9 @@ ScoreboardHazardRecognizer::getHazardType(SUnit *SU, int Stalls) { } if (!freeUnits) { - DEBUG(dbgs() << "*** Hazard in cycle +" << StageCycle << ", "); - DEBUG(dbgs() << "SU(" << SU->NodeNum << "): "); - DEBUG(DAG->dumpNode(SU)); + LLVM_DEBUG(dbgs() << "*** Hazard in cycle +" << StageCycle << ", "); + LLVM_DEBUG(dbgs() << "SU(" << SU->NodeNum << "): "); + LLVM_DEBUG(DAG->dumpNode(SU)); return Hazard; } } @@ -224,8 +224,8 @@ void ScoreboardHazardRecognizer::EmitInstruction(SUnit *SU) { cycle += IS->getNextCycles(); } - DEBUG(ReservedScoreboard.dump()); - DEBUG(RequiredScoreboard.dump()); + LLVM_DEBUG(ReservedScoreboard.dump()); + LLVM_DEBUG(RequiredScoreboard.dump()); } void ScoreboardHazardRecognizer::AdvanceCycle() { diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index d03c6ffa6bb..ccbbc056dd0 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -972,11 +972,9 @@ SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, bool AddTo) { assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); ++NodesCombined; - DEBUG(dbgs() << "\nReplacing.1 "; - N->dump(&DAG); - dbgs() << "\nWith: "; - To[0].getNode()->dump(&DAG); - dbgs() << " and " << NumTo-1 << " other values\n"); + LLVM_DEBUG(dbgs() << "\nReplacing.1 "; N->dump(&DAG); dbgs() << "\nWith: "; + To[0].getNode()->dump(&DAG); + dbgs() << " and " << NumTo - 1 << " other values\n"); for (unsigned i = 0, e = NumTo; i != e; ++i) assert((!To[i].getNode() || N->getValueType(i) == To[i].getValueType()) && @@ -1033,11 +1031,9 @@ bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { // Replace the old value with the new one. ++NodesCombined; - DEBUG(dbgs() << "\nReplacing.2 "; - TLO.Old.getNode()->dump(&DAG); - dbgs() << "\nWith: "; - TLO.New.getNode()->dump(&DAG); - dbgs() << '\n'); + LLVM_DEBUG(dbgs() << "\nReplacing.2 "; TLO.Old.getNode()->dump(&DAG); + dbgs() << "\nWith: "; TLO.New.getNode()->dump(&DAG); + dbgs() << '\n'); CommitTargetLoweringOpt(TLO); return true; @@ -1058,8 +1054,9 @@ bool DAGCombiner::SimplifyDemandedVectorElts(SDValue Op, // Replace the old value with the new one. ++NodesCombined; - DEBUG(dbgs() << "\nReplacing.2 "; TLO.Old.getNode()->dump(&DAG); - dbgs() << "\nWith: "; TLO.New.getNode()->dump(&DAG); dbgs() << '\n'); + LLVM_DEBUG(dbgs() << "\nReplacing.2 "; TLO.Old.getNode()->dump(&DAG); + dbgs() << "\nWith: "; TLO.New.getNode()->dump(&DAG); + dbgs() << '\n'); CommitTargetLoweringOpt(TLO); return true; @@ -1070,11 +1067,8 @@ void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) { EVT VT = Load->getValueType(0); SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, VT, SDValue(ExtLoad, 0)); - DEBUG(dbgs() << "\nReplacing.9 "; - Load->dump(&DAG); - dbgs() << "\nWith: "; - Trunc.getNode()->dump(&DAG); - dbgs() << '\n'); + LLVM_DEBUG(dbgs() << "\nReplacing.9 "; Load->dump(&DAG); dbgs() << "\nWith: "; + Trunc.getNode()->dump(&DAG); dbgs() << '\n'); WorklistRemover DeadNodes(*this); DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc); DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1)); @@ -1173,7 +1167,7 @@ SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) { if (TLI.IsDesirableToPromoteOp(Op, PVT)) { assert(PVT != VT && "Don't know what type to promote to!"); - DEBUG(dbgs() << "\nPromoting "; Op.getNode()->dump(&DAG)); + LLVM_DEBUG(dbgs() << "\nPromoting "; Op.getNode()->dump(&DAG)); bool Replace0 = false; SDValue N0 = Op.getOperand(0); @@ -1238,7 +1232,7 @@ SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) { if (TLI.IsDesirableToPromoteOp(Op, PVT)) { assert(PVT != VT && "Don't know what type to promote to!"); - DEBUG(dbgs() << "\nPromoting "; Op.getNode()->dump(&DAG)); + LLVM_DEBUG(dbgs() << "\nPromoting "; Op.getNode()->dump(&DAG)); bool Replace = false; SDValue N0 = Op.getOperand(0); @@ -1290,8 +1284,7 @@ SDValue DAGCombiner::PromoteExtend(SDValue Op) { // fold (aext (aext x)) -> (aext x) // fold (aext (zext x)) -> (zext x) // fold (aext (sext x)) -> (sext x) - DEBUG(dbgs() << "\nPromoting "; - Op.getNode()->dump(&DAG)); + LLVM_DEBUG(dbgs() << "\nPromoting "; Op.getNode()->dump(&DAG)); return DAG.getNode(Op.getOpcode(), SDLoc(Op), VT, Op.getOperand(0)); } return SDValue(); @@ -1331,11 +1324,8 @@ bool DAGCombiner::PromoteLoad(SDValue Op) { MemVT, LD->getMemOperand()); SDValue Result = DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD); - DEBUG(dbgs() << "\nPromoting "; - N->dump(&DAG); - dbgs() << "\nTo: "; - Result.getNode()->dump(&DAG); - dbgs() << '\n'); + LLVM_DEBUG(dbgs() << "\nPromoting "; N->dump(&DAG); dbgs() << "\nTo: "; + Result.getNode()->dump(&DAG); dbgs() << '\n'); WorklistRemover DeadNodes(*this); DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result); DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1)); @@ -1430,7 +1420,7 @@ void DAGCombiner::Run(CombineLevel AtLevel) { continue; } - DEBUG(dbgs() << "\nCombining: "; N->dump(&DAG)); + LLVM_DEBUG(dbgs() << "\nCombining: "; N->dump(&DAG)); // Add any operands of the new node which have not yet been combined to the // worklist as well. Because the worklist uniques things already, this @@ -1458,8 +1448,7 @@ void DAGCombiner::Run(CombineLevel AtLevel) { RV.getOpcode() != ISD::DELETED_NODE && "Node was deleted but visit returned new node!"); - DEBUG(dbgs() << " ... into: "; - RV.getNode()->dump(&DAG)); + LLVM_DEBUG(dbgs() << " ... into: "; RV.getNode()->dump(&DAG)); if (N->getNumValues() == RV.getNode()->getNumValues()) DAG.ReplaceAllUsesWith(N, RV.getNode()); @@ -3957,13 +3946,13 @@ bool DAGCombiner::BackwardsPropagateMask(SDNode *N, SelectionDAG &DAG) { if (Loads.size() == 0) return false; - DEBUG(dbgs() << "Backwards propagate AND: "; N->dump()); + LLVM_DEBUG(dbgs() << "Backwards propagate AND: "; N->dump()); SDValue MaskOp = N->getOperand(1); // If it exists, fixup the single node we allow in the tree that needs // masking. if (FixupNode) { - DEBUG(dbgs() << "First, need to fix up: "; FixupNode->dump()); + LLVM_DEBUG(dbgs() << "First, need to fix up: "; FixupNode->dump()); SDValue And = DAG.getNode(ISD::AND, SDLoc(FixupNode), FixupNode->getValueType(0), SDValue(FixupNode, 0), MaskOp); @@ -3988,7 +3977,7 @@ bool DAGCombiner::BackwardsPropagateMask(SDNode *N, SelectionDAG &DAG) { // Create narrow loads. for (auto *Load : Loads) { - DEBUG(dbgs() << "Propagate AND back to: "; Load->dump()); + LLVM_DEBUG(dbgs() << "Propagate AND back to: "; Load->dump()); SDValue And = DAG.getNode(ISD::AND, SDLoc(Load), Load->getValueType(0), SDValue(Load, 0), MaskOp); DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), And); @@ -11774,11 +11763,8 @@ bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { BasePtr, Offset, AM); ++PreIndexedNodes; ++NodesCombined; - DEBUG(dbgs() << "\nReplacing.4 "; - N->dump(&DAG); - dbgs() << "\nWith: "; - Result.getNode()->dump(&DAG); - dbgs() << '\n'); + LLVM_DEBUG(dbgs() << "\nReplacing.4 "; N->dump(&DAG); dbgs() << "\nWith: "; + Result.getNode()->dump(&DAG); dbgs() << '\n'); WorklistRemover DeadNodes(*this); if (isLoad) { DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0)); @@ -11943,11 +11929,9 @@ bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { BasePtr, Offset, AM); ++PostIndexedNodes; ++NodesCombined; - DEBUG(dbgs() << "\nReplacing.5 "; - N->dump(&DAG); - dbgs() << "\nWith: "; - Result.getNode()->dump(&DAG); - dbgs() << '\n'); + LLVM_DEBUG(dbgs() << "\nReplacing.5 "; N->dump(&DAG); + dbgs() << "\nWith: "; Result.getNode()->dump(&DAG); + dbgs() << '\n'); WorklistRemover DeadNodes(*this); if (isLoad) { DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0)); @@ -12013,11 +11997,9 @@ SDValue DAGCombiner::visitLOAD(SDNode *N) { // v3 = add v2, c // Now we replace use of chain2 with chain1. This makes the second load // isomorphic to the one we are deleting, and thus makes this load live. - DEBUG(dbgs() << "\nReplacing.6 "; - N->dump(&DAG); - dbgs() << "\nWith chain: "; - Chain.getNode()->dump(&DAG); - dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "\nReplacing.6 "; N->dump(&DAG); + dbgs() << "\nWith chain: "; Chain.getNode()->dump(&DAG); + dbgs() << "\n"); WorklistRemover DeadNodes(*this); DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain); AddUsersToWorklist(Chain.getNode()); @@ -12048,11 +12030,9 @@ SDValue DAGCombiner::visitLOAD(SDNode *N) { AddUsersToWorklist(N); } else Index = DAG.getUNDEF(N->getValueType(1)); - DEBUG(dbgs() << "\nReplacing.7 "; - N->dump(&DAG); - dbgs() << "\nWith: "; - Undef.getNode()->dump(&DAG); - dbgs() << " and 2 other values\n"); + LLVM_DEBUG(dbgs() << "\nReplacing.7 "; N->dump(&DAG); + dbgs() << "\nWith: "; Undef.getNode()->dump(&DAG); + dbgs() << " and 2 other values\n"); WorklistRemover DeadNodes(*this); DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef); DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Index); diff --git a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp index 166e7b1d416..99b223b1332 100644 --- a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp @@ -261,7 +261,8 @@ void FastISel::sinkLocalValueMaterialization(MachineInstr &LocalMI, if (!UsedByPHI && MRI.use_nodbg_empty(DefReg)) { if (EmitStartPt == &LocalMI) EmitStartPt = EmitStartPt->getPrevNode(); - DEBUG(dbgs() << "removing dead local value materialization " << LocalMI); + LLVM_DEBUG(dbgs() << "removing dead local value materialization " + << LocalMI); OrderMap.Orders.erase(&LocalMI); LocalMI.eraseFromParent(); return; @@ -312,7 +313,7 @@ void FastISel::sinkLocalValueMaterialization(MachineInstr &LocalMI, } // Sink LocalMI before SinkPos and assign it the same DebugLoc. - DEBUG(dbgs() << "sinking local value to first use " << LocalMI); + LLVM_DEBUG(dbgs() << "sinking local value to first use " << LocalMI); FuncInfo.MBB->remove(&LocalMI); FuncInfo.MBB->insert(SinkPos, &LocalMI); if (SinkPos != FuncInfo.MBB->end()) @@ -1329,13 +1330,13 @@ bool FastISel::selectIntrinsicCall(const IntrinsicInst *II) { const DbgDeclareInst *DI = cast<DbgDeclareInst>(II); assert(DI->getVariable() && "Missing variable"); if (!FuncInfo.MF->getMMI().hasDebugInfo()) { - DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n"); + LLVM_DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n"); return true; } const Value *Address = DI->getAddress(); if (!Address || isa<UndefValue>(Address)) { - DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n"); + LLVM_DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n"); return true; } @@ -1387,7 +1388,7 @@ bool FastISel::selectIntrinsicCall(const IntrinsicInst *II) { } else { // We can't yet handle anything else here because it would require // generating code, thus altering codegen because of debug info. - DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n"); + LLVM_DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n"); } return true; } @@ -1430,7 +1431,7 @@ bool FastISel::selectIntrinsicCall(const IntrinsicInst *II) { } else { // We can't yet handle anything else here because it would require // generating code, thus altering codegen because of debug info. - DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n"); + LLVM_DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n"); } return true; } diff --git a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp index f1d92dc7270..798b924244a 100644 --- a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp @@ -485,7 +485,7 @@ int FunctionLoweringInfo::getArgumentFrameIndex(const Argument *A) { auto I = ByValArgFrameIndexMap.find(A); if (I != ByValArgFrameIndexMap.end()) return I->second; - DEBUG(dbgs() << "Argument does not have assigned frame index!\n"); + LLVM_DEBUG(dbgs() << "Argument does not have assigned frame index!\n"); return INT_MAX; } diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 86c6c054264..71bb3c7d024 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -200,8 +200,8 @@ public: } void ReplaceNode(SDNode *Old, SDNode *New) { - DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG); - dbgs() << " with: "; New->dump(&DAG)); + LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG); + dbgs() << " with: "; New->dump(&DAG)); assert(Old->getNumValues() == New->getNumValues() && "Replacing one node with another that produces a different number " @@ -213,8 +213,8 @@ public: } void ReplaceNode(SDValue Old, SDValue New) { - DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG); - dbgs() << " with: "; New->dump(&DAG)); + LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG); + dbgs() << " with: "; New->dump(&DAG)); DAG.ReplaceAllUsesWith(Old, New); if (UpdatedNodes) @@ -223,13 +223,12 @@ public: } void ReplaceNode(SDNode *Old, const SDValue *New) { - DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG)); + LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG)); DAG.ReplaceAllUsesWith(Old, New); for (unsigned i = 0, e = Old->getNumValues(); i != e; ++i) { - DEBUG(dbgs() << (i == 0 ? " with: " - : " and: "); - New[i]->dump(&DAG)); + LLVM_DEBUG(dbgs() << (i == 0 ? " with: " : " and: "); + New[i]->dump(&DAG)); if (UpdatedNodes) UpdatedNodes->insert(New[i].getNode()); } @@ -408,7 +407,7 @@ SDValue SelectionDAGLegalize::ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, } SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) { - DEBUG(dbgs() << "Optimizing float store operations\n"); + LLVM_DEBUG(dbgs() << "Optimizing float store operations\n"); // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' // FIXME: We shouldn't do this for TargetConstantFP's. // FIXME: move this to the DAG Combiner! Note that we can't regress due @@ -477,7 +476,7 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) { AAMDNodes AAInfo = ST->getAAInfo(); if (!ST->isTruncatingStore()) { - DEBUG(dbgs() << "Legalizing store operation\n"); + LLVM_DEBUG(dbgs() << "Legalizing store operation\n"); if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) { ReplaceNode(ST, OptStore); return; @@ -495,15 +494,15 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) { unsigned Align = ST->getAlignment(); const DataLayout &DL = DAG.getDataLayout(); if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align)) { - DEBUG(dbgs() << "Expanding unsupported unaligned store\n"); + LLVM_DEBUG(dbgs() << "Expanding unsupported unaligned store\n"); SDValue Result = TLI.expandUnalignedStore(ST, DAG); ReplaceNode(SDValue(ST, 0), Result); } else - DEBUG(dbgs() << "Legal store\n"); + LLVM_DEBUG(dbgs() << "Legal store\n"); break; } case TargetLowering::Custom: { - DEBUG(dbgs() << "Trying custom lowering\n"); + LLVM_DEBUG(dbgs() << "Trying custom lowering\n"); SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG); if (Res && Res != SDValue(Node, 0)) ReplaceNode(SDValue(Node, 0), Res); @@ -524,7 +523,7 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) { return; } - DEBUG(dbgs() << "Legalizing truncating store operations\n"); + LLVM_DEBUG(dbgs() << "Legalizing truncating store operations\n"); SDValue Value = ST->getValue(); EVT StVT = ST->getMemoryVT(); unsigned StWidth = StVT.getSizeInBits(); @@ -656,7 +655,7 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) { ISD::LoadExtType ExtType = LD->getExtensionType(); if (ExtType == ISD::NON_EXTLOAD) { - DEBUG(dbgs() << "Legalizing non-extending load operation\n"); + LLVM_DEBUG(dbgs() << "Legalizing non-extending load operation\n"); MVT VT = Node->getSimpleValueType(0); SDValue RVal = SDValue(Node, 0); SDValue RChain = SDValue(Node, 1); @@ -706,7 +705,7 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) { return; } - DEBUG(dbgs() << "Legalizing extending load operation\n"); + LLVM_DEBUG(dbgs() << "Legalizing extending load operation\n"); EVT SrcVT = LD->getMemoryVT(); unsigned SrcWidth = SrcVT.getSizeInBits(); unsigned Alignment = LD->getAlignment(); @@ -979,7 +978,7 @@ getStrictFPOpcodeAction(const TargetLowering &TLI, unsigned Opcode, EVT VT) { /// Return a legal replacement for the given operation, with all legal operands. void SelectionDAGLegalize::LegalizeOp(SDNode *Node) { - DEBUG(dbgs() << "\nLegalizing: "; Node->dump(&DAG)); + LLVM_DEBUG(dbgs() << "\nLegalizing: "; Node->dump(&DAG)); // Allow illegal target nodes and illegal registers. if (Node->getOpcode() == ISD::TargetConstant || @@ -1202,10 +1201,10 @@ void SelectionDAGLegalize::LegalizeOp(SDNode *Node) { } switch (Action) { case TargetLowering::Legal: - DEBUG(dbgs() << "Legal node: nothing to do\n"); + LLVM_DEBUG(dbgs() << "Legal node: nothing to do\n"); return; case TargetLowering::Custom: - DEBUG(dbgs() << "Trying custom legalization\n"); + LLVM_DEBUG(dbgs() << "Trying custom legalization\n"); // FIXME: The handling for custom lowering with multiple results is // a complete mess. if (SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG)) { @@ -1213,7 +1212,7 @@ void SelectionDAGLegalize::LegalizeOp(SDNode *Node) { return; if (Node->getNumValues() == 1) { - DEBUG(dbgs() << "Successfully custom legalized node\n"); + LLVM_DEBUG(dbgs() << "Successfully custom legalized node\n"); // We can just directly replace this node with the lowered value. ReplaceNode(SDValue(Node, 0), Res); return; @@ -1222,11 +1221,11 @@ void SelectionDAGLegalize::LegalizeOp(SDNode *Node) { SmallVector<SDValue, 8> ResultVals; for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) ResultVals.push_back(Res.getValue(i)); - DEBUG(dbgs() << "Successfully custom legalized node\n"); + LLVM_DEBUG(dbgs() << "Successfully custom legalized node\n"); ReplaceNode(Node, ResultVals.data()); return; } - DEBUG(dbgs() << "Could not custom legalize node\n"); + LLVM_DEBUG(dbgs() << "Could not custom legalize node\n"); LLVM_FALLTHROUGH; case TargetLowering::Expand: if (ExpandNode(Node)) @@ -2041,12 +2040,12 @@ SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI); if (!CallInfo.second.getNode()) { - DEBUG(dbgs() << "Created tailcall: "; DAG.getRoot().dump()); + LLVM_DEBUG(dbgs() << "Created tailcall: "; DAG.getRoot().dump()); // It's a tailcall, return the chain (which is the DAG root). return DAG.getRoot(); } - DEBUG(dbgs() << "Created libcall: "; CallInfo.first.dump()); + LLVM_DEBUG(dbgs() << "Created libcall: "; CallInfo.first.dump()); return CallInfo.first; } @@ -2332,10 +2331,10 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, SDValue Op0, EVT DestVT, const SDLoc &dl) { // TODO: Should any fast-math-flags be set for the created nodes? - DEBUG(dbgs() << "Legalizing INT_TO_FP\n"); + LLVM_DEBUG(dbgs() << "Legalizing INT_TO_FP\n"); if (Op0.getValueType() == MVT::i32 && TLI.isTypeLegal(MVT::f64)) { - DEBUG(dbgs() << "32-bit [signed|unsigned] integer to float/double " - "expansion\n"); + LLVM_DEBUG(dbgs() << "32-bit [signed|unsigned] integer to float/double " + "expansion\n"); // Get the stack frame index of a 8 byte buffer. SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64); @@ -2400,7 +2399,7 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, SDValue Op0, // and in all alternate rounding modes. // TODO: Generalize this for use with other types. if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) { - DEBUG(dbgs() << "Converting unsigned i64 to f64\n"); + LLVM_DEBUG(dbgs() << "Converting unsigned i64 to f64\n"); SDValue TwoP52 = DAG.getConstant(UINT64_C(0x4330000000000000), dl, MVT::i64); SDValue TwoP84PlusTwoP52 = @@ -2423,7 +2422,7 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, SDValue Op0, // TODO: Generalize this for use with other types. if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) { - DEBUG(dbgs() << "Converting unsigned i64 to f32\n"); + LLVM_DEBUG(dbgs() << "Converting unsigned i64 to f32\n"); // For unsigned conversions, convert them to signed conversions using the // algorithm from the x86_64 __floatundidf in compiler_rt. if (!isSigned) { @@ -2858,7 +2857,7 @@ SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op, } bool SelectionDAGLegalize::ExpandNode(SDNode *Node) { - DEBUG(dbgs() << "Trying to expand node\n"); + LLVM_DEBUG(dbgs() << "Trying to expand node\n"); SmallVector<SDValue, 8> Results; SDLoc dl(Node); SDValue Tmp1, Tmp2, Tmp3, Tmp4; @@ -3316,7 +3315,7 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) { } break; case ISD::FP_TO_FP16: - DEBUG(dbgs() << "Legalizing FP_TO_FP16\n"); + LLVM_DEBUG(dbgs() << "Legalizing FP_TO_FP16\n"); if (!TLI.useSoftFloat() && TM.Options.UnsafeFPMath) { SDValue Op = Node->getOperand(0); MVT SVT = Op.getSimpleValueType(); @@ -3927,17 +3926,17 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) { // Replace the original node with the legalized result. if (Results.empty()) { - DEBUG(dbgs() << "Cannot expand node\n"); + LLVM_DEBUG(dbgs() << "Cannot expand node\n"); return false; } - DEBUG(dbgs() << "Succesfully expanded node\n"); + LLVM_DEBUG(dbgs() << "Succesfully expanded node\n"); ReplaceNode(Node, Results.data()); return true; } void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) { - DEBUG(dbgs() << "Trying to convert node to libcall\n"); + LLVM_DEBUG(dbgs() << "Trying to convert node to libcall\n"); SmallVector<SDValue, 8> Results; SDLoc dl(Node); // FIXME: Check flags on the node to see if we can use a finite call. @@ -4237,10 +4236,10 @@ void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) { // Replace the original node with the legalized result. if (!Results.empty()) { - DEBUG(dbgs() << "Successfully converted node to libcall\n"); + LLVM_DEBUG(dbgs() << "Successfully converted node to libcall\n"); ReplaceNode(Node, Results.data()); } else - DEBUG(dbgs() << "Could not convert node to libcall\n"); + LLVM_DEBUG(dbgs() << "Could not convert node to libcall\n"); } // Determine the vector type to use in place of an original scalar element when @@ -4254,7 +4253,7 @@ static MVT getPromotedVectorElementType(const TargetLowering &TLI, } void SelectionDAGLegalize::PromoteNode(SDNode *Node) { - DEBUG(dbgs() << "Trying to promote node\n"); + LLVM_DEBUG(dbgs() << "Trying to promote node\n"); SmallVector<SDValue, 8> Results; MVT OVT = Node->getSimpleValueType(0); if (Node->getOpcode() == ISD::UINT_TO_FP || @@ -4692,10 +4691,10 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) { // Replace the original node with the legalized result. if (!Results.empty()) { - DEBUG(dbgs() << "Successfully promoted node\n"); + LLVM_DEBUG(dbgs() << "Successfully promoted node\n"); ReplaceNode(Node, Results.data()); } else - DEBUG(dbgs() << "Could not promote node\n"); + LLVM_DEBUG(dbgs() << "Could not promote node\n"); } /// This is the entry point for the file. diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp index 3f17d4d605e..67661cece5e 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp @@ -47,8 +47,8 @@ static RTLIB::Libcall GetFPLibCall(EVT VT, //===----------------------------------------------------------------------===// bool DAGTypeLegalizer::SoftenFloatResult(SDNode *N, unsigned ResNo) { - DEBUG(dbgs() << "Soften float result " << ResNo << ": "; N->dump(&DAG); - dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "Soften float result " << ResNo << ": "; N->dump(&DAG); + dbgs() << "\n"); SDValue R = SDValue(); switch (N->getOpcode()) { @@ -738,8 +738,8 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_XINT_TO_FP(SDNode *N) { //===----------------------------------------------------------------------===// bool DAGTypeLegalizer::SoftenFloatOperand(SDNode *N, unsigned OpNo) { - DEBUG(dbgs() << "Soften float operand " << OpNo << ": "; N->dump(&DAG); - dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "Soften float operand " << OpNo << ": "; N->dump(&DAG); + dbgs() << "\n"); SDValue Res = SDValue(); switch (N->getOpcode()) { @@ -1039,7 +1039,7 @@ SDValue DAGTypeLegalizer::SoftenFloatOp_STORE(SDNode *N, unsigned OpNo) { /// have invalid operands or may have other results that need promotion, we just /// know that (at least) one result needs expansion. void DAGTypeLegalizer::ExpandFloatResult(SDNode *N, unsigned ResNo) { - DEBUG(dbgs() << "Expand float result: "; N->dump(&DAG); dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "Expand float result: "; N->dump(&DAG); dbgs() << "\n"); SDValue Lo, Hi; Lo = Hi = SDValue(); @@ -1538,7 +1538,7 @@ void DAGTypeLegalizer::ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo, /// types of the node are known to be legal, but other operands of the node may /// need promotion or expansion as well as the specified one. bool DAGTypeLegalizer::ExpandFloatOperand(SDNode *N, unsigned OpNo) { - DEBUG(dbgs() << "Expand float operand: "; N->dump(&DAG); dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "Expand float operand: "; N->dump(&DAG); dbgs() << "\n"); SDValue Res = SDValue(); // See if the target wants to custom expand this node. diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp index 8ed0f1b6e96..e6d8b0491ec 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -36,12 +36,13 @@ using namespace llvm; /// may also have invalid operands or may have other results that need /// expansion, we just know that (at least) one result needs promotion. void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) { - DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); + dbgs() << "\n"); SDValue Res = SDValue(); // See if the target wants to custom expand this node. if (CustomLowerNode(N, N->getValueType(ResNo), true)) { - DEBUG(dbgs() << "Node has been custom expanded, done\n"); + LLVM_DEBUG(dbgs() << "Node has been custom expanded, done\n"); return; } @@ -897,11 +898,12 @@ SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) { /// result types of the node are known to be legal, but other operands of the /// node may need promotion or expansion as well as the specified one. bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) { - DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG); dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG); + dbgs() << "\n"); SDValue Res = SDValue(); if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false)) { - DEBUG(dbgs() << "Node has been custom lowered, done\n"); + LLVM_DEBUG(dbgs() << "Node has been custom lowered, done\n"); return false; } @@ -1349,7 +1351,8 @@ SDValue DAGTypeLegalizer::PromoteIntOp_ADDSUBCARRY(SDNode *N, unsigned OpNo) { /// have invalid operands or may have other results that need promotion, we just /// know that (at least) one result needs expansion. void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) { - DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG); dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG); + dbgs() << "\n"); SDValue Lo, Hi; Lo = Hi = SDValue(); @@ -2887,7 +2890,8 @@ void DAGTypeLegalizer::ExpandIntRes_ATOMIC_LOAD(SDNode *N, /// result types of the node are known to be legal, but other operands of the /// node may need promotion or expansion as well as the specified one. bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) { - DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG); dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG); + dbgs() << "\n"); SDValue Res = SDValue(); if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false)) diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp index e2cee0717cb..20f9a7e6514 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp @@ -224,9 +224,9 @@ bool DAGTypeLegalizer::run() { assert(N->getNodeId() == ReadyToProcess && "Node should be ready if on worklist!"); - DEBUG(dbgs() << "Legalizing node: "; N->dump(&DAG)); + LLVM_DEBUG(dbgs() << "Legalizing node: "; N->dump(&DAG)); if (IgnoreNodeResults(N)) { - DEBUG(dbgs() << "Ignoring node results\n"); + LLVM_DEBUG(dbgs() << "Ignoring node results\n"); goto ScanOperands; } @@ -234,11 +234,11 @@ bool DAGTypeLegalizer::run() { // types are illegal. for (unsigned i = 0, NumResults = N->getNumValues(); i < NumResults; ++i) { EVT ResultVT = N->getValueType(i); - DEBUG(dbgs() << "Analyzing result type: " << - ResultVT.getEVTString() << "\n"); + LLVM_DEBUG(dbgs() << "Analyzing result type: " << ResultVT.getEVTString() + << "\n"); switch (getTypeAction(ResultVT)) { case TargetLowering::TypeLegal: - DEBUG(dbgs() << "Legal result type\n"); + LLVM_DEBUG(dbgs() << "Legal result type\n"); break; // The following calls must take care of *all* of the node's results, // not just the illegal result they were passed (this includes results @@ -296,11 +296,11 @@ ScanOperands: continue; const auto Op = N->getOperand(i); - DEBUG(dbgs() << "Analyzing operand: "; Op.dump(&DAG)); + LLVM_DEBUG(dbgs() << "Analyzing operand: "; Op.dump(&DAG)); EVT OpVT = Op.getValueType(); switch (getTypeAction(OpVT)) { case TargetLowering::TypeLegal: - DEBUG(dbgs() << "Legal operand\n"); + LLVM_DEBUG(dbgs() << "Legal operand\n"); continue; // The following calls must either replace all of the node's results // using ReplaceValueWith, and return "false"; or update the node's @@ -370,7 +370,8 @@ ScanOperands: } if (i == NumOperands) { - DEBUG(dbgs() << "Legally typed node: "; N->dump(&DAG); dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "Legally typed node: "; N->dump(&DAG); + dbgs() << "\n"); } } NodeDone: diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp index 724a909a210..41fc8c0509e 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp @@ -229,7 +229,8 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) { LoadSDNode *LD = cast<LoadSDNode>(Op.getNode()); ISD::LoadExtType ExtType = LD->getExtensionType(); if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) { - DEBUG(dbgs() << "\nLegalizing extending vector load: "; Node->dump(&DAG)); + LLVM_DEBUG(dbgs() << "\nLegalizing extending vector load: "; + Node->dump(&DAG)); switch (TLI.getLoadExtAction(LD->getExtensionType(), LD->getValueType(0), LD->getMemoryVT())) { default: llvm_unreachable("This action is not supported yet!"); @@ -261,8 +262,8 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) { EVT StVT = ST->getMemoryVT(); MVT ValVT = ST->getValue().getSimpleValueType(); if (StVT.isVector() && ST->isTruncatingStore()) { - DEBUG(dbgs() << "\nLegalizing truncating vector store: "; - Node->dump(&DAG)); + LLVM_DEBUG(dbgs() << "\nLegalizing truncating vector store: "; + Node->dump(&DAG)); switch (TLI.getTruncStoreAction(ValVT, StVT)) { default: llvm_unreachable("This action is not supported yet!"); case TargetLowering::Legal: @@ -384,7 +385,7 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) { break; } - DEBUG(dbgs() << "\nLegalizing vector op: "; Node->dump(&DAG)); + LLVM_DEBUG(dbgs() << "\nLegalizing vector op: "; Node->dump(&DAG)); switch (TLI.getOperationAction(Node->getOpcode(), QueryType)) { default: llvm_unreachable("This action is not supported yet!"); @@ -393,16 +394,16 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) { Changed = true; break; case TargetLowering::Legal: - DEBUG(dbgs() << "Legal node: nothing to do\n"); + LLVM_DEBUG(dbgs() << "Legal node: nothing to do\n"); break; case TargetLowering::Custom: { - DEBUG(dbgs() << "Trying custom legalization\n"); + LLVM_DEBUG(dbgs() << "Trying custom legalization\n"); if (SDValue Tmp1 = TLI.LowerOperation(Op, DAG)) { - DEBUG(dbgs() << "Successfully custom legalized node\n"); + LLVM_DEBUG(dbgs() << "Successfully custom legalized node\n"); Result = Tmp1; break; } - DEBUG(dbgs() << "Could not custom legalize node\n"); + LLVM_DEBUG(dbgs() << "Could not custom legalize node\n"); LLVM_FALLTHROUGH; } case TargetLowering::Expand: diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index b15dcbf1a78..b975d8e314b 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -33,9 +33,8 @@ using namespace llvm; //===----------------------------------------------------------------------===// void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) { - DEBUG(dbgs() << "Scalarize node result " << ResNo << ": "; - N->dump(&DAG); - dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "Scalarize node result " << ResNo << ": "; N->dump(&DAG); + dbgs() << "\n"); SDValue R = SDValue(); switch (N->getOpcode()) { @@ -443,9 +442,8 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) { //===----------------------------------------------------------------------===// bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) { - DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": "; - N->dump(&DAG); - dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": "; N->dump(&DAG); + dbgs() << "\n"); SDValue Res = SDValue(); if (!Res.getNode()) { @@ -628,9 +626,7 @@ SDValue DAGTypeLegalizer::ScalarizeVecOp_FP_ROUND(SDNode *N, unsigned OpNo) { /// invalid operands or may have other results that need legalization, we just /// know that (at least) one result needs vector splitting. void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) { - DEBUG(dbgs() << "Split node result: "; - N->dump(&DAG); - dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "Split node result: "; N->dump(&DAG); dbgs() << "\n"); SDValue Lo, Hi; // See if the target wants to custom expand this node. @@ -1376,8 +1372,8 @@ void DAGTypeLegalizer::SplitVecRes_ExtendOp(SDNode *N, SDValue &Lo, std::tie(SplitLoVT, SplitHiVT) = DAG.GetSplitDestVTs(NewSrcVT); if (TLI.isTypeLegal(SrcVT) && !TLI.isTypeLegal(SplitSrcVT) && TLI.isTypeLegal(NewSrcVT) && TLI.isTypeLegal(SplitLoVT)) { - DEBUG(dbgs() << "Split vector extend via incremental extend:"; - N->dump(&DAG); dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "Split vector extend via incremental extend:"; + N->dump(&DAG); dbgs() << "\n"); // Extend the source vector by one step. SDValue NewSrc = DAG.getNode(N->getOpcode(), dl, NewSrcVT, N->getOperand(0)); @@ -1512,9 +1508,7 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, /// the node are known to be legal, but other operands of the node may need /// legalization as well as the specified one. bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) { - DEBUG(dbgs() << "Split node operand: "; - N->dump(&DAG); - dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "Split node operand: "; N->dump(&DAG); dbgs() << "\n"); SDValue Res = SDValue(); // See if the target wants to custom split this node. @@ -2183,9 +2177,8 @@ SDValue DAGTypeLegalizer::SplitVecOp_FCOPYSIGN(SDNode *N) { //===----------------------------------------------------------------------===// void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) { - DEBUG(dbgs() << "Widen node result " << ResNo << ": "; - N->dump(&DAG); - dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "Widen node result " << ResNo << ": "; N->dump(&DAG); + dbgs() << "\n"); // See if the target wants to custom widen this node. if (CustomWidenLowerNode(N, N->getValueType(ResNo))) @@ -3329,9 +3322,8 @@ SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) { // Widen Vector Operand //===----------------------------------------------------------------------===// bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) { - DEBUG(dbgs() << "Widen node operand " << OpNo << ": "; - N->dump(&DAG); - dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "Widen node operand " << OpNo << ": "; N->dump(&DAG); + dbgs() << "\n"); SDValue Res = SDValue(); // See if the target wants to custom widen this node. diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp index f55d85f01e7..3944d7df286 100644 --- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp @@ -116,7 +116,7 @@ private: /// Schedule - Schedule the DAG using list scheduling. void ScheduleDAGFast::Schedule() { - DEBUG(dbgs() << "********** List Scheduling **********\n"); + LLVM_DEBUG(dbgs() << "********** List Scheduling **********\n"); NumLiveRegs = 0; LiveRegDefs.resize(TRI->getNumRegs(), nullptr); @@ -125,8 +125,8 @@ void ScheduleDAGFast::Schedule() { // Build the scheduling graph. BuildSchedGraph(nullptr); - DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su) - SUnits[su].dumpAll(this)); + LLVM_DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su) SUnits[su] + .dumpAll(this)); // Execute the actual scheduling loop. ListScheduleBottomUp(); @@ -181,8 +181,8 @@ void ScheduleDAGFast::ReleasePredecessors(SUnit *SU, unsigned CurCycle) { /// count of its predecessors. If a predecessor pending count is zero, add it to /// the Available queue. void ScheduleDAGFast::ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) { - DEBUG(dbgs() << "*** Scheduling [" << CurCycle << "]: "); - DEBUG(SU->dump(this)); + LLVM_DEBUG(dbgs() << "*** Scheduling [" << CurCycle << "]: "); + LLVM_DEBUG(SU->dump(this)); assert(CurCycle >= SU->getHeight() && "Node scheduled below its height!"); SU->setHeightToAtLeast(CurCycle); @@ -237,7 +237,7 @@ SUnit *ScheduleDAGFast::CopyAndMoveSuccessors(SUnit *SU) { if (!TII->unfoldMemoryOperand(*DAG, N, NewNodes)) return nullptr; - DEBUG(dbgs() << "Unfolding SU # " << SU->NodeNum << "\n"); + LLVM_DEBUG(dbgs() << "Unfolding SU # " << SU->NodeNum << "\n"); assert(NewNodes.size() == 2 && "Expected a load folding node!"); N = NewNodes[1]; @@ -347,7 +347,7 @@ SUnit *ScheduleDAGFast::CopyAndMoveSuccessors(SUnit *SU) { SU = NewSU; } - DEBUG(dbgs() << "Duplicating SU # " << SU->NodeNum << "\n"); + LLVM_DEBUG(dbgs() << "Duplicating SU # " << SU->NodeNum << "\n"); NewSU = Clone(SU); // New SUnit has the exact same predecessors. @@ -593,14 +593,14 @@ void ScheduleDAGFast::ListScheduleBottomUp() { // Issue copies, these can be expensive cross register class copies. SmallVector<SUnit*, 2> Copies; InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies); - DEBUG(dbgs() << "Adding an edge from SU # " << TrySU->NodeNum - << " to SU #" << Copies.front()->NodeNum << "\n"); + LLVM_DEBUG(dbgs() << "Adding an edge from SU # " << TrySU->NodeNum + << " to SU #" << Copies.front()->NodeNum << "\n"); AddPred(TrySU, SDep(Copies.front(), SDep::Artificial)); NewDef = Copies.back(); } - DEBUG(dbgs() << "Adding an edge from SU # " << NewDef->NodeNum - << " to SU #" << TrySU->NodeNum << "\n"); + LLVM_DEBUG(dbgs() << "Adding an edge from SU # " << NewDef->NodeNum + << " to SU #" << TrySU->NodeNum << "\n"); LiveRegDefs[Reg] = NewDef; AddPred(NewDef, SDep(TrySU, SDep::Artificial)); TrySU->isAvailable = false; @@ -667,8 +667,8 @@ void ScheduleDAGLinearize::ScheduleNode(SDNode *N) { // These nodes do not need to be translated into MIs. return; - DEBUG(dbgs() << "\n*** Scheduling: "); - DEBUG(N->dump(DAG)); + LLVM_DEBUG(dbgs() << "\n*** Scheduling: "); + LLVM_DEBUG(N->dump(DAG)); Sequence.push_back(N); unsigned NumOps = N->getNumOperands(); @@ -714,7 +714,7 @@ static SDNode *findGluedUser(SDNode *N) { } void ScheduleDAGLinearize::Schedule() { - DEBUG(dbgs() << "********** DAG Linearization **********\n"); + LLVM_DEBUG(dbgs() << "********** DAG Linearization **********\n"); SmallVector<SDNode*, 8> Glues; unsigned DAGSize = 0; @@ -764,15 +764,13 @@ ScheduleDAGLinearize::EmitSchedule(MachineBasicBlock::iterator &InsertPos) { InstrEmitter Emitter(BB, InsertPos); DenseMap<SDValue, unsigned> VRBaseMap; - DEBUG({ - dbgs() << "\n*** Final schedule ***\n"; - }); + LLVM_DEBUG({ dbgs() << "\n*** Final schedule ***\n"; }); unsigned NumNodes = Sequence.size(); MachineBasicBlock *BB = Emitter.getBlock(); for (unsigned i = 0; i != NumNodes; ++i) { SDNode *N = Sequence[NumNodes-i-1]; - DEBUG(N->dump(DAG)); + LLVM_DEBUG(N->dump(DAG)); Emitter.EmitNode(N, false, false, VRBaseMap); // Emit any debug values associated with the node. @@ -788,7 +786,7 @@ ScheduleDAGLinearize::EmitSchedule(MachineBasicBlock::iterator &InsertPos) { } } - DEBUG(dbgs() << '\n'); + LLVM_DEBUG(dbgs() << '\n'); InsertPos = Emitter.getInsertPos(); return Emitter.getBlock(); diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index 617f84d11ef..73f855f8f84 100644 --- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -347,8 +347,8 @@ static void GetCostForDef(const ScheduleDAGSDNodes::RegDefIter &RegDefPos, /// Schedule - Schedule the DAG using list scheduling. void ScheduleDAGRRList::Schedule() { - DEBUG(dbgs() << "********** List Scheduling " << printMBBReference(*BB) - << " '" << BB->getName() << "' **********\n"); + LLVM_DEBUG(dbgs() << "********** List Scheduling " << printMBBReference(*BB) + << " '" << BB->getName() << "' **********\n"); CurCycle = 0; IssueCount = 0; @@ -365,8 +365,7 @@ void ScheduleDAGRRList::Schedule() { // Build the scheduling graph. BuildSchedGraph(nullptr); - DEBUG(for (SUnit &SU : SUnits) - SU.dumpAll(this)); + LLVM_DEBUG(for (SUnit &SU : SUnits) SU.dumpAll(this)); Topo.InitDAGTopologicalSorting(); AvailableQueue->initNodes(SUnits); @@ -378,11 +377,11 @@ void ScheduleDAGRRList::Schedule() { AvailableQueue->releaseState(); - DEBUG({ - dbgs() << "*** Final schedule ***\n"; - dumpSchedule(); - dbgs() << '\n'; - }); + LLVM_DEBUG({ + dbgs() << "*** Final schedule ***\n"; + dumpSchedule(); + dbgs() << '\n'; + }); } //===----------------------------------------------------------------------===// @@ -729,13 +728,13 @@ static void resetVRegCycle(SUnit *SU); /// count of its predecessors. If a predecessor pending count is zero, add it to /// the Available queue. void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU) { - DEBUG(dbgs() << "\n*** Scheduling [" << CurCycle << "]: "); - DEBUG(SU->dump(this)); + LLVM_DEBUG(dbgs() << "\n*** Scheduling [" << CurCycle << "]: "); + LLVM_DEBUG(SU->dump(this)); #ifndef NDEBUG if (CurCycle < SU->getHeight()) - DEBUG(dbgs() << " Height [" << SU->getHeight() - << "] pipeline stall!\n"); + LLVM_DEBUG(dbgs() << " Height [" << SU->getHeight() + << "] pipeline stall!\n"); #endif // FIXME: Do not modify node height. It may interfere with @@ -828,8 +827,8 @@ void ScheduleDAGRRList::CapturePred(SDep *PredEdge) { /// UnscheduleNodeBottomUp - Remove the node from the schedule, update its and /// its predecessor states to reflect the change. void ScheduleDAGRRList::UnscheduleNodeBottomUp(SUnit *SU) { - DEBUG(dbgs() << "*** Unscheduling [" << SU->getHeight() << "]: "); - DEBUG(SU->dump(this)); + LLVM_DEBUG(dbgs() << "*** Unscheduling [" << SU->getHeight() << "]: "); + LLVM_DEBUG(SU->dump(this)); for (SDep &Pred : SU->Preds) { CapturePred(&Pred); @@ -1011,7 +1010,7 @@ SUnit *ScheduleDAGRRList::TryUnfoldSU(SUnit *SU) { computeLatency(LoadSU); } - DEBUG(dbgs() << "Unfolding SU #" << SU->NodeNum << "\n"); + LLVM_DEBUG(dbgs() << "Unfolding SU #" << SU->NodeNum << "\n"); // Now that we are committed to unfolding replace DAG Uses. for (unsigned i = 0; i != NumVals; ++i) @@ -1118,12 +1117,13 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) { if (!N) return nullptr; - DEBUG(dbgs() << "Considering duplicating the SU\n"); - DEBUG(SU->dump(this)); + LLVM_DEBUG(dbgs() << "Considering duplicating the SU\n"); + LLVM_DEBUG(SU->dump(this)); if (N->getGluedNode() && !TII->canCopyGluedNodeDuringSchedule(N)) { - DEBUG(dbgs() + LLVM_DEBUG( + dbgs() << "Giving up because it has incoming glue and the target does not " "want to copy it\n"); return nullptr; @@ -1134,7 +1134,7 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) { for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) { MVT VT = N->getSimpleValueType(i); if (VT == MVT::Glue) { - DEBUG(dbgs() << "Giving up because it has outgoing glue\n"); + LLVM_DEBUG(dbgs() << "Giving up because it has outgoing glue\n"); return nullptr; } else if (VT == MVT::Other) TryUnfold = true; @@ -1142,8 +1142,9 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) { for (const SDValue &Op : N->op_values()) { MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); if (VT == MVT::Glue && !TII->canCopyGluedNodeDuringSchedule(N)) { - DEBUG(dbgs() << "Giving up because it one of the operands is glue and " - "the target does not want to copy it\n"); + LLVM_DEBUG( + dbgs() << "Giving up because it one of the operands is glue and " + "the target does not want to copy it\n"); return nullptr; } } @@ -1160,7 +1161,7 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) { return SU; } - DEBUG(dbgs() << " Duplicating SU #" << SU->NodeNum << "\n"); + LLVM_DEBUG(dbgs() << " Duplicating SU #" << SU->NodeNum << "\n"); NewSU = CreateClone(SU); // New SUnit has the exact same predecessors. @@ -1421,7 +1422,7 @@ void ScheduleDAGRRList::releaseInterferences(unsigned Reg) { // Furthermore, it may have been made available again, in which case it is // now already in the AvailableQueue. if (SU->isAvailable && !SU->NodeQueueId) { - DEBUG(dbgs() << " Repushing SU #" << SU->NodeNum << '\n'); + LLVM_DEBUG(dbgs() << " Repushing SU #" << SU->NodeNum << '\n'); AvailableQueue->push(SU); } if (i < Interferences.size()) @@ -1442,12 +1443,10 @@ SUnit *ScheduleDAGRRList::PickNodeToScheduleBottomUp() { SmallVector<unsigned, 4> LRegs; if (!DelayForLiveRegsBottomUp(CurSU, LRegs)) break; - DEBUG(dbgs() << " Interfering reg "; - if (LRegs[0] == TRI->getNumRegs()) - dbgs() << "CallResource"; - else - dbgs() << printReg(LRegs[0], TRI); - dbgs() << " SU #" << CurSU->NodeNum << '\n'); + LLVM_DEBUG(dbgs() << " Interfering reg "; + if (LRegs[0] == TRI->getNumRegs()) dbgs() << "CallResource"; + else dbgs() << printReg(LRegs[0], TRI); + dbgs() << " SU #" << CurSU->NodeNum << '\n'); std::pair<LRegsMapT::iterator, bool> LRegsPair = LRegsMap.insert(std::make_pair(CurSU, LRegs)); if (LRegsPair.second) { @@ -1493,17 +1492,17 @@ SUnit *ScheduleDAGRRList::PickNodeToScheduleBottomUp() { if (!BtSU->isPending) AvailableQueue->remove(BtSU); } - DEBUG(dbgs() << "ARTIFICIAL edge from SU(" << BtSU->NodeNum << ") to SU(" - << TrySU->NodeNum << ")\n"); + LLVM_DEBUG(dbgs() << "ARTIFICIAL edge from SU(" << BtSU->NodeNum + << ") to SU(" << TrySU->NodeNum << ")\n"); AddPred(TrySU, SDep(BtSU, SDep::Artificial)); // If one or more successors has been unscheduled, then the current // node is no longer available. if (!TrySU->isAvailable || !TrySU->NodeQueueId) { - DEBUG(dbgs() << "TrySU not available; choosing node from queue\n"); + LLVM_DEBUG(dbgs() << "TrySU not available; choosing node from queue\n"); CurSU = AvailableQueue->pop(); } else { - DEBUG(dbgs() << "TrySU available\n"); + LLVM_DEBUG(dbgs() << "TrySU available\n"); // Available and in AvailableQueue AvailableQueue->remove(TrySU); CurSU = TrySU; @@ -1547,14 +1546,14 @@ SUnit *ScheduleDAGRRList::PickNodeToScheduleBottomUp() { // Issue copies, these can be expensive cross register class copies. SmallVector<SUnit*, 2> Copies; InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies); - DEBUG(dbgs() << " Adding an edge from SU #" << TrySU->NodeNum - << " to SU #" << Copies.front()->NodeNum << "\n"); + LLVM_DEBUG(dbgs() << " Adding an edge from SU #" << TrySU->NodeNum + << " to SU #" << Copies.front()->NodeNum << "\n"); AddPred(TrySU, SDep(Copies.front(), SDep::Artificial)); NewDef = Copies.back(); } - DEBUG(dbgs() << " Adding an edge from SU #" << NewDef->NodeNum - << " to SU #" << TrySU->NodeNum << "\n"); + LLVM_DEBUG(dbgs() << " Adding an edge from SU #" << NewDef->NodeNum + << " to SU #" << TrySU->NodeNum << "\n"); LiveRegDefs[Reg] = NewDef; AddPred(NewDef, SDep(TrySU, SDep::Artificial)); TrySU->isAvailable = false; @@ -1582,8 +1581,8 @@ void ScheduleDAGRRList::ListScheduleBottomUp() { // priority. If it is not ready put it back. Schedule the node. Sequence.reserve(SUnits.size()); while (!AvailableQueue->empty() || !Interferences.empty()) { - DEBUG(dbgs() << "\nExamining Available:\n"; - AvailableQueue->dump(this)); + LLVM_DEBUG(dbgs() << "\nExamining Available:\n"; + AvailableQueue->dump(this)); // Pick the best node to schedule taking all constraints into // consideration. @@ -2046,8 +2045,8 @@ LLVM_DUMP_METHOD void RegReductionPQBase::dumpRegPressure() const { unsigned Id = RC->getID(); unsigned RP = RegPressure[Id]; if (!RP) continue; - DEBUG(dbgs() << TRI->getRegClassName(RC) << ": " << RP << " / " - << RegLimit[Id] << '\n'); + LLVM_DEBUG(dbgs() << TRI->getRegClassName(RC) << ": " << RP << " / " + << RegLimit[Id] << '\n'); } } #endif @@ -2199,14 +2198,15 @@ void RegReductionPQBase::scheduledNode(SUnit *SU) { if (RegPressure[RCId] < Cost) { // Register pressure tracking is imprecise. This can happen. But we try // hard not to let it happen because it likely results in poor scheduling. - DEBUG(dbgs() << " SU(" << SU->NodeNum << ") has too many regdefs\n"); + LLVM_DEBUG(dbgs() << " SU(" << SU->NodeNum + << ") has too many regdefs\n"); RegPressure[RCId] = 0; } else { RegPressure[RCId] -= Cost; } } - DEBUG(dumpRegPressure()); + LLVM_DEBUG(dumpRegPressure()); } void RegReductionPQBase::unscheduledNode(SUnit *SU) { @@ -2286,7 +2286,7 @@ void RegReductionPQBase::unscheduledNode(SUnit *SU) { } } - DEBUG(dumpRegPressure()); + LLVM_DEBUG(dumpRegPressure()); } //===----------------------------------------------------------------------===// @@ -2381,7 +2381,7 @@ static void initVRegCycle(SUnit *SU) { if (!hasOnlyLiveInOpers(SU) || !hasOnlyLiveOutUses(SU)) return; - DEBUG(dbgs() << "VRegCycle: SU(" << SU->NodeNum << ")\n"); + LLVM_DEBUG(dbgs() << "VRegCycle: SU(" << SU->NodeNum << ")\n"); SU->isVRegCycle = true; @@ -2419,7 +2419,7 @@ static bool hasVRegCycleUse(const SUnit *SU) { if (Pred.isCtrl()) continue; // ignore chain preds if (Pred.getSUnit()->isVRegCycle && Pred.getSUnit()->getNode()->getOpcode() == ISD::CopyFromReg) { - DEBUG(dbgs() << " VReg cycle use: SU (" << SU->NodeNum << ")\n"); + LLVM_DEBUG(dbgs() << " VReg cycle use: SU (" << SU->NodeNum << ")\n"); return true; } } @@ -2479,9 +2479,9 @@ static int BUCompareLatency(SUnit *left, SUnit *right, bool checkPref, int LDepth = left->getDepth() - LPenalty; int RDepth = right->getDepth() - RPenalty; if (LDepth != RDepth) { - DEBUG(dbgs() << " Comparing latency of SU (" << left->NodeNum - << ") depth " << LDepth << " vs SU (" << right->NodeNum - << ") depth " << RDepth << "\n"); + LLVM_DEBUG(dbgs() << " Comparing latency of SU (" << left->NodeNum + << ") depth " << LDepth << " vs SU (" << right->NodeNum + << ") depth " << RDepth << "\n"); return LDepth < RDepth ? 1 : -1; } if (left->Latency != right->Latency) @@ -2503,9 +2503,9 @@ static bool BURRSort(SUnit *left, SUnit *right, RegReductionPQBase *SPQ) { static const char *const PhysRegMsg[] = { " has no physreg", " defines a physreg" }; #endif - DEBUG(dbgs() << " SU (" << left->NodeNum << ") " - << PhysRegMsg[LHasPhysReg] << " SU(" << right->NodeNum << ") " - << PhysRegMsg[RHasPhysReg] << "\n"); + LLVM_DEBUG(dbgs() << " SU (" << left->NodeNum << ") " + << PhysRegMsg[LHasPhysReg] << " SU(" << right->NodeNum + << ") " << PhysRegMsg[RHasPhysReg] << "\n"); return LHasPhysReg < RHasPhysReg; } } @@ -2649,13 +2649,13 @@ bool hybrid_ls_rr_sort::operator()(SUnit *left, SUnit *right) const { // Avoid causing spills. If register pressure is high, schedule for // register pressure reduction. if (LHigh && !RHigh) { - DEBUG(dbgs() << " pressure SU(" << left->NodeNum << ") > SU(" - << right->NodeNum << ")\n"); + LLVM_DEBUG(dbgs() << " pressure SU(" << left->NodeNum << ") > SU(" + << right->NodeNum << ")\n"); return true; } else if (!LHigh && RHigh) { - DEBUG(dbgs() << " pressure SU(" << right->NodeNum << ") > SU(" - << left->NodeNum << ")\n"); + LLVM_DEBUG(dbgs() << " pressure SU(" << right->NodeNum << ") > SU(" + << left->NodeNum << ")\n"); return false; } if (!LHigh && !RHigh) { @@ -2717,8 +2717,9 @@ bool ilp_ls_rr_sort::operator()(SUnit *left, SUnit *right) const { RPDiff = SPQ->RegPressureDiff(right, RLiveUses); } if (!DisableSchedRegPressure && LPDiff != RPDiff) { - DEBUG(dbgs() << "RegPressureDiff SU(" << left->NodeNum << "): " << LPDiff - << " != SU(" << right->NodeNum << "): " << RPDiff << "\n"); + LLVM_DEBUG(dbgs() << "RegPressureDiff SU(" << left->NodeNum + << "): " << LPDiff << " != SU(" << right->NodeNum + << "): " << RPDiff << "\n"); return LPDiff > RPDiff; } @@ -2730,8 +2731,9 @@ bool ilp_ls_rr_sort::operator()(SUnit *left, SUnit *right) const { } if (!DisableSchedLiveUses && (LLiveUses != RLiveUses)) { - DEBUG(dbgs() << "Live uses SU(" << left->NodeNum << "): " << LLiveUses - << " != SU(" << right->NodeNum << "): " << RLiveUses << "\n"); + LLVM_DEBUG(dbgs() << "Live uses SU(" << left->NodeNum << "): " << LLiveUses + << " != SU(" << right->NodeNum << "): " << RLiveUses + << "\n"); return LLiveUses < RLiveUses; } @@ -2745,9 +2747,9 @@ bool ilp_ls_rr_sort::operator()(SUnit *left, SUnit *right) const { if (!DisableSchedCriticalPath) { int spread = (int)left->getDepth() - (int)right->getDepth(); if (std::abs(spread) > MaxReorderWindow) { - DEBUG(dbgs() << "Depth of SU(" << left->NodeNum << "): " - << left->getDepth() << " != SU(" << right->NodeNum << "): " - << right->getDepth() << "\n"); + LLVM_DEBUG(dbgs() << "Depth of SU(" << left->NodeNum << "): " + << left->getDepth() << " != SU(" << right->NodeNum + << "): " << right->getDepth() << "\n"); return left->getDepth() < right->getDepth(); } } @@ -2968,9 +2970,10 @@ void RegReductionPQBase::PrescheduleNodesWithMultipleUses() { // Ok, the transformation is safe and the heuristics suggest it is // profitable. Update the graph. - DEBUG(dbgs() << " Prescheduling SU #" << SU.NodeNum - << " next to PredSU #" << PredSU->NodeNum - << " to guide scheduling in the presence of multiple uses\n"); + LLVM_DEBUG( + dbgs() << " Prescheduling SU #" << SU.NodeNum << " next to PredSU #" + << PredSU->NodeNum + << " to guide scheduling in the presence of multiple uses\n"); for (unsigned i = 0; i != PredSU->Succs.size(); ++i) { SDep Edge = PredSU->Succs[i]; assert(!Edge.isAssignedRegDep()); @@ -3059,8 +3062,9 @@ void RegReductionPQBase::AddPseudoTwoAddrDeps() { (isLiveOut && !hasOnlyLiveOutUses(SuccSU)) || (!SU.isCommutable && SuccSU->isCommutable)) && !scheduleDAG->IsReachable(SuccSU, &SU)) { - DEBUG(dbgs() << " Adding a pseudo-two-addr edge from SU #" - << SU.NodeNum << " to SU #" << SuccSU->NodeNum << "\n"); + LLVM_DEBUG(dbgs() + << " Adding a pseudo-two-addr edge from SU #" + << SU.NodeNum << " to SU #" << SuccSU->NodeNum << "\n"); scheduleDAG->AddPred(&SU, SDep(SuccSU, SDep::Artificial)); } } diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp index 07b46b9183a..84055f8ecc1 100644 --- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp @@ -93,8 +93,8 @@ private: /// Schedule - Schedule the DAG using list scheduling. void ScheduleDAGVLIW::Schedule() { - DEBUG(dbgs() << "********** List Scheduling " << printMBBReference(*BB) - << " '" << BB->getName() << "' **********\n"); + LLVM_DEBUG(dbgs() << "********** List Scheduling " << printMBBReference(*BB) + << " '" << BB->getName() << "' **********\n"); // Build the scheduling graph. BuildSchedGraph(AA); @@ -151,8 +151,8 @@ void ScheduleDAGVLIW::releaseSuccessors(SUnit *SU) { /// count of its successors. If a successor pending count is zero, add it to /// the Available queue. void ScheduleDAGVLIW::scheduleNodeTopDown(SUnit *SU, unsigned CurCycle) { - DEBUG(dbgs() << "*** Scheduling [" << CurCycle << "]: "); - DEBUG(SU->dump(this)); + LLVM_DEBUG(dbgs() << "*** Scheduling [" << CurCycle << "]: "); + LLVM_DEBUG(SU->dump(this)); Sequence.push_back(SU); assert(CurCycle >= SU->getDepth() && "Node scheduled above its depth!"); @@ -246,7 +246,7 @@ void ScheduleDAGVLIW::listScheduleTopDown() { } else if (!HasNoopHazards) { // Otherwise, we have a pipeline stall, but no other problem, just advance // the current cycle and try again. - DEBUG(dbgs() << "*** Advancing cycle, no work to do\n"); + LLVM_DEBUG(dbgs() << "*** Advancing cycle, no work to do\n"); HazardRec->AdvanceCycle(); ++NumStalls; ++CurCycle; @@ -254,7 +254,7 @@ void ScheduleDAGVLIW::listScheduleTopDown() { // Otherwise, we have no instructions to issue and we have instructions // that will fault if we don't do this right. This is the case for // processors without pipeline interlocks and other cases. - DEBUG(dbgs() << "*** Emitting noop\n"); + LLVM_DEBUG(dbgs() << "*** Emitting noop\n"); HazardRec->EmitNoop(); Sequence.push_back(nullptr); // NULL here means noop ++NumNoops; diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 688eb78d67a..f486a90380e 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -90,10 +90,7 @@ void SelectionDAG::DAGUpdateListener::NodeUpdated(SDNode*) {} #define DEBUG_TYPE "selectiondag" static void NewSDValueDbgMsg(SDValue V, StringRef Msg, SelectionDAG *G) { - DEBUG( - dbgs() << Msg; - V.getNode()->dump(G); - ); + LLVM_DEBUG(dbgs() << Msg; V.getNode()->dump(G);); } //===----------------------------------------------------------------------===// @@ -7410,8 +7407,9 @@ void SelectionDAG::salvageDebugInfo(SDNode &N) { DV->isIndirect(), DV->getDebugLoc(), DV->getOrder()); ClonedDVs.push_back(Clone); DV->setIsInvalidated(); - DEBUG(dbgs() << "SALVAGE: Rewriting"; N0.getNode()->dumprFull(this); - dbgs() << " into " << *DIExpr << '\n'); + LLVM_DEBUG(dbgs() << "SALVAGE: Rewriting"; + N0.getNode()->dumprFull(this); + dbgs() << " into " << *DIExpr << '\n'); } } } diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index 57eadbb4410..c79a885ece5 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -1102,7 +1102,8 @@ void SelectionDAGBuilder::dropDanglingDebugInfo(const DILocalVariable *Variable, DIExpression *DanglingExpr = DI->getExpression(); if (DanglingVariable == Variable && Expr->fragmentsOverlap(DanglingExpr)) { - DEBUG(dbgs() << "Dropping dangling debug info for " << *DI << "\n"); + LLVM_DEBUG(dbgs() + << "Dropping dangling debug info for " << *DI << "\n"); DDI = DanglingDebugInfo(); } } @@ -1127,24 +1128,24 @@ void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V, SDDbgValue *SDV; if (Val.getNode()) { if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, false, Val)) { - DEBUG(dbgs() << "Resolve dangling debug info [order=" << DbgSDNodeOrder - << "] for:\n " << *DI << "\n"); - DEBUG(dbgs() << " By mapping to:\n "; Val.dump()); + LLVM_DEBUG(dbgs() << "Resolve dangling debug info [order=" + << DbgSDNodeOrder << "] for:\n " << *DI << "\n"); + LLVM_DEBUG(dbgs() << " By mapping to:\n "; Val.dump()); // Increase the SDNodeOrder for the DbgValue here to make sure it is // inserted after the definition of Val when emitting the instructions // after ISel. An alternative could be to teach // ScheduleDAGSDNodes::EmitSchedule to delay the insertion properly. - DEBUG(if (ValSDNodeOrder > DbgSDNodeOrder) - dbgs() << "changing SDNodeOrder from " << DbgSDNodeOrder - << " to " << ValSDNodeOrder << "\n"); + LLVM_DEBUG(if (ValSDNodeOrder > DbgSDNodeOrder) dbgs() + << "changing SDNodeOrder from " << DbgSDNodeOrder << " to " + << ValSDNodeOrder << "\n"); SDV = getDbgValue(Val, Variable, Expr, dl, std::max(DbgSDNodeOrder, ValSDNodeOrder)); DAG.AddDbgValue(SDV, Val.getNode(), false); } else - DEBUG(dbgs() << "Resolved dangling debug info for " << *DI - << "in EmitFuncArgumentDbgValue\n"); + LLVM_DEBUG(dbgs() << "Resolved dangling debug info for " << *DI + << "in EmitFuncArgumentDbgValue\n"); } else - DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n"); + LLVM_DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n"); } DanglingDebugInfoMap[V].clear(); } @@ -2750,7 +2751,7 @@ void SelectionDAGBuilder::visitBinary(const User &I, unsigned Opcode) { } if (isVectorReductionOp(&I)) { Flags.setVectorReduction(true); - DEBUG(dbgs() << "Detected a reduction operation:" << I << "\n"); + LLVM_DEBUG(dbgs() << "Detected a reduction operation:" << I << "\n"); } if (auto *FPOp = dyn_cast<FPMathOperator>(&I)) { Flags.copyFMF(*FPOp); @@ -5142,7 +5143,7 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) { const Value *Address = DI.getVariableLocation(); if (!Address || isa<UndefValue>(Address) || (Address->use_empty() && !isa<Argument>(Address))) { - DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); + LLVM_DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); return nullptr; } @@ -5204,7 +5205,7 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) { // virtual register info from the FuncInfo.ValueMap. if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, true, N)) { - DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); + LLVM_DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); } } return nullptr; @@ -5307,8 +5308,8 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) { return nullptr; } - DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n"); - DEBUG(dbgs() << " Last seen at:\n " << *V << "\n"); + LLVM_DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n"); + LLVM_DEBUG(dbgs() << " Last seen at:\n " << *V << "\n"); return nullptr; } @@ -8629,7 +8630,8 @@ findArgumentCopyElisionCandidates(const DataLayout &DL, continue; } - DEBUG(dbgs() << "Found argument copy elision candidate: " << *AI << '\n'); + LLVM_DEBUG(dbgs() << "Found argument copy elision candidate: " << *AI + << '\n'); // Mark this alloca and store for argument copy elision. *Info = StaticAllocaInfo::Elidable; @@ -8670,8 +8672,9 @@ static void tryToElideArgumentCopy( int OldIndex = AllocaIndex; MachineFrameInfo &MFI = FuncInfo->MF->getFrameInfo(); if (MFI.getObjectSize(FixedIndex) != MFI.getObjectSize(OldIndex)) { - DEBUG(dbgs() << " argument copy elision failed due to bad fixed stack " - "object size\n"); + LLVM_DEBUG( + dbgs() << " argument copy elision failed due to bad fixed stack " + "object size\n"); return; } unsigned RequiredAlignment = AI->getAlignment(); @@ -8680,16 +8683,16 @@ static void tryToElideArgumentCopy( AI->getAllocatedType()); } if (MFI.getObjectAlignment(FixedIndex) < RequiredAlignment) { - DEBUG(dbgs() << " argument copy elision failed: alignment of alloca " - "greater than stack argument alignment (" - << RequiredAlignment << " vs " - << MFI.getObjectAlignment(FixedIndex) << ")\n"); + LLVM_DEBUG(dbgs() << " argument copy elision failed: alignment of alloca " + "greater than stack argument alignment (" + << RequiredAlignment << " vs " + << MFI.getObjectAlignment(FixedIndex) << ")\n"); return; } // Perform the elision. Delete the old stack object and replace its only use // in the variable info map. Mark the stack object as mutable. - DEBUG({ + LLVM_DEBUG({ dbgs() << "Eliding argument copy from " << Arg << " to " << *AI << '\n' << " Replacing frame index " << OldIndex << " with " << FixedIndex << '\n'; @@ -8861,14 +8864,14 @@ void SelectionDAGISel::LowerArguments(const Function &F) { "LowerFormalArguments didn't return a valid chain!"); assert(InVals.size() == Ins.size() && "LowerFormalArguments didn't emit the correct number of values!"); - DEBUG({ - for (unsigned i = 0, e = Ins.size(); i != e; ++i) { - assert(InVals[i].getNode() && - "LowerFormalArguments emitted a null value!"); - assert(EVT(Ins[i].VT) == InVals[i].getValueType() && - "LowerFormalArguments emitted a value with the wrong type!"); - } - }); + LLVM_DEBUG({ + for (unsigned i = 0, e = Ins.size(); i != e; ++i) { + assert(InVals[i].getNode() && + "LowerFormalArguments emitted a null value!"); + assert(EVT(Ins[i].VT) == InVals[i].getValueType() && + "LowerFormalArguments emitted a value with the wrong type!"); + } + }); // Update the DAG with the new chain value resulting from argument lowering. DAG.setRoot(NewRoot); @@ -10012,8 +10015,8 @@ MachineBasicBlock *SelectionDAGBuilder::peelDominantCaseCluster( if (!SwitchPeeled) return SwitchMBB; - DEBUG(dbgs() << "Peeled one top case in switch stmt, prob: " << TopCaseProb - << "\n"); + LLVM_DEBUG(dbgs() << "Peeled one top case in switch stmt, prob: " + << TopCaseProb << "\n"); // Record the MBB for the peeled switch statement. MachineFunction::iterator BBI(SwitchMBB); @@ -10030,10 +10033,11 @@ MachineBasicBlock *SelectionDAGBuilder::peelDominantCaseCluster( Clusters.erase(PeeledCaseIt); for (CaseCluster &CC : Clusters) { - DEBUG(dbgs() << "Scale the probablity for one cluster, before scaling: " - << CC.Prob << "\n"); + LLVM_DEBUG( + dbgs() << "Scale the probablity for one cluster, before scaling: " + << CC.Prob << "\n"); CC.Prob = scaleCaseProbality(CC.Prob, TopCaseProb); - DEBUG(dbgs() << "After scaling: " << CC.Prob << "\n"); + LLVM_DEBUG(dbgs() << "After scaling: " << CC.Prob << "\n"); } PeeledCaseProb = TopCaseProb; return PeeledSwitchMBB; @@ -10112,11 +10116,13 @@ void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) { findJumpTables(Clusters, &SI, DefaultMBB); findBitTestClusters(Clusters, &SI); - DEBUG({ + LLVM_DEBUG({ dbgs() << "Case clusters: "; for (const CaseCluster &C : Clusters) { - if (C.Kind == CC_JumpTable) dbgs() << "JT:"; - if (C.Kind == CC_BitTests) dbgs() << "BT:"; + if (C.Kind == CC_JumpTable) + dbgs() << "JT:"; + if (C.Kind == CC_BitTests) + dbgs() << "BT:"; C.Low->getValue().print(dbgs(), true); if (C.Low != C.High) { diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index f8ccb9cbbab..f9e4bc6196b 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -212,26 +212,27 @@ namespace llvm { return; IS.OptLevel = NewOptLevel; IS.TM.setOptLevel(NewOptLevel); - DEBUG(dbgs() << "\nChanging optimization level for Function " - << IS.MF->getFunction().getName() << "\n"); - DEBUG(dbgs() << "\tBefore: -O" << SavedOptLevel - << " ; After: -O" << NewOptLevel << "\n"); + LLVM_DEBUG(dbgs() << "\nChanging optimization level for Function " + << IS.MF->getFunction().getName() << "\n"); + LLVM_DEBUG(dbgs() << "\tBefore: -O" << SavedOptLevel << " ; After: -O" + << NewOptLevel << "\n"); SavedFastISel = IS.TM.Options.EnableFastISel; if (NewOptLevel == CodeGenOpt::None) { IS.TM.setFastISel(IS.TM.getO0WantsFastISel()); - DEBUG(dbgs() << "\tFastISel is " - << (IS.TM.Options.EnableFastISel ? "enabled" : "disabled") - << "\n"); + LLVM_DEBUG( + dbgs() << "\tFastISel is " + << (IS.TM.Options.EnableFastISel ? "enabled" : "disabled") + << "\n"); } } ~OptLevelChanger() { if (IS.OptLevel == SavedOptLevel) return; - DEBUG(dbgs() << "\nRestoring optimization level for Function " - << IS.MF->getFunction().getName() << "\n"); - DEBUG(dbgs() << "\tBefore: -O" << IS.OptLevel - << " ; After: -O" << SavedOptLevel << "\n"); + LLVM_DEBUG(dbgs() << "\nRestoring optimization level for Function " + << IS.MF->getFunction().getName() << "\n"); + LLVM_DEBUG(dbgs() << "\tBefore: -O" << IS.OptLevel << " ; After: -O" + << SavedOptLevel << "\n"); IS.OptLevel = SavedOptLevel; IS.TM.setOptLevel(SavedOptLevel); IS.TM.setFastISel(SavedFastISel); @@ -412,7 +413,7 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { auto *LIWP = getAnalysisIfAvailable<LoopInfoWrapperPass>(); LoopInfo *LI = LIWP ? &LIWP->getLoopInfo() : nullptr; - DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); + LLVM_DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); SplitCriticalSideEffectEdges(const_cast<Function &>(Fn), DT, LI); @@ -516,8 +517,8 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { // FIXME: VR def may not be in entry block. Def->getParent()->insert(std::next(InsertPos), MI); } else - DEBUG(dbgs() << "Dropping debug info for dead vreg" - << TargetRegisterInfo::virtReg2Index(Reg) << "\n"); + LLVM_DEBUG(dbgs() << "Dropping debug info for dead vreg" + << TargetRegisterInfo::virtReg2Index(Reg) << "\n"); } // If Reg is live-in then update debug info to track its copy in a vreg. @@ -624,8 +625,8 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { // at this point. FuncInfo->clear(); - DEBUG(dbgs() << "*** MachineFunction at end of ISel ***\n"); - DEBUG(MF->print(dbgs())); + LLVM_DEBUG(dbgs() << "*** MachineFunction at end of ISel ***\n"); + LLVM_DEBUG(MF->print(dbgs())); return true; } @@ -735,9 +736,10 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { BlockName = (MF->getName() + ":" + FuncInfo->MBB->getBasicBlock()->getName()).str(); } - DEBUG(dbgs() << "Initial selection DAG: " << printMBBReference(*FuncInfo->MBB) - << " '" << BlockName << "'\n"; - CurDAG->dump()); + LLVM_DEBUG(dbgs() << "Initial selection DAG: " + << printMBBReference(*FuncInfo->MBB) << " '" << BlockName + << "'\n"; + CurDAG->dump()); if (ViewDAGCombine1 && MatchFilterBB) CurDAG->viewGraph("dag-combine1 input for " + BlockName); @@ -752,10 +754,10 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { if (TTI.hasBranchDivergence()) CurDAG->VerifyDAGDiverence(); - DEBUG(dbgs() << "Optimized lowered selection DAG: " - << printMBBReference(*FuncInfo->MBB) << " '" << BlockName - << "'\n"; - CurDAG->dump()); + LLVM_DEBUG(dbgs() << "Optimized lowered selection DAG: " + << printMBBReference(*FuncInfo->MBB) << " '" << BlockName + << "'\n"; + CurDAG->dump()); // Second step, hack on the DAG until it only uses operations and types that // the target supports. @@ -772,10 +774,10 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { if (TTI.hasBranchDivergence()) CurDAG->VerifyDAGDiverence(); - DEBUG(dbgs() << "Type-legalized selection DAG: " - << printMBBReference(*FuncInfo->MBB) << " '" << BlockName - << "'\n"; - CurDAG->dump()); + LLVM_DEBUG(dbgs() << "Type-legalized selection DAG: " + << printMBBReference(*FuncInfo->MBB) << " '" << BlockName + << "'\n"; + CurDAG->dump()); // Only allow creation of legal node types. CurDAG->NewNodesMustHaveLegalTypes = true; @@ -794,10 +796,10 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { if (TTI.hasBranchDivergence()) CurDAG->VerifyDAGDiverence(); - DEBUG(dbgs() << "Optimized type-legalized selection DAG: " - << printMBBReference(*FuncInfo->MBB) << " '" << BlockName - << "'\n"; - CurDAG->dump()); + LLVM_DEBUG(dbgs() << "Optimized type-legalized selection DAG: " + << printMBBReference(*FuncInfo->MBB) << " '" << BlockName + << "'\n"; + CurDAG->dump()); } { @@ -807,10 +809,10 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { } if (Changed) { - DEBUG(dbgs() << "Vector-legalized selection DAG: " - << printMBBReference(*FuncInfo->MBB) << " '" << BlockName - << "'\n"; - CurDAG->dump()); + LLVM_DEBUG(dbgs() << "Vector-legalized selection DAG: " + << printMBBReference(*FuncInfo->MBB) << " '" << BlockName + << "'\n"; + CurDAG->dump()); { NamedRegionTimer T("legalize_types2", "Type Legalization 2", GroupName, @@ -818,10 +820,10 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { CurDAG->LegalizeTypes(); } - DEBUG(dbgs() << "Vector/type-legalized selection DAG: " - << printMBBReference(*FuncInfo->MBB) << " '" << BlockName - << "'\n"; - CurDAG->dump()); + LLVM_DEBUG(dbgs() << "Vector/type-legalized selection DAG: " + << printMBBReference(*FuncInfo->MBB) << " '" << BlockName + << "'\n"; + CurDAG->dump()); if (ViewDAGCombineLT && MatchFilterBB) CurDAG->viewGraph("dag-combine-lv input for " + BlockName); @@ -833,10 +835,10 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { CurDAG->Combine(AfterLegalizeVectorOps, AA, OptLevel); } - DEBUG(dbgs() << "Optimized vector-legalized selection DAG: " - << printMBBReference(*FuncInfo->MBB) << " '" << BlockName - << "'\n"; - CurDAG->dump()); + LLVM_DEBUG(dbgs() << "Optimized vector-legalized selection DAG: " + << printMBBReference(*FuncInfo->MBB) << " '" << BlockName + << "'\n"; + CurDAG->dump()); if (TTI.hasBranchDivergence()) CurDAG->VerifyDAGDiverence(); @@ -854,10 +856,10 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { if (TTI.hasBranchDivergence()) CurDAG->VerifyDAGDiverence(); - DEBUG(dbgs() << "Legalized selection DAG: " - << printMBBReference(*FuncInfo->MBB) << " '" << BlockName - << "'\n"; - CurDAG->dump()); + LLVM_DEBUG(dbgs() << "Legalized selection DAG: " + << printMBBReference(*FuncInfo->MBB) << " '" << BlockName + << "'\n"; + CurDAG->dump()); if (ViewDAGCombine2 && MatchFilterBB) CurDAG->viewGraph("dag-combine2 input for " + BlockName); @@ -872,10 +874,10 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { if (TTI.hasBranchDivergence()) CurDAG->VerifyDAGDiverence(); - DEBUG(dbgs() << "Optimized legalized selection DAG: " - << printMBBReference(*FuncInfo->MBB) << " '" << BlockName - << "'\n"; - CurDAG->dump()); + LLVM_DEBUG(dbgs() << "Optimized legalized selection DAG: " + << printMBBReference(*FuncInfo->MBB) << " '" << BlockName + << "'\n"; + CurDAG->dump()); if (OptLevel != CodeGenOpt::None) ComputeLiveOutVRegInfo(); @@ -891,10 +893,10 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { DoInstructionSelection(); } - DEBUG(dbgs() << "Selected selection DAG: " - << printMBBReference(*FuncInfo->MBB) << " '" << BlockName - << "'\n"; - CurDAG->dump()); + LLVM_DEBUG(dbgs() << "Selected selection DAG: " + << printMBBReference(*FuncInfo->MBB) << " '" << BlockName + << "'\n"; + CurDAG->dump()); if (ViewSchedDAGs && MatchFilterBB) CurDAG->viewGraph("scheduler input for " + BlockName); @@ -1013,9 +1015,9 @@ int SelectionDAGISel::getUninvalidatedNodeId(SDNode *N) { } void SelectionDAGISel::DoInstructionSelection() { - DEBUG(dbgs() << "===== Instruction selection begins: " - << printMBBReference(*FuncInfo->MBB) << " '" - << FuncInfo->MBB->getName() << "'\n"); + LLVM_DEBUG(dbgs() << "===== Instruction selection begins: " + << printMBBReference(*FuncInfo->MBB) << " '" + << FuncInfo->MBB->getName() << "'\n"); PreprocessISelDAG(); @@ -1087,8 +1089,8 @@ void SelectionDAGISel::DoInstructionSelection() { if (Node->isStrictFPOpcode()) Node = CurDAG->mutateStrictFPToFP(Node); - DEBUG(dbgs() << "\nISEL: Starting selection on root node: "; - Node->dump(CurDAG)); + LLVM_DEBUG(dbgs() << "\nISEL: Starting selection on root node: "; + Node->dump(CurDAG)); Select(Node); } @@ -1096,7 +1098,7 @@ void SelectionDAGISel::DoInstructionSelection() { CurDAG->setRoot(Dummy.getValue()); } - DEBUG(dbgs() << "\n===== Instruction selection ends:\n"); + LLVM_DEBUG(dbgs() << "\n===== Instruction selection ends:\n"); PostprocessISelDAG(); } @@ -1486,7 +1488,7 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { // Initialize the Fast-ISel state, if needed. FastISel *FastIS = nullptr; if (TM.Options.EnableFastISel) { - DEBUG(dbgs() << "Enabling fast-isel\n"); + LLVM_DEBUG(dbgs() << "Enabling fast-isel\n"); FastIS = TLI->createFastISel(*FuncInfo, LibInfo); } @@ -1837,12 +1839,12 @@ FindSplitPointForStackProtector(MachineBasicBlock *BB) { void SelectionDAGISel::FinishBasicBlock() { - DEBUG(dbgs() << "Total amount of phi nodes to update: " - << FuncInfo->PHINodesToUpdate.size() << "\n"; - for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) - dbgs() << "Node " << i << " : (" - << FuncInfo->PHINodesToUpdate[i].first - << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n"); + LLVM_DEBUG(dbgs() << "Total amount of phi nodes to update: " + << FuncInfo->PHINodesToUpdate.size() << "\n"; + for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; + ++i) dbgs() + << "Node " << i << " : (" << FuncInfo->PHINodesToUpdate[i].first + << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n"); // Next, now that we know what the last MBB the LLVM BB expanded is, update // PHI nodes in successors. @@ -2473,7 +2475,7 @@ void SelectionDAGISel::UpdateChains( if (!NowDeadNodes.empty()) CurDAG->RemoveDeadNodes(NowDeadNodes); - DEBUG(dbgs() << "ISEL: Match complete!\n"); + LLVM_DEBUG(dbgs() << "ISEL: Match complete!\n"); } /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains @@ -2961,7 +2963,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch, // update the chain results when the pattern is complete. SmallVector<SDNode*, 3> ChainNodesMatched; - DEBUG(dbgs() << "ISEL: Starting pattern match\n"); + LLVM_DEBUG(dbgs() << "ISEL: Starting pattern match\n"); // Determine where to start the interpreter. Normally we start at opcode #0, // but if the state machine starts with an OPC_SwitchOpcode, then we @@ -2973,7 +2975,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch, // Already computed the OpcodeOffset table, just index into it. if (N.getOpcode() < OpcodeOffset.size()) MatcherIndex = OpcodeOffset[N.getOpcode()]; - DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n"); + LLVM_DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n"); } else if (MatcherTable[0] == OPC_SwitchOpcode) { // Otherwise, the table isn't computed, but the state machine does start @@ -3040,9 +3042,10 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch, if (!Result) break; - DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at " - << "index " << MatcherIndexOfPredicate - << ", continuing at " << FailIndex << "\n"); + LLVM_DEBUG( + dbgs() << " Skipped scope entry (due to false predicate) at " + << "index " << MatcherIndexOfPredicate << ", continuing at " + << FailIndex << "\n"); ++NumDAGIselRetries; // Otherwise, we know that this case of the Scope is guaranteed to fail, @@ -3091,11 +3094,8 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch, if (auto *MN = dyn_cast<MemSDNode>(N)) MatchedMemRefs.push_back(MN->getMemOperand()); else { - DEBUG( - dbgs() << "Expected MemSDNode "; - N->dump(CurDAG); - dbgs() << '\n' - ); + LLVM_DEBUG(dbgs() << "Expected MemSDNode "; N->dump(CurDAG); + dbgs() << '\n'); } continue; @@ -3216,8 +3216,8 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch, if (CaseSize == 0) break; // Otherwise, execute the case we found. - DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart - << " to " << MatcherIndex << "\n"); + LLVM_DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart << " to " + << MatcherIndex << "\n"); continue; } @@ -3248,8 +3248,9 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch, if (CaseSize == 0) break; // Otherwise, execute the case we found. - DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() - << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); + LLVM_DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() + << "] from " << SwitchStart << " to " << MatcherIndex + << '\n'); continue; } case OPC_CheckChild0Type: case OPC_CheckChild1Type: @@ -3629,14 +3630,11 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch, Res->setMemRefs(MemRefs, MemRefs + NumMemRefs); } - DEBUG( - if (!MatchedMemRefs.empty() && Res->memoperands_empty()) - dbgs() << " Dropping mem operands\n"; - dbgs() << " " - << (IsMorphNodeTo ? "Morphed" : "Created") - << " node: "; - Res->dump(CurDAG); - ); + LLVM_DEBUG(if (!MatchedMemRefs.empty() && Res->memoperands_empty()) dbgs() + << " Dropping mem operands\n"; + dbgs() << " " << (IsMorphNodeTo ? "Morphed" : "Created") + << " node: "; + Res->dump(CurDAG);); // If this was a MorphNodeTo then we're completely done! if (IsMorphNodeTo) { @@ -3698,7 +3696,8 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch, // If the code reached this point, then the match failed. See if there is // another child to try in the current 'Scope', otherwise pop it until we // find a case to check. - DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); + LLVM_DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex + << "\n"); ++NumDAGIselRetries; while (true) { if (MatchScopes.empty()) { @@ -3718,7 +3717,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch, MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); MatcherIndex = LastScope.FailIndex; - DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n"); + LLVM_DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n"); InputChain = LastScope.InputChain; InputGlue = LastScope.InputGlue; diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp index be4ab094bf4..3b19bff4743 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp @@ -229,7 +229,7 @@ bool SelectionDAG::setSubgraphColorHelper(SDNode *N, const char *Color, DenseSet if (level >= 20) { if (!printed) { printed = true; - DEBUG(dbgs() << "setSubgraphColor hit max level\n"); + LLVM_DEBUG(dbgs() << "setSubgraphColor hit max level\n"); } return true; } diff --git a/llvm/lib/CodeGen/ShrinkWrap.cpp b/llvm/lib/CodeGen/ShrinkWrap.cpp index d4fbe0a8df0..7647df0d340 100644 --- a/llvm/lib/CodeGen/ShrinkWrap.cpp +++ b/llvm/lib/CodeGen/ShrinkWrap.cpp @@ -254,7 +254,7 @@ bool ShrinkWrap::useOrDefCSROrFI(const MachineInstr &MI, RegScavenger *RS) const { if (MI.getOpcode() == FrameSetupOpcode || MI.getOpcode() == FrameDestroyOpcode) { - DEBUG(dbgs() << "Frame instruction: " << MI << '\n'); + LLVM_DEBUG(dbgs() << "Frame instruction: " << MI << '\n'); return true; } for (const MachineOperand &MO : MI.operands()) { @@ -286,8 +286,8 @@ bool ShrinkWrap::useOrDefCSROrFI(const MachineInstr &MI, } // Skip FrameIndex operands in DBG_VALUE instructions. if (UseOrDefCSR || (MO.isFI() && !MI.isDebugValue())) { - DEBUG(dbgs() << "Use or define CSR(" << UseOrDefCSR << ") or FI(" - << MO.isFI() << "): " << MI << '\n'); + LLVM_DEBUG(dbgs() << "Use or define CSR(" << UseOrDefCSR << ") or FI(" + << MO.isFI() << "): " << MI << '\n'); return true; } } @@ -318,7 +318,7 @@ void ShrinkWrap::updateSaveRestorePoints(MachineBasicBlock &MBB, Save = MDT->findNearestCommonDominator(Save, &MBB); if (!Save) { - DEBUG(dbgs() << "Found a block that is not reachable from Entry\n"); + LLVM_DEBUG(dbgs() << "Found a block that is not reachable from Entry\n"); return; } @@ -352,7 +352,8 @@ void ShrinkWrap::updateSaveRestorePoints(MachineBasicBlock &MBB, } if (!Restore) { - DEBUG(dbgs() << "Restore point needs to be spanned on several blocks\n"); + LLVM_DEBUG( + dbgs() << "Restore point needs to be spanned on several blocks\n"); return; } @@ -435,7 +436,7 @@ bool ShrinkWrap::runOnMachineFunction(MachineFunction &MF) { if (skipFunction(MF.getFunction()) || MF.empty() || !isShrinkWrapEnabled(MF)) return false; - DEBUG(dbgs() << "**** Analysing " << MF.getName() << '\n'); + LLVM_DEBUG(dbgs() << "**** Analysing " << MF.getName() << '\n'); init(MF); @@ -447,7 +448,7 @@ bool ShrinkWrap::runOnMachineFunction(MachineFunction &MF) { // results. Moreover, we may miss that the prologue and // epilogue are not in the same loop, leading to unbalanced // construction/deconstruction of the stack frame. - DEBUG(dbgs() << "Irreducible CFGs are not supported yet\n"); + LLVM_DEBUG(dbgs() << "Irreducible CFGs are not supported yet\n"); return false; } @@ -456,11 +457,11 @@ bool ShrinkWrap::runOnMachineFunction(MachineFunction &MF) { TRI->requiresRegisterScavenging(MF) ? new RegScavenger() : nullptr); for (MachineBasicBlock &MBB : MF) { - DEBUG(dbgs() << "Look into: " << MBB.getNumber() << ' ' << MBB.getName() - << '\n'); + LLVM_DEBUG(dbgs() << "Look into: " << MBB.getNumber() << ' ' + << MBB.getName() << '\n'); if (MBB.isEHFuncletEntry()) { - DEBUG(dbgs() << "EH Funclets are not supported yet.\n"); + LLVM_DEBUG(dbgs() << "EH Funclets are not supported yet.\n"); return false; } @@ -474,7 +475,7 @@ bool ShrinkWrap::runOnMachineFunction(MachineFunction &MF) { // basic block can jump out from the middle. updateSaveRestorePoints(MBB, RS.get()); if (!ArePointsInteresting()) { - DEBUG(dbgs() << "EHPad prevents shrink-wrapping\n"); + LLVM_DEBUG(dbgs() << "EHPad prevents shrink-wrapping\n"); return false; } continue; @@ -489,7 +490,7 @@ bool ShrinkWrap::runOnMachineFunction(MachineFunction &MF) { // If we are at a point where we cannot improve the placement of // save/restore instructions, just give up. if (!ArePointsInteresting()) { - DEBUG(dbgs() << "No Shrink wrap candidate found\n"); + LLVM_DEBUG(dbgs() << "No Shrink wrap candidate found\n"); return false; } // No need to look for other instructions, this basic block @@ -502,20 +503,21 @@ bool ShrinkWrap::runOnMachineFunction(MachineFunction &MF) { // because it means we did not encounter any frame/CSR related code. // Otherwise, we would have returned from the previous loop. assert(!Save && !Restore && "We miss a shrink-wrap opportunity?!"); - DEBUG(dbgs() << "Nothing to shrink-wrap\n"); + LLVM_DEBUG(dbgs() << "Nothing to shrink-wrap\n"); return false; } - DEBUG(dbgs() << "\n ** Results **\nFrequency of the Entry: " << EntryFreq - << '\n'); + LLVM_DEBUG(dbgs() << "\n ** Results **\nFrequency of the Entry: " << EntryFreq + << '\n'); const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); do { - DEBUG(dbgs() << "Shrink wrap candidates (#, Name, Freq):\nSave: " - << Save->getNumber() << ' ' << Save->getName() << ' ' - << MBFI->getBlockFreq(Save).getFrequency() << "\nRestore: " - << Restore->getNumber() << ' ' << Restore->getName() << ' ' - << MBFI->getBlockFreq(Restore).getFrequency() << '\n'); + LLVM_DEBUG(dbgs() << "Shrink wrap candidates (#, Name, Freq):\nSave: " + << Save->getNumber() << ' ' << Save->getName() << ' ' + << MBFI->getBlockFreq(Save).getFrequency() + << "\nRestore: " << Restore->getNumber() << ' ' + << Restore->getName() << ' ' + << MBFI->getBlockFreq(Restore).getFrequency() << '\n'); bool IsSaveCheap, TargetCanUseSaveAsPrologue = false; if (((IsSaveCheap = EntryFreq >= MBFI->getBlockFreq(Save).getFrequency()) && @@ -523,7 +525,8 @@ bool ShrinkWrap::runOnMachineFunction(MachineFunction &MF) { ((TargetCanUseSaveAsPrologue = TFI->canUseAsPrologue(*Save)) && TFI->canUseAsEpilogue(*Restore))) break; - DEBUG(dbgs() << "New points are too expensive or invalid for the target\n"); + LLVM_DEBUG( + dbgs() << "New points are too expensive or invalid for the target\n"); MachineBasicBlock *NewBB; if (!IsSaveCheap || !TargetCanUseSaveAsPrologue) { Save = FindIDom<>(*Save, Save->predecessors(), *MDT); @@ -545,9 +548,10 @@ bool ShrinkWrap::runOnMachineFunction(MachineFunction &MF) { return false; } - DEBUG(dbgs() << "Final shrink wrap candidates:\nSave: " << Save->getNumber() - << ' ' << Save->getName() << "\nRestore: " - << Restore->getNumber() << ' ' << Restore->getName() << '\n'); + LLVM_DEBUG(dbgs() << "Final shrink wrap candidates:\nSave: " + << Save->getNumber() << ' ' << Save->getName() + << "\nRestore: " << Restore->getNumber() << ' ' + << Restore->getName() << '\n'); MachineFrameInfo &MFI = MF.getFrameInfo(); MFI.setSavePoint(Save); diff --git a/llvm/lib/CodeGen/SjLjEHPrepare.cpp b/llvm/lib/CodeGen/SjLjEHPrepare.cpp index 611ec97689a..f657c16a320 100644 --- a/llvm/lib/CodeGen/SjLjEHPrepare.cpp +++ b/llvm/lib/CodeGen/SjLjEHPrepare.cpp @@ -307,8 +307,8 @@ void SjLjEHPrepare::lowerAcrossUnwindEdges(Function &F, for (InvokeInst *Invoke : Invokes) { BasicBlock *UnwindBlock = Invoke->getUnwindDest(); if (UnwindBlock != &BB && LiveBBs.count(UnwindBlock)) { - DEBUG(dbgs() << "SJLJ Spill: " << Inst << " around " - << UnwindBlock->getName() << "\n"); + LLVM_DEBUG(dbgs() << "SJLJ Spill: " << Inst << " around " + << UnwindBlock->getName() << "\n"); NeedsSpill = true; break; } diff --git a/llvm/lib/CodeGen/SlotIndexes.cpp b/llvm/lib/CodeGen/SlotIndexes.cpp index ff706a6a655..ed74b3e4fa1 100644 --- a/llvm/lib/CodeGen/SlotIndexes.cpp +++ b/llvm/lib/CodeGen/SlotIndexes.cpp @@ -97,7 +97,7 @@ bool SlotIndexes::runOnMachineFunction(MachineFunction &fn) { // Sort the Idx2MBBMap llvm::sort(idx2MBBMap.begin(), idx2MBBMap.end(), Idx2MBBCompare()); - DEBUG(mf->print(dbgs(), this)); + LLVM_DEBUG(mf->print(dbgs(), this)); // And we're done! return false; @@ -147,7 +147,7 @@ void SlotIndexes::removeSingleMachineInstrFromMaps(MachineInstr &MI) { void SlotIndexes::renumberIndexes() { // Renumber updates the index of every element of the index list. - DEBUG(dbgs() << "\n*** Renumbering SlotIndexes ***\n"); + LLVM_DEBUG(dbgs() << "\n*** Renumbering SlotIndexes ***\n"); ++NumGlobalRenum; unsigned index = 0; @@ -174,8 +174,8 @@ void SlotIndexes::renumberIndexes(IndexList::iterator curItr) { // If the next index is bigger, we have caught up. } while (curItr != indexList.end() && curItr->getIndex() <= index); - DEBUG(dbgs() << "\n*** Renumbered SlotIndexes " << startItr->getIndex() << '-' - << index << " ***\n"); + LLVM_DEBUG(dbgs() << "\n*** Renumbered SlotIndexes " << startItr->getIndex() + << '-' << index << " ***\n"); ++NumLocalRenum; } diff --git a/llvm/lib/CodeGen/SplitKit.cpp b/llvm/lib/CodeGen/SplitKit.cpp index 9c0b6c39952..d639f447530 100644 --- a/llvm/lib/CodeGen/SplitKit.cpp +++ b/llvm/lib/CodeGen/SplitKit.cpp @@ -192,7 +192,7 @@ void SplitAnalysis::analyzeUses() { // I am looking at you, RegisterCoalescer! DidRepairRange = true; ++NumRepairs; - DEBUG(dbgs() << "*** Fixing inconsistent live interval! ***\n"); + LLVM_DEBUG(dbgs() << "*** Fixing inconsistent live interval! ***\n"); const_cast<LiveIntervals&>(LIS) .shrinkToUses(const_cast<LiveInterval*>(CurLI)); UseBlocks.clear(); @@ -202,10 +202,9 @@ void SplitAnalysis::analyzeUses() { assert(fixed && "Couldn't fix broken live interval"); } - DEBUG(dbgs() << "Analyze counted " - << UseSlots.size() << " instrs in " - << UseBlocks.size() << " blocks, through " - << NumThroughBlocks << " blocks.\n"); + LLVM_DEBUG(dbgs() << "Analyze counted " << UseSlots.size() << " instrs in " + << UseBlocks.size() << " blocks, through " + << NumThroughBlocks << " blocks.\n"); } /// calcLiveBlockInfo - Fill the LiveBlocks array with information about blocks @@ -686,20 +685,20 @@ unsigned SplitEditor::openIntv() { void SplitEditor::selectIntv(unsigned Idx) { assert(Idx != 0 && "Cannot select the complement interval"); assert(Idx < Edit->size() && "Can only select previously opened interval"); - DEBUG(dbgs() << " selectIntv " << OpenIdx << " -> " << Idx << '\n'); + LLVM_DEBUG(dbgs() << " selectIntv " << OpenIdx << " -> " << Idx << '\n'); OpenIdx = Idx; } SlotIndex SplitEditor::enterIntvBefore(SlotIndex Idx) { assert(OpenIdx && "openIntv not called before enterIntvBefore"); - DEBUG(dbgs() << " enterIntvBefore " << Idx); + LLVM_DEBUG(dbgs() << " enterIntvBefore " << Idx); Idx = Idx.getBaseIndex(); VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx); if (!ParentVNI) { - DEBUG(dbgs() << ": not live\n"); + LLVM_DEBUG(dbgs() << ": not live\n"); return Idx; } - DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n'); + LLVM_DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n'); MachineInstr *MI = LIS.getInstructionFromIndex(Idx); assert(MI && "enterIntvBefore called with invalid index"); @@ -709,14 +708,14 @@ SlotIndex SplitEditor::enterIntvBefore(SlotIndex Idx) { SlotIndex SplitEditor::enterIntvAfter(SlotIndex Idx) { assert(OpenIdx && "openIntv not called before enterIntvAfter"); - DEBUG(dbgs() << " enterIntvAfter " << Idx); + LLVM_DEBUG(dbgs() << " enterIntvAfter " << Idx); Idx = Idx.getBoundaryIndex(); VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx); if (!ParentVNI) { - DEBUG(dbgs() << ": not live\n"); + LLVM_DEBUG(dbgs() << ": not live\n"); return Idx; } - DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n'); + LLVM_DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n'); MachineInstr *MI = LIS.getInstructionFromIndex(Idx); assert(MI && "enterIntvAfter called with invalid index"); @@ -729,18 +728,18 @@ SlotIndex SplitEditor::enterIntvAtEnd(MachineBasicBlock &MBB) { assert(OpenIdx && "openIntv not called before enterIntvAtEnd"); SlotIndex End = LIS.getMBBEndIdx(&MBB); SlotIndex Last = End.getPrevSlot(); - DEBUG(dbgs() << " enterIntvAtEnd " << printMBBReference(MBB) << ", " - << Last); + LLVM_DEBUG(dbgs() << " enterIntvAtEnd " << printMBBReference(MBB) << ", " + << Last); VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Last); if (!ParentVNI) { - DEBUG(dbgs() << ": not live\n"); + LLVM_DEBUG(dbgs() << ": not live\n"); return End; } - DEBUG(dbgs() << ": valno " << ParentVNI->id); + LLVM_DEBUG(dbgs() << ": valno " << ParentVNI->id); VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Last, MBB, SA.getLastSplitPointIter(&MBB)); RegAssign.insert(VNI->def, End, OpenIdx); - DEBUG(dump()); + LLVM_DEBUG(dump()); return VNI->def; } @@ -751,23 +750,23 @@ void SplitEditor::useIntv(const MachineBasicBlock &MBB) { void SplitEditor::useIntv(SlotIndex Start, SlotIndex End) { assert(OpenIdx && "openIntv not called before useIntv"); - DEBUG(dbgs() << " useIntv [" << Start << ';' << End << "):"); + LLVM_DEBUG(dbgs() << " useIntv [" << Start << ';' << End << "):"); RegAssign.insert(Start, End, OpenIdx); - DEBUG(dump()); + LLVM_DEBUG(dump()); } SlotIndex SplitEditor::leaveIntvAfter(SlotIndex Idx) { assert(OpenIdx && "openIntv not called before leaveIntvAfter"); - DEBUG(dbgs() << " leaveIntvAfter " << Idx); + LLVM_DEBUG(dbgs() << " leaveIntvAfter " << Idx); // The interval must be live beyond the instruction at Idx. SlotIndex Boundary = Idx.getBoundaryIndex(); VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Boundary); if (!ParentVNI) { - DEBUG(dbgs() << ": not live\n"); + LLVM_DEBUG(dbgs() << ": not live\n"); return Boundary.getNextSlot(); } - DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n'); + LLVM_DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n'); MachineInstr *MI = LIS.getInstructionFromIndex(Boundary); assert(MI && "No instruction at index"); @@ -789,16 +788,16 @@ SlotIndex SplitEditor::leaveIntvAfter(SlotIndex Idx) { SlotIndex SplitEditor::leaveIntvBefore(SlotIndex Idx) { assert(OpenIdx && "openIntv not called before leaveIntvBefore"); - DEBUG(dbgs() << " leaveIntvBefore " << Idx); + LLVM_DEBUG(dbgs() << " leaveIntvBefore " << Idx); // The interval must be live into the instruction at Idx. Idx = Idx.getBaseIndex(); VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx); if (!ParentVNI) { - DEBUG(dbgs() << ": not live\n"); + LLVM_DEBUG(dbgs() << ": not live\n"); return Idx.getNextSlot(); } - DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n'); + LLVM_DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n'); MachineInstr *MI = LIS.getInstructionFromIndex(Idx); assert(MI && "No instruction at index"); @@ -809,19 +808,19 @@ SlotIndex SplitEditor::leaveIntvBefore(SlotIndex Idx) { SlotIndex SplitEditor::leaveIntvAtTop(MachineBasicBlock &MBB) { assert(OpenIdx && "openIntv not called before leaveIntvAtTop"); SlotIndex Start = LIS.getMBBStartIdx(&MBB); - DEBUG(dbgs() << " leaveIntvAtTop " << printMBBReference(MBB) << ", " - << Start); + LLVM_DEBUG(dbgs() << " leaveIntvAtTop " << printMBBReference(MBB) << ", " + << Start); VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start); if (!ParentVNI) { - DEBUG(dbgs() << ": not live\n"); + LLVM_DEBUG(dbgs() << ": not live\n"); return Start; } VNInfo *VNI = defFromParent(0, ParentVNI, Start, MBB, MBB.SkipPHIsLabelsAndDebug(MBB.begin())); RegAssign.insert(Start, VNI->def, OpenIdx); - DEBUG(dump()); + LLVM_DEBUG(dump()); return VNI->def; } @@ -836,9 +835,9 @@ void SplitEditor::overlapIntv(SlotIndex Start, SlotIndex End) { // The complement interval will be extended as needed by LRCalc.extend(). if (ParentVNI) forceRecompute(0, *ParentVNI); - DEBUG(dbgs() << " overlapIntv [" << Start << ';' << End << "):"); + LLVM_DEBUG(dbgs() << " overlapIntv [" << Start << ';' << End << "):"); RegAssign.insert(Start, End, OpenIdx); - DEBUG(dump()); + LLVM_DEBUG(dump()); } //===----------------------------------------------------------------------===// @@ -847,7 +846,7 @@ void SplitEditor::overlapIntv(SlotIndex Start, SlotIndex End) { void SplitEditor::removeBackCopies(SmallVectorImpl<VNInfo*> &Copies) { LiveInterval *LI = &LIS.getInterval(Edit->get(0)); - DEBUG(dbgs() << "Removing " << Copies.size() << " back-copies.\n"); + LLVM_DEBUG(dbgs() << "Removing " << Copies.size() << " back-copies.\n"); RegAssignMap::iterator AssignI; AssignI.setMap(RegAssign); @@ -862,7 +861,7 @@ void SplitEditor::removeBackCopies(SmallVectorImpl<VNInfo*> &Copies) { do AtBegin = MBBI == MBB->begin(); while (!AtBegin && (--MBBI)->isDebugInstr()); - DEBUG(dbgs() << "Removing " << Def << '\t' << *MI); + LLVM_DEBUG(dbgs() << "Removing " << Def << '\t' << *MI); LIS.removeVRegDefAt(*LI, Def); LIS.RemoveMachineInstrFromMaps(*MI); MI->eraseFromParent(); @@ -877,11 +876,12 @@ void SplitEditor::removeBackCopies(SmallVectorImpl<VNInfo*> &Copies) { continue; unsigned RegIdx = AssignI.value(); if (AtBegin || !MBBI->readsVirtualRegister(Edit->getReg())) { - DEBUG(dbgs() << " cannot find simple kill of RegIdx " << RegIdx << '\n'); + LLVM_DEBUG(dbgs() << " cannot find simple kill of RegIdx " << RegIdx + << '\n'); forceRecompute(RegIdx, *Edit->getParent().getVNInfoAt(Def)); } else { SlotIndex Kill = LIS.getInstructionIndex(*MBBI).getRegSlot(); - DEBUG(dbgs() << " move kill to " << Kill << '\t' << *MBBI); + LLVM_DEBUG(dbgs() << " move kill to " << Kill << '\t' << *MBBI); AssignI.setStop(Kill); } } @@ -908,15 +908,17 @@ SplitEditor::findShallowDominator(MachineBasicBlock *MBB, // MBB isn't in a loop, it doesn't get any better. All dominators have a // higher frequency by definition. if (!Loop) { - DEBUG(dbgs() << "Def in " << printMBBReference(*DefMBB) << " dominates " - << printMBBReference(*MBB) << " at depth 0\n"); + LLVM_DEBUG(dbgs() << "Def in " << printMBBReference(*DefMBB) + << " dominates " << printMBBReference(*MBB) + << " at depth 0\n"); return MBB; } // We'll never be able to exit the DefLoop. if (Loop == DefLoop) { - DEBUG(dbgs() << "Def in " << printMBBReference(*DefMBB) << " dominates " - << printMBBReference(*MBB) << " in the same loop\n"); + LLVM_DEBUG(dbgs() << "Def in " << printMBBReference(*DefMBB) + << " dominates " << printMBBReference(*MBB) + << " in the same loop\n"); return MBB; } @@ -925,8 +927,9 @@ SplitEditor::findShallowDominator(MachineBasicBlock *MBB, if (Depth < BestDepth) { BestMBB = MBB; BestDepth = Depth; - DEBUG(dbgs() << "Def in " << printMBBReference(*DefMBB) << " dominates " - << printMBBReference(*MBB) << " at depth " << Depth << '\n'); + LLVM_DEBUG(dbgs() << "Def in " << printMBBReference(*DefMBB) + << " dominates " << printMBBReference(*MBB) + << " at depth " << Depth << '\n'); } // Leave loop by going to the immediate dominator of the loop header. @@ -1032,14 +1035,14 @@ void SplitEditor::hoistCopies() { // instruction in the complement range. All other copies of ParentVNI // should be eliminated. if (VNI->def == ParentVNI->def) { - DEBUG(dbgs() << "Direct complement def at " << VNI->def << '\n'); + LLVM_DEBUG(dbgs() << "Direct complement def at " << VNI->def << '\n'); Dom = DomPair(ValMBB, VNI->def); continue; } // Skip the singly mapped values. There is nothing to gain from hoisting a // single back-copy. if (Values.lookup(std::make_pair(0, ParentVNI->id)).getPointer()) { - DEBUG(dbgs() << "Single complement def at " << VNI->def << '\n'); + LLVM_DEBUG(dbgs() << "Single complement def at " << VNI->def << '\n'); continue; } @@ -1063,10 +1066,11 @@ void SplitEditor::hoistCopies() { Costs[ParentVNI->id] += MBFI.getBlockFreq(ValMBB); } - DEBUG(dbgs() << "Multi-mapped complement " << VNI->id << '@' << VNI->def - << " for parent " << ParentVNI->id << '@' << ParentVNI->def - << " hoist to " << printMBBReference(*Dom.first) << ' ' - << Dom.second << '\n'); + LLVM_DEBUG(dbgs() << "Multi-mapped complement " << VNI->id << '@' + << VNI->def << " for parent " << ParentVNI->id << '@' + << ParentVNI->def << " hoist to " + << printMBBReference(*Dom.first) << ' ' << Dom.second + << '\n'); } // Insert the hoisted copies. @@ -1119,7 +1123,7 @@ bool SplitEditor::transferValues() { bool Skipped = false; RegAssignMap::const_iterator AssignI = RegAssign.begin(); for (const LiveRange::Segment &S : Edit->getParent()) { - DEBUG(dbgs() << " blit " << S << ':'); + LLVM_DEBUG(dbgs() << " blit " << S << ':'); VNInfo *ParentVNI = S.valno; // RegAssign has holes where RegIdx 0 should be used. SlotIndex Start = S.start; @@ -1141,14 +1145,14 @@ bool SplitEditor::transferValues() { } // The interval [Start;End) is continuously mapped to RegIdx, ParentVNI. - DEBUG(dbgs() << " [" << Start << ';' << End << ")=" << RegIdx - << '(' << printReg(Edit->get(RegIdx)) << ')'); + LLVM_DEBUG(dbgs() << " [" << Start << ';' << End << ")=" << RegIdx << '(' + << printReg(Edit->get(RegIdx)) << ')'); LiveInterval &LI = LIS.getInterval(Edit->get(RegIdx)); // Check for a simply defined value that can be blitted directly. ValueForcePair VFP = Values.lookup(std::make_pair(RegIdx, ParentVNI->id)); if (VNInfo *VNI = VFP.getPointer()) { - DEBUG(dbgs() << ':' << VNI->id); + LLVM_DEBUG(dbgs() << ':' << VNI->id); LI.addSegment(LiveInterval::Segment(Start, End, VNI)); Start = End; continue; @@ -1156,7 +1160,7 @@ bool SplitEditor::transferValues() { // Skip values with forced recomputation. if (VFP.getInt()) { - DEBUG(dbgs() << "(recalc)"); + LLVM_DEBUG(dbgs() << "(recalc)"); Skipped = true; Start = End; continue; @@ -1175,7 +1179,7 @@ bool SplitEditor::transferValues() { if (Start != BlockStart) { VNInfo *VNI = LI.extendInBlock(BlockStart, std::min(BlockEnd, End)); assert(VNI && "Missing def for complex mapped value"); - DEBUG(dbgs() << ':' << VNI->id << "*" << printMBBReference(*MBB)); + LLVM_DEBUG(dbgs() << ':' << VNI->id << "*" << printMBBReference(*MBB)); // MBB has its own def. Is it also live-out? if (BlockEnd <= End) LRC.setLiveOutValue(&*MBB, VNI); @@ -1188,7 +1192,7 @@ bool SplitEditor::transferValues() { // Handle the live-in blocks covered by [Start;End). assert(Start <= BlockStart && "Expected live-in block"); while (BlockStart < End) { - DEBUG(dbgs() << ">" << printMBBReference(*MBB)); + LLVM_DEBUG(dbgs() << ">" << printMBBReference(*MBB)); BlockEnd = LIS.getMBBEndIdx(&*MBB); if (BlockStart == ParentVNI->def) { // This block has the def of a parent PHI, so it isn't live-in. @@ -1213,7 +1217,7 @@ bool SplitEditor::transferValues() { } Start = End; } while (Start != S.end); - DEBUG(dbgs() << '\n'); + LLVM_DEBUG(dbgs() << '\n'); } LRCalc[0].calculateValues(); @@ -1315,7 +1319,7 @@ void SplitEditor::rewriteAssigned(bool ExtendRanges) { ++RI; // LiveDebugVariables should have handled all DBG_VALUE instructions. if (MI->isDebugValue()) { - DEBUG(dbgs() << "Zapping " << *MI); + LLVM_DEBUG(dbgs() << "Zapping " << *MI); MO.setReg(0); continue; } @@ -1331,8 +1335,8 @@ void SplitEditor::rewriteAssigned(bool ExtendRanges) { unsigned RegIdx = RegAssign.lookup(Idx); LiveInterval &LI = LIS.getInterval(Edit->get(RegIdx)); MO.setReg(LI.reg); - DEBUG(dbgs() << " rewr " << printMBBReference(*MI->getParent()) << '\t' - << Idx << ':' << RegIdx << '\t' << *MI); + LLVM_DEBUG(dbgs() << " rewr " << printMBBReference(*MI->getParent()) + << '\t' << Idx << ':' << RegIdx << '\t' << *MI); // Extend liveness to Idx if the instruction reads reg. if (!ExtendRanges || MO.isUndef()) @@ -1417,7 +1421,7 @@ void SplitEditor::deleteRematVictims() { if (!MI->allDefsAreDead()) continue; - DEBUG(dbgs() << "All defs dead: " << *MI); + LLVM_DEBUG(dbgs() << "All defs dead: " << *MI); Dead.push_back(MI); } } @@ -1599,9 +1603,9 @@ void SplitEditor::splitLiveThroughBlock(unsigned MBBNum, SlotIndex Start, Stop; std::tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(MBBNum); - DEBUG(dbgs() << "%bb." << MBBNum << " [" << Start << ';' << Stop << ") intf " - << LeaveBefore << '-' << EnterAfter << ", live-through " - << IntvIn << " -> " << IntvOut); + LLVM_DEBUG(dbgs() << "%bb." << MBBNum << " [" << Start << ';' << Stop + << ") intf " << LeaveBefore << '-' << EnterAfter + << ", live-through " << IntvIn << " -> " << IntvOut); assert((IntvIn || IntvOut) && "Use splitSingleBlock for isolated blocks"); @@ -1612,7 +1616,7 @@ void SplitEditor::splitLiveThroughBlock(unsigned MBBNum, MachineBasicBlock *MBB = VRM.getMachineFunction().getBlockNumbered(MBBNum); if (!IntvOut) { - DEBUG(dbgs() << ", spill on entry.\n"); + LLVM_DEBUG(dbgs() << ", spill on entry.\n"); // // <<<<<<<<< Possible LeaveBefore interference. // |-----------| Live through. @@ -1626,7 +1630,7 @@ void SplitEditor::splitLiveThroughBlock(unsigned MBBNum, } if (!IntvIn) { - DEBUG(dbgs() << ", reload on exit.\n"); + LLVM_DEBUG(dbgs() << ", reload on exit.\n"); // // >>>>>>> Possible EnterAfter interference. // |-----------| Live through. @@ -1640,7 +1644,7 @@ void SplitEditor::splitLiveThroughBlock(unsigned MBBNum, } if (IntvIn == IntvOut && !LeaveBefore && !EnterAfter) { - DEBUG(dbgs() << ", straight through.\n"); + LLVM_DEBUG(dbgs() << ", straight through.\n"); // // |-----------| Live through. // ------------- Straight through, same intv, no interference. @@ -1656,7 +1660,7 @@ void SplitEditor::splitLiveThroughBlock(unsigned MBBNum, if (IntvIn != IntvOut && (!LeaveBefore || !EnterAfter || LeaveBefore.getBaseIndex() > EnterAfter.getBoundaryIndex())) { - DEBUG(dbgs() << ", switch avoiding interference.\n"); + LLVM_DEBUG(dbgs() << ", switch avoiding interference.\n"); // // >>>> <<<< Non-overlapping EnterAfter/LeaveBefore interference. // |-----------| Live through. @@ -1677,7 +1681,7 @@ void SplitEditor::splitLiveThroughBlock(unsigned MBBNum, return; } - DEBUG(dbgs() << ", create local intv for interference.\n"); + LLVM_DEBUG(dbgs() << ", create local intv for interference.\n"); // // >>><><><><<<< Overlapping EnterAfter/LeaveBefore interference. // |-----------| Live through. @@ -1701,17 +1705,18 @@ void SplitEditor::splitRegInBlock(const SplitAnalysis::BlockInfo &BI, SlotIndex Start, Stop; std::tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB); - DEBUG(dbgs() << printMBBReference(*BI.MBB) << " [" << Start << ';' << Stop - << "), uses " << BI.FirstInstr << '-' << BI.LastInstr - << ", reg-in " << IntvIn << ", leave before " << LeaveBefore - << (BI.LiveOut ? ", stack-out" : ", killed in block")); + LLVM_DEBUG(dbgs() << printMBBReference(*BI.MBB) << " [" << Start << ';' + << Stop << "), uses " << BI.FirstInstr << '-' + << BI.LastInstr << ", reg-in " << IntvIn + << ", leave before " << LeaveBefore + << (BI.LiveOut ? ", stack-out" : ", killed in block")); assert(IntvIn && "Must have register in"); assert(BI.LiveIn && "Must be live-in"); assert((!LeaveBefore || LeaveBefore > Start) && "Bad interference"); if (!BI.LiveOut && (!LeaveBefore || LeaveBefore >= BI.LastInstr)) { - DEBUG(dbgs() << " before interference.\n"); + LLVM_DEBUG(dbgs() << " before interference.\n"); // // <<< Interference after kill. // |---o---x | Killed in block. @@ -1736,13 +1741,13 @@ void SplitEditor::splitRegInBlock(const SplitAnalysis::BlockInfo &BI, // \_____ Stack interval is live-out. // if (BI.LastInstr < LSP) { - DEBUG(dbgs() << ", spill after last use before interference.\n"); + LLVM_DEBUG(dbgs() << ", spill after last use before interference.\n"); selectIntv(IntvIn); SlotIndex Idx = leaveIntvAfter(BI.LastInstr); useIntv(Start, Idx); assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference"); } else { - DEBUG(dbgs() << ", spill before last split point.\n"); + LLVM_DEBUG(dbgs() << ", spill before last split point.\n"); selectIntv(IntvIn); SlotIndex Idx = leaveIntvBefore(LSP); overlapIntv(Idx, BI.LastInstr); @@ -1757,7 +1762,7 @@ void SplitEditor::splitRegInBlock(const SplitAnalysis::BlockInfo &BI, // different register. unsigned LocalIntv = openIntv(); (void)LocalIntv; - DEBUG(dbgs() << ", creating local interval " << LocalIntv << ".\n"); + LLVM_DEBUG(dbgs() << ", creating local interval " << LocalIntv << ".\n"); if (!BI.LiveOut || BI.LastInstr < LSP) { // @@ -1793,10 +1798,11 @@ void SplitEditor::splitRegOutBlock(const SplitAnalysis::BlockInfo &BI, SlotIndex Start, Stop; std::tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB); - DEBUG(dbgs() << printMBBReference(*BI.MBB) << " [" << Start << ';' << Stop - << "), uses " << BI.FirstInstr << '-' << BI.LastInstr - << ", reg-out " << IntvOut << ", enter after " << EnterAfter - << (BI.LiveIn ? ", stack-in" : ", defined in block")); + LLVM_DEBUG(dbgs() << printMBBReference(*BI.MBB) << " [" << Start << ';' + << Stop << "), uses " << BI.FirstInstr << '-' + << BI.LastInstr << ", reg-out " << IntvOut + << ", enter after " << EnterAfter + << (BI.LiveIn ? ", stack-in" : ", defined in block")); SlotIndex LSP = SA.getLastSplitPoint(BI.MBB->getNumber()); @@ -1805,7 +1811,7 @@ void SplitEditor::splitRegOutBlock(const SplitAnalysis::BlockInfo &BI, assert((!EnterAfter || EnterAfter < LSP) && "Bad interference"); if (!BI.LiveIn && (!EnterAfter || EnterAfter <= BI.FirstInstr)) { - DEBUG(dbgs() << " after interference.\n"); + LLVM_DEBUG(dbgs() << " after interference.\n"); // // >>>> Interference before def. // | o---o---| Defined in block. @@ -1817,7 +1823,7 @@ void SplitEditor::splitRegOutBlock(const SplitAnalysis::BlockInfo &BI, } if (!EnterAfter || EnterAfter < BI.FirstInstr.getBaseIndex()) { - DEBUG(dbgs() << ", reload after interference.\n"); + LLVM_DEBUG(dbgs() << ", reload after interference.\n"); // // >>>> Interference before def. // |---o---o---| Live-through, stack-in. @@ -1833,7 +1839,7 @@ void SplitEditor::splitRegOutBlock(const SplitAnalysis::BlockInfo &BI, // The interference is overlapping somewhere we wanted to use IntvOut. That // means we need to create a local interval that can be allocated a // different register. - DEBUG(dbgs() << ", interference overlaps uses.\n"); + LLVM_DEBUG(dbgs() << ", interference overlaps uses.\n"); // // >>>>>>> Interference overlapping uses. // |---o---o---| Live-through, stack-in. diff --git a/llvm/lib/CodeGen/StackColoring.cpp b/llvm/lib/CodeGen/StackColoring.cpp index e9eb6005827..4f3d1f704aa 100644 --- a/llvm/lib/CodeGen/StackColoring.cpp +++ b/llvm/lib/CodeGen/StackColoring.cpp @@ -673,13 +673,13 @@ unsigned StackColoring::collectMarkers(unsigned NumSlot) { } const AllocaInst *Allocation = MFI->getObjectAllocation(Slot); if (Allocation) { - DEBUG(dbgs() << "Found a lifetime "); - DEBUG(dbgs() << (MI.getOpcode() == TargetOpcode::LIFETIME_START - ? "start" - : "end")); - DEBUG(dbgs() << " marker for slot #" << Slot); - DEBUG(dbgs() << " with allocation: " << Allocation->getName() - << "\n"); + LLVM_DEBUG(dbgs() << "Found a lifetime "); + LLVM_DEBUG(dbgs() << (MI.getOpcode() == TargetOpcode::LIFETIME_START + ? "start" + : "end")); + LLVM_DEBUG(dbgs() << " marker for slot #" << Slot); + LLVM_DEBUG(dbgs() + << " with allocation: " << Allocation->getName() << "\n"); } Markers.push_back(&MI); MarkersFound += 1; @@ -708,7 +708,7 @@ unsigned StackColoring::collectMarkers(unsigned NumSlot) { for (unsigned slot = 0; slot < NumSlot; ++slot) if (NumStartLifetimes[slot] > 1 || NumEndLifetimes[slot] > 1) ConservativeSlots.set(slot); - DEBUG(dumpBV("Conservative slots", ConservativeSlots)); + LLVM_DEBUG(dumpBV("Conservative slots", ConservativeSlots)); // Step 2: compute begin/end sets for each block @@ -739,14 +739,16 @@ unsigned StackColoring::collectMarkers(unsigned NumSlot) { BlockInfo.End.set(Slot); } else { for (auto Slot : slots) { - DEBUG(dbgs() << "Found a use of slot #" << Slot); - DEBUG(dbgs() << " at " << printMBBReference(*MBB) << " index "); - DEBUG(Indexes->getInstructionIndex(MI).print(dbgs())); + LLVM_DEBUG(dbgs() << "Found a use of slot #" << Slot); + LLVM_DEBUG(dbgs() + << " at " << printMBBReference(*MBB) << " index "); + LLVM_DEBUG(Indexes->getInstructionIndex(MI).print(dbgs())); const AllocaInst *Allocation = MFI->getObjectAllocation(Slot); if (Allocation) { - DEBUG(dbgs() << " with allocation: "<< Allocation->getName()); + LLVM_DEBUG(dbgs() + << " with allocation: " << Allocation->getName()); } - DEBUG(dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "\n"); if (BlockInfo.End.test(Slot)) { BlockInfo.End.reset(Slot); } @@ -881,7 +883,7 @@ bool StackColoring::removeAllMarkers() { } Markers.clear(); - DEBUG(dbgs()<<"Removed "<<Count<<" markers.\n"); + LLVM_DEBUG(dbgs() << "Removed " << Count << " markers.\n"); return Count; } @@ -895,8 +897,8 @@ void StackColoring::remapInstructions(DenseMap<int, int> &SlotRemap) { if (!VI.Var) continue; if (SlotRemap.count(VI.Slot)) { - DEBUG(dbgs() << "Remapping debug info for [" - << cast<DILocalVariable>(VI.Var)->getName() << "].\n"); + LLVM_DEBUG(dbgs() << "Remapping debug info for [" + << cast<DILocalVariable>(VI.Var)->getName() << "].\n"); VI.Slot = SlotRemap[VI.Slot]; FixedDbg++; } @@ -1065,9 +1067,9 @@ void StackColoring::remapInstructions(DenseMap<int, int> &SlotRemap) { SlotRemap.count(H.CatchObj.FrameIndex)) H.CatchObj.FrameIndex = SlotRemap[H.CatchObj.FrameIndex]; - DEBUG(dbgs()<<"Fixed "<<FixedMemOp<<" machine memory operands.\n"); - DEBUG(dbgs()<<"Fixed "<<FixedDbg<<" debug locations.\n"); - DEBUG(dbgs()<<"Fixed "<<FixedInstr<<" machine instructions.\n"); + LLVM_DEBUG(dbgs() << "Fixed " << FixedMemOp << " machine memory operands.\n"); + LLVM_DEBUG(dbgs() << "Fixed " << FixedDbg << " debug locations.\n"); + LLVM_DEBUG(dbgs() << "Fixed " << FixedInstr << " machine instructions.\n"); } void StackColoring::removeInvalidSlotRanges() { @@ -1105,7 +1107,7 @@ void StackColoring::removeInvalidSlotRanges() { SlotIndex Index = Indexes->getInstructionIndex(I); if (Interval->find(Index) == Interval->end()) { Interval->clear(); - DEBUG(dbgs()<<"Invalidating range #"<<Slot<<"\n"); + LLVM_DEBUG(dbgs() << "Invalidating range #" << Slot << "\n"); EscapedAllocas++; } } @@ -1129,8 +1131,8 @@ void StackColoring::expungeSlotMap(DenseMap<int, int> &SlotRemap, } bool StackColoring::runOnMachineFunction(MachineFunction &Func) { - DEBUG(dbgs() << "********** Stack Coloring **********\n" - << "********** Function: " << Func.getName() << '\n'); + LLVM_DEBUG(dbgs() << "********** Stack Coloring **********\n" + << "********** Function: " << Func.getName() << '\n'); MF = &Func; MFI = &MF->getFrameInfo(); Indexes = &getAnalysis<SlotIndexes>(); @@ -1157,21 +1159,23 @@ bool StackColoring::runOnMachineFunction(MachineFunction &Func) { unsigned NumMarkers = collectMarkers(NumSlots); unsigned TotalSize = 0; - DEBUG(dbgs()<<"Found "<<NumMarkers<<" markers and "<<NumSlots<<" slots\n"); - DEBUG(dbgs()<<"Slot structure:\n"); + LLVM_DEBUG(dbgs() << "Found " << NumMarkers << " markers and " << NumSlots + << " slots\n"); + LLVM_DEBUG(dbgs() << "Slot structure:\n"); for (int i=0; i < MFI->getObjectIndexEnd(); ++i) { - DEBUG(dbgs()<<"Slot #"<<i<<" - "<<MFI->getObjectSize(i)<<" bytes.\n"); + LLVM_DEBUG(dbgs() << "Slot #" << i << " - " << MFI->getObjectSize(i) + << " bytes.\n"); TotalSize += MFI->getObjectSize(i); } - DEBUG(dbgs()<<"Total Stack size: "<<TotalSize<<" bytes\n\n"); + LLVM_DEBUG(dbgs() << "Total Stack size: " << TotalSize << " bytes\n\n"); // Don't continue because there are not enough lifetime markers, or the // stack is too small, or we are told not to optimize the slots. if (NumMarkers < 2 || TotalSize < 16 || DisableColoring || skipFunction(Func.getFunction())) { - DEBUG(dbgs()<<"Will not try to merge slots.\n"); + LLVM_DEBUG(dbgs() << "Will not try to merge slots.\n"); return removeAllMarkers(); } @@ -1184,12 +1188,12 @@ bool StackColoring::runOnMachineFunction(MachineFunction &Func) { // Calculate the liveness of each block. calculateLocalLiveness(); - DEBUG(dbgs() << "Dataflow iterations: " << NumIterations << "\n"); - DEBUG(dump()); + LLVM_DEBUG(dbgs() << "Dataflow iterations: " << NumIterations << "\n"); + LLVM_DEBUG(dump()); // Propagate the liveness information. calculateLiveIntervals(NumSlots); - DEBUG(dumpIntervals()); + LLVM_DEBUG(dumpIntervals()); // Search for allocas which are used outside of the declared lifetime // markers. @@ -1260,8 +1264,8 @@ bool StackColoring::runOnMachineFunction(MachineFunction &Func) { SlotRemap[SecondSlot] = FirstSlot; SortedSlots[J] = -1; - DEBUG(dbgs()<<"Merging #"<<FirstSlot<<" and slots #"<< - SecondSlot<<" together.\n"); + LLVM_DEBUG(dbgs() << "Merging #" << FirstSlot << " and slots #" + << SecondSlot << " together.\n"); unsigned MaxAlignment = std::max(MFI->getObjectAlignment(FirstSlot), MFI->getObjectAlignment(SecondSlot)); @@ -1281,8 +1285,8 @@ bool StackColoring::runOnMachineFunction(MachineFunction &Func) { // Record statistics. StackSpaceSaved += ReducedSize; StackSlotMerged += RemovedSlots; - DEBUG(dbgs()<<"Merge "<<RemovedSlots<<" slots. Saved "<< - ReducedSize<<" bytes\n"); + LLVM_DEBUG(dbgs() << "Merge " << RemovedSlots << " slots. Saved " + << ReducedSize << " bytes\n"); // Scan the entire function and update all machine operands that use frame // indices to use the remapped frame index. diff --git a/llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp b/llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp index 32d6f54f679..fc2895a03f6 100644 --- a/llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp +++ b/llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp @@ -106,8 +106,8 @@ bool StackMapLiveness::runOnMachineFunction(MachineFunction &MF) { if (!EnablePatchPointLiveness) return false; - DEBUG(dbgs() << "********** COMPUTING STACKMAP LIVENESS: " << MF.getName() - << " **********\n"); + LLVM_DEBUG(dbgs() << "********** COMPUTING STACKMAP LIVENESS: " + << MF.getName() << " **********\n"); TRI = MF.getSubtarget().getRegisterInfo(); ++NumStackMapFuncVisited; @@ -124,7 +124,7 @@ bool StackMapLiveness::calculateLiveness(MachineFunction &MF) { bool HasChanged = false; // For all basic blocks in the function. for (auto &MBB : MF) { - DEBUG(dbgs() << "****** BB " << MBB.getName() << " ******\n"); + LLVM_DEBUG(dbgs() << "****** BB " << MBB.getName() << " ******\n"); LiveRegs.init(*TRI); // FIXME: This should probably be addLiveOuts(). LiveRegs.addLiveOutsNoPristines(MBB); @@ -138,7 +138,7 @@ bool StackMapLiveness::calculateLiveness(MachineFunction &MF) { HasStackMap = true; ++NumStackMaps; } - DEBUG(dbgs() << " " << LiveRegs << " " << *I); + LLVM_DEBUG(dbgs() << " " << LiveRegs << " " << *I); LiveRegs.stepBackward(*I); } ++NumBBsVisited; diff --git a/llvm/lib/CodeGen/StackMaps.cpp b/llvm/lib/CodeGen/StackMaps.cpp index 873190cfe7a..19a191c01db 100644 --- a/llvm/lib/CodeGen/StackMaps.cpp +++ b/llvm/lib/CodeGen/StackMaps.cpp @@ -420,13 +420,13 @@ void StackMaps::emitStackmapHeader(MCStreamer &OS) { OS.EmitIntValue(0, 2); // Reserved. // Num functions. - DEBUG(dbgs() << WSMP << "#functions = " << FnInfos.size() << '\n'); + LLVM_DEBUG(dbgs() << WSMP << "#functions = " << FnInfos.size() << '\n'); OS.EmitIntValue(FnInfos.size(), 4); // Num constants. - DEBUG(dbgs() << WSMP << "#constants = " << ConstPool.size() << '\n'); + LLVM_DEBUG(dbgs() << WSMP << "#constants = " << ConstPool.size() << '\n'); OS.EmitIntValue(ConstPool.size(), 4); // Num callsites. - DEBUG(dbgs() << WSMP << "#callsites = " << CSInfos.size() << '\n'); + LLVM_DEBUG(dbgs() << WSMP << "#callsites = " << CSInfos.size() << '\n'); OS.EmitIntValue(CSInfos.size(), 4); } @@ -439,11 +439,11 @@ void StackMaps::emitStackmapHeader(MCStreamer &OS) { /// } void StackMaps::emitFunctionFrameRecords(MCStreamer &OS) { // Function Frame records. - DEBUG(dbgs() << WSMP << "functions:\n"); + LLVM_DEBUG(dbgs() << WSMP << "functions:\n"); for (auto const &FR : FnInfos) { - DEBUG(dbgs() << WSMP << "function addr: " << FR.first - << " frame size: " << FR.second.StackSize - << " callsite count: " << FR.second.RecordCount << '\n'); + LLVM_DEBUG(dbgs() << WSMP << "function addr: " << FR.first + << " frame size: " << FR.second.StackSize + << " callsite count: " << FR.second.RecordCount << '\n'); OS.EmitSymbolValue(FR.first, 8); OS.EmitIntValue(FR.second.StackSize, 8); OS.EmitIntValue(FR.second.RecordCount, 8); @@ -455,9 +455,9 @@ void StackMaps::emitFunctionFrameRecords(MCStreamer &OS) { /// int64 : Constants[NumConstants] void StackMaps::emitConstantPoolEntries(MCStreamer &OS) { // Constant pool entries. - DEBUG(dbgs() << WSMP << "constants:\n"); + LLVM_DEBUG(dbgs() << WSMP << "constants:\n"); for (const auto &ConstEntry : ConstPool) { - DEBUG(dbgs() << WSMP << ConstEntry.second << '\n'); + LLVM_DEBUG(dbgs() << WSMP << ConstEntry.second << '\n'); OS.EmitIntValue(ConstEntry.second, 8); } } @@ -492,7 +492,7 @@ void StackMaps::emitConstantPoolEntries(MCStreamer &OS) { /// 0x4, Constant, Offset (small constant) /// 0x5, ConstIndex, Constants[Offset] (large constant) void StackMaps::emitCallsiteEntries(MCStreamer &OS) { - DEBUG(print(dbgs())); + LLVM_DEBUG(print(dbgs())); // Callsite entries. for (const auto &CSI : CSInfos) { const LocationVec &CSLocs = CSI.Locations; @@ -569,7 +569,7 @@ void StackMaps::serializeToStackMapSection() { OS.EmitLabel(OutContext.getOrCreateSymbol(Twine("__LLVM_StackMaps"))); // Serialize data. - DEBUG(dbgs() << "********** Stack Map Output **********\n"); + LLVM_DEBUG(dbgs() << "********** Stack Map Output **********\n"); emitStackmapHeader(OS); emitFunctionFrameRecords(OS); emitConstantPoolEntries(OS); diff --git a/llvm/lib/CodeGen/StackSlotColoring.cpp b/llvm/lib/CodeGen/StackSlotColoring.cpp index cd13b3f7969..b3ffebca613 100644 --- a/llvm/lib/CodeGen/StackSlotColoring.cpp +++ b/llvm/lib/CodeGen/StackSlotColoring.cpp @@ -213,10 +213,10 @@ void StackSlotColoring::InitializeSlots() { [](Pair *LHS, Pair *RHS) { return LHS->first < RHS->first; }); // Gather all spill slots into a list. - DEBUG(dbgs() << "Spill slot intervals:\n"); + LLVM_DEBUG(dbgs() << "Spill slot intervals:\n"); for (auto *I : Intervals) { LiveInterval &li = I->second; - DEBUG(li.dump()); + LLVM_DEBUG(li.dump()); int FI = TargetRegisterInfo::stackSlot2Index(li.reg); if (MFI->isDeadObjectIndex(FI)) continue; @@ -225,7 +225,7 @@ void StackSlotColoring::InitializeSlots() { OrigSizes[FI] = MFI->getObjectSize(FI); AllColors.set(FI); } - DEBUG(dbgs() << '\n'); + LLVM_DEBUG(dbgs() << '\n'); // Sort them by weight. std::stable_sort(SSIntervals.begin(), SSIntervals.end(), IntervalSorter()); @@ -267,7 +267,7 @@ int StackSlotColoring::ColorSlot(LiveInterval *li) { } if (Color != -1 && MFI->getStackID(Color) != MFI->getStackID(FI)) { - DEBUG(dbgs() << "cannot share FIs with different stack IDs\n"); + LLVM_DEBUG(dbgs() << "cannot share FIs with different stack IDs\n"); Share = false; } @@ -282,7 +282,7 @@ int StackSlotColoring::ColorSlot(LiveInterval *li) { // Record the assignment. Assignments[Color].push_back(li); - DEBUG(dbgs() << "Assigning fi#" << FI << " to fi#" << Color << "\n"); + LLVM_DEBUG(dbgs() << "Assigning fi#" << FI << " to fi#" << Color << "\n"); // Change size and alignment of the allocated slot. If there are multiple // objects sharing the same slot, then make sure the size and alignment @@ -305,7 +305,7 @@ bool StackSlotColoring::ColorSlots(MachineFunction &MF) { SmallVector<SmallVector<int, 4>, 16> RevMap(NumObjs); BitVector UsedColors(NumObjs); - DEBUG(dbgs() << "Color spill slot intervals:\n"); + LLVM_DEBUG(dbgs() << "Color spill slot intervals:\n"); bool Changed = false; for (unsigned i = 0, e = SSIntervals.size(); i != e; ++i) { LiveInterval *li = SSIntervals[i]; @@ -319,7 +319,7 @@ bool StackSlotColoring::ColorSlots(MachineFunction &MF) { Changed |= (SS != NewSS); } - DEBUG(dbgs() << "\nSpill slots after coloring:\n"); + LLVM_DEBUG(dbgs() << "\nSpill slots after coloring:\n"); for (unsigned i = 0, e = SSIntervals.size(); i != e; ++i) { LiveInterval *li = SSIntervals[i]; int SS = TargetRegisterInfo::stackSlot2Index(li->reg); @@ -330,8 +330,8 @@ bool StackSlotColoring::ColorSlots(MachineFunction &MF) { #ifndef NDEBUG for (unsigned i = 0, e = SSIntervals.size(); i != e; ++i) - DEBUG(SSIntervals[i]->dump()); - DEBUG(dbgs() << '\n'); + LLVM_DEBUG(SSIntervals[i]->dump()); + LLVM_DEBUG(dbgs() << '\n'); #endif if (!Changed) @@ -358,7 +358,8 @@ bool StackSlotColoring::ColorSlots(MachineFunction &MF) { // Delete unused stack slots. while (NextColor != -1) { - DEBUG(dbgs() << "Removing unused stack object fi#" << NextColor << "\n"); + LLVM_DEBUG(dbgs() << "Removing unused stack object fi#" << NextColor + << "\n"); MFI->RemoveStackObject(NextColor); NextColor = AllColors.find_next(NextColor); } @@ -454,10 +455,10 @@ bool StackSlotColoring::RemoveDeadStores(MachineBasicBlock* MBB) { } bool StackSlotColoring::runOnMachineFunction(MachineFunction &MF) { - DEBUG({ - dbgs() << "********** Stack Slot Coloring **********\n" - << "********** Function: " << MF.getName() << '\n'; - }); + LLVM_DEBUG({ + dbgs() << "********** Stack Slot Coloring **********\n" + << "********** Function: " << MF.getName() << '\n'; + }); if (skipFunction(MF.getFunction())) return false; diff --git a/llvm/lib/CodeGen/TailDuplicator.cpp b/llvm/lib/CodeGen/TailDuplicator.cpp index b4ee8777d1f..b118c176a89 100644 --- a/llvm/lib/CodeGen/TailDuplicator.cpp +++ b/llvm/lib/CodeGen/TailDuplicator.cpp @@ -262,7 +262,7 @@ bool TailDuplicator::tailDuplicateBlocks() { bool MadeChange = false; if (PreRegAlloc && TailDupVerify) { - DEBUG(dbgs() << "\n*** Before tail-duplicating\n"); + LLVM_DEBUG(dbgs() << "\n*** Before tail-duplicating\n"); VerifyPHIs(*MF, true); } @@ -718,8 +718,8 @@ bool TailDuplicator::duplicateSimpleBB( continue; Changed = true; - DEBUG(dbgs() << "\nTail-duplicating into PredBB: " << *PredBB - << "From simple Succ: " << *TailBB); + LLVM_DEBUG(dbgs() << "\nTail-duplicating into PredBB: " << *PredBB + << "From simple Succ: " << *TailBB); MachineBasicBlock *NewTarget = *TailBB->succ_begin(); MachineBasicBlock *NextBB = PredBB->getNextNode(); @@ -799,8 +799,8 @@ bool TailDuplicator::tailDuplicate(bool IsSimple, MachineBasicBlock *TailBB, MachineBasicBlock *ForcedLayoutPred, SmallVectorImpl<MachineBasicBlock *> &TDBBs, SmallVectorImpl<MachineInstr *> &Copies) { - DEBUG(dbgs() << "\n*** Tail-duplicating " << printMBBReference(*TailBB) - << '\n'); + LLVM_DEBUG(dbgs() << "\n*** Tail-duplicating " << printMBBReference(*TailBB) + << '\n'); DenseSet<unsigned> UsedByPhi; getRegsUsedByPHIs(*TailBB, &UsedByPhi); @@ -830,8 +830,8 @@ bool TailDuplicator::tailDuplicate(bool IsSimple, MachineBasicBlock *TailBB, if (IsLayoutSuccessor) continue; - DEBUG(dbgs() << "\nTail-duplicating into PredBB: " << *PredBB - << "From Succ: " << *TailBB); + LLVM_DEBUG(dbgs() << "\nTail-duplicating into PredBB: " << *PredBB + << "From Succ: " << *TailBB); TDBBs.push_back(PredBB); @@ -893,8 +893,8 @@ bool TailDuplicator::tailDuplicate(bool IsSimple, MachineBasicBlock *TailBB, (!PriorTBB || PriorTBB == TailBB) && TailBB->pred_size() == 1 && !TailBB->hasAddressTaken()) { - DEBUG(dbgs() << "\nMerging into block: " << *PrevBB - << "From MBB: " << *TailBB); + LLVM_DEBUG(dbgs() << "\nMerging into block: " << *PrevBB + << "From MBB: " << *TailBB); // There may be a branch to the layout successor. This is unlikely but it // happens. The correct thing to do is to remove the branch before // duplicating the instructions in all cases. @@ -999,7 +999,7 @@ void TailDuplicator::removeDeadBlock( MachineBasicBlock *MBB, function_ref<void(MachineBasicBlock *)> *RemovalCallback) { assert(MBB->pred_empty() && "MBB must be dead!"); - DEBUG(dbgs() << "\nRemoving MBB: " << *MBB); + LLVM_DEBUG(dbgs() << "\nRemoving MBB: " << *MBB); if (RemovalCallback) (*RemovalCallback)(MBB); diff --git a/llvm/lib/CodeGen/TargetRegisterInfo.cpp b/llvm/lib/CodeGen/TargetRegisterInfo.cpp index 80622ea7bae..661dc18f7a8 100644 --- a/llvm/lib/CodeGen/TargetRegisterInfo.cpp +++ b/llvm/lib/CodeGen/TargetRegisterInfo.cpp @@ -443,7 +443,8 @@ bool TargetRegisterInfo::needsStackRealignment( if (F.hasFnAttribute("stackrealign") || requiresRealignment) { if (canRealignStack(MF)) return true; - DEBUG(dbgs() << "Can't realign function's stack: " << F.getName() << "\n"); + LLVM_DEBUG(dbgs() << "Can't realign function's stack: " << F.getName() + << "\n"); } return false; } diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp index da55c18854a..0ca435016ea 100644 --- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp +++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp @@ -685,15 +685,15 @@ bool TwoAddressInstructionPass::commuteInstruction(MachineInstr *MI, unsigned RegCIdx, unsigned Dist) { unsigned RegC = MI->getOperand(RegCIdx).getReg(); - DEBUG(dbgs() << "2addr: COMMUTING : " << *MI); + LLVM_DEBUG(dbgs() << "2addr: COMMUTING : " << *MI); MachineInstr *NewMI = TII->commuteInstruction(*MI, false, RegBIdx, RegCIdx); if (NewMI == nullptr) { - DEBUG(dbgs() << "2addr: COMMUTING FAILED!\n"); + LLVM_DEBUG(dbgs() << "2addr: COMMUTING FAILED!\n"); return false; } - DEBUG(dbgs() << "2addr: COMMUTED TO: " << *NewMI); + LLVM_DEBUG(dbgs() << "2addr: COMMUTED TO: " << *NewMI); assert(NewMI == MI && "TargetInstrInfo::commuteInstruction() should not return a new " "instruction unless it was requested."); @@ -740,8 +740,8 @@ TwoAddressInstructionPass::convertInstTo3Addr(MachineBasicBlock::iterator &mi, if (!NewMI) return false; - DEBUG(dbgs() << "2addr: CONVERTING 2-ADDR: " << *mi); - DEBUG(dbgs() << "2addr: TO 3-ADDR: " << *NewMI); + LLVM_DEBUG(dbgs() << "2addr: CONVERTING 2-ADDR: " << *mi); + LLVM_DEBUG(dbgs() << "2addr: TO 3-ADDR: " << *NewMI); bool Sunk = false; if (LIS) @@ -1014,7 +1014,7 @@ rescheduleMIBelowKill(MachineBasicBlock::iterator &mi, LV->addVirtualRegisterKilled(Reg, *MI); } - DEBUG(dbgs() << "\trescheduled below kill: " << *KillMI); + LLVM_DEBUG(dbgs() << "\trescheduled below kill: " << *KillMI); return true; } @@ -1181,7 +1181,7 @@ rescheduleKillAboveMI(MachineBasicBlock::iterator &mi, LV->addVirtualRegisterKilled(Reg, *MI); } - DEBUG(dbgs() << "\trescheduled kill: " << *KillMI); + LLVM_DEBUG(dbgs() << "\trescheduled kill: " << *KillMI); return true; } @@ -1352,7 +1352,7 @@ tryInstructionTransform(MachineBasicBlock::iterator &mi, const MCInstrDesc &UnfoldMCID = TII->get(NewOpc); if (UnfoldMCID.getNumDefs() == 1) { // Unfold the load. - DEBUG(dbgs() << "2addr: UNFOLDING: " << MI); + LLVM_DEBUG(dbgs() << "2addr: UNFOLDING: " << MI); const TargetRegisterClass *RC = TRI->getAllocatableClass( TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI, *MF)); @@ -1361,7 +1361,7 @@ tryInstructionTransform(MachineBasicBlock::iterator &mi, if (!TII->unfoldMemoryOperand(*MF, MI, Reg, /*UnfoldLoad=*/true, /*UnfoldStore=*/false, NewMIs)) { - DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n"); + LLVM_DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n"); return false; } assert(NewMIs.size() == 2 && @@ -1374,8 +1374,8 @@ tryInstructionTransform(MachineBasicBlock::iterator &mi, MBB->insert(mi, NewMIs[0]); MBB->insert(mi, NewMIs[1]); - DEBUG(dbgs() << "2addr: NEW LOAD: " << *NewMIs[0] - << "2addr: NEW INST: " << *NewMIs[1]); + LLVM_DEBUG(dbgs() << "2addr: NEW LOAD: " << *NewMIs[0] + << "2addr: NEW INST: " << *NewMIs[1]); // Transform the instruction, now that it no longer has a load. unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA); @@ -1440,7 +1440,7 @@ tryInstructionTransform(MachineBasicBlock::iterator &mi, // Transforming didn't eliminate the tie and didn't lead to an // improvement. Clean up the unfolded instructions and keep the // original. - DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n"); + LLVM_DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n"); NewMIs[0]->eraseFromParent(); NewMIs[1]->eraseFromParent(); } @@ -1484,7 +1484,7 @@ collectTiedOperands(MachineInstr *MI, TiedOperandMap &TiedOperands) { MRI->constrainRegClass(DstReg, RC); SrcMO.setReg(DstReg); SrcMO.setSubReg(0); - DEBUG(dbgs() << "\t\trewrite undef:\t" << *MI); + LLVM_DEBUG(dbgs() << "\t\trewrite undef:\t" << *MI); continue; } TiedOperands[SrcReg].push_back(std::make_pair(SrcIdx, DstIdx)); @@ -1583,7 +1583,7 @@ TwoAddressInstructionPass::processTiedPairs(MachineInstr *MI, } } - DEBUG(dbgs() << "\t\tprepend:\t" << *MIB); + LLVM_DEBUG(dbgs() << "\t\tprepend:\t" << *MIB); MachineOperand &MO = MI->getOperand(SrcIdx); assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() && @@ -1677,9 +1677,8 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) { bool MadeChange = false; - DEBUG(dbgs() << "********** REWRITING TWO-ADDR INSTRS **********\n"); - DEBUG(dbgs() << "********** Function: " - << MF->getName() << '\n'); + LLVM_DEBUG(dbgs() << "********** REWRITING TWO-ADDR INSTRS **********\n"); + LLVM_DEBUG(dbgs() << "********** Function: " << MF->getName() << '\n'); // This pass takes the function out of SSA form. MRI->leaveSSA(); @@ -1722,7 +1721,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) { ++NumTwoAddressInstrs; MadeChange = true; - DEBUG(dbgs() << '\t' << *mi); + LLVM_DEBUG(dbgs() << '\t' << *mi); // If the instruction has a single pair of tied operands, try some // transformations that may either eliminate the tied operands or @@ -1749,7 +1748,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) { // Now iterate over the information collected above. for (auto &TO : TiedOperands) { processTiedPairs(&*mi, TO.second, Dist); - DEBUG(dbgs() << "\t\trewrite to:\t" << *mi); + LLVM_DEBUG(dbgs() << "\t\trewrite to:\t" << *mi); } // Rewrite INSERT_SUBREG as COPY now that we no longer need SSA form. @@ -1763,7 +1762,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) { mi->getOperand(0).setIsUndef(mi->getOperand(1).isUndef()); mi->RemoveOperand(1); mi->setDesc(TII->get(TargetOpcode::COPY)); - DEBUG(dbgs() << "\t\tconvert to:\t" << *mi); + LLVM_DEBUG(dbgs() << "\t\tconvert to:\t" << *mi); } // Clear TiedOperands here instead of at the top of the loop @@ -1796,7 +1795,7 @@ eliminateRegSequence(MachineBasicBlock::iterator &MBBI) { if (MI.getOperand(0).getSubReg() || TargetRegisterInfo::isPhysicalRegister(DstReg) || !(MI.getNumOperands() & 1)) { - DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << MI); + LLVM_DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << MI); llvm_unreachable(nullptr); } @@ -1847,19 +1846,19 @@ eliminateRegSequence(MachineBasicBlock::iterator &MBBI) { if (LV && isKill && !TargetRegisterInfo::isPhysicalRegister(SrcReg)) LV->replaceKillInstruction(SrcReg, MI, *CopyMI); - DEBUG(dbgs() << "Inserted: " << *CopyMI); + LLVM_DEBUG(dbgs() << "Inserted: " << *CopyMI); } MachineBasicBlock::iterator EndMBBI = std::next(MachineBasicBlock::iterator(MI)); if (!DefEmitted) { - DEBUG(dbgs() << "Turned: " << MI << " into an IMPLICIT_DEF"); + LLVM_DEBUG(dbgs() << "Turned: " << MI << " into an IMPLICIT_DEF"); MI.setDesc(TII->get(TargetOpcode::IMPLICIT_DEF)); for (int j = MI.getNumOperands() - 1, ee = 0; j > ee; --j) MI.RemoveOperand(j); } else { - DEBUG(dbgs() << "Eliminated: " << MI); + LLVM_DEBUG(dbgs() << "Eliminated: " << MI); MI.eraseFromParent(); } diff --git a/llvm/lib/CodeGen/VirtRegMap.cpp b/llvm/lib/CodeGen/VirtRegMap.cpp index ccec691fc07..3f9dcd4edce 100644 --- a/llvm/lib/CodeGen/VirtRegMap.cpp +++ b/llvm/lib/CodeGen/VirtRegMap.cpp @@ -242,10 +242,9 @@ bool VirtRegRewriter::runOnMachineFunction(MachineFunction &fn) { Indexes = &getAnalysis<SlotIndexes>(); LIS = &getAnalysis<LiveIntervals>(); VRM = &getAnalysis<VirtRegMap>(); - DEBUG(dbgs() << "********** REWRITE VIRTUAL REGISTERS **********\n" - << "********** Function: " - << MF->getName() << '\n'); - DEBUG(VRM->dump()); + LLVM_DEBUG(dbgs() << "********** REWRITE VIRTUAL REGISTERS **********\n" + << "********** Function: " << MF->getName() << '\n'); + LLVM_DEBUG(VRM->dump()); // Add kill flags while we still have virtual registers. LIS->addKillFlags(VRM); @@ -377,7 +376,7 @@ bool VirtRegRewriter::readsUndefSubreg(const MachineOperand &MO) const { void VirtRegRewriter::handleIdentityCopy(MachineInstr &MI) const { if (!MI.isIdentityCopy()) return; - DEBUG(dbgs() << "Identity copy: " << MI); + LLVM_DEBUG(dbgs() << "Identity copy: " << MI); ++NumIdCopies; // Copies like: @@ -388,14 +387,14 @@ void VirtRegRewriter::handleIdentityCopy(MachineInstr &MI) const { // instruction to maintain this information. if (MI.getOperand(0).isUndef() || MI.getNumOperands() > 2) { MI.setDesc(TII->get(TargetOpcode::KILL)); - DEBUG(dbgs() << " replace by: " << MI); + LLVM_DEBUG(dbgs() << " replace by: " << MI); return; } if (Indexes) Indexes->removeSingleMachineInstrFromMaps(MI); MI.eraseFromBundle(); - DEBUG(dbgs() << " deleted.\n"); + LLVM_DEBUG(dbgs() << " deleted.\n"); } /// The liverange splitting logic sometimes produces bundles of copies when @@ -462,7 +461,7 @@ void VirtRegRewriter::rewrite() { for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end(); MBBI != MBBE; ++MBBI) { - DEBUG(MBBI->print(dbgs(), Indexes)); + LLVM_DEBUG(MBBI->print(dbgs(), Indexes)); for (MachineBasicBlock::instr_iterator MII = MBBI->instr_begin(), MIE = MBBI->instr_end(); MII != MIE;) { MachineInstr *MI = &*MII; @@ -545,7 +544,7 @@ void VirtRegRewriter::rewrite() { while (!SuperDefs.empty()) MI->addRegisterDefined(SuperDefs.pop_back_val(), TRI); - DEBUG(dbgs() << "> " << *MI); + LLVM_DEBUG(dbgs() << "> " << *MI); expandCopyBundle(*MI); diff --git a/llvm/lib/CodeGen/WinEHPrepare.cpp b/llvm/lib/CodeGen/WinEHPrepare.cpp index 2592c2d98ed..199e7228a8a 100644 --- a/llvm/lib/CodeGen/WinEHPrepare.cpp +++ b/llvm/lib/CodeGen/WinEHPrepare.cpp @@ -271,10 +271,11 @@ static void calculateCXXStateNumbers(WinEHFuncInfo &FuncInfo, } int CatchHigh = FuncInfo.getLastStateNumber(); addTryBlockMapEntry(FuncInfo, TryLow, TryHigh, CatchHigh, Handlers); - DEBUG(dbgs() << "TryLow[" << BB->getName() << "]: " << TryLow << '\n'); - DEBUG(dbgs() << "TryHigh[" << BB->getName() << "]: " << TryHigh << '\n'); - DEBUG(dbgs() << "CatchHigh[" << BB->getName() << "]: " << CatchHigh - << '\n'); + LLVM_DEBUG(dbgs() << "TryLow[" << BB->getName() << "]: " << TryLow << '\n'); + LLVM_DEBUG(dbgs() << "TryHigh[" << BB->getName() << "]: " << TryHigh + << '\n'); + LLVM_DEBUG(dbgs() << "CatchHigh[" << BB->getName() << "]: " << CatchHigh + << '\n'); } else { auto *CleanupPad = cast<CleanupPadInst>(FirstNonPHI); @@ -285,8 +286,8 @@ static void calculateCXXStateNumbers(WinEHFuncInfo &FuncInfo, int CleanupState = addUnwindMapEntry(FuncInfo, ParentState, BB); FuncInfo.EHPadStateMap[CleanupPad] = CleanupState; - DEBUG(dbgs() << "Assigning state #" << CleanupState << " to BB " - << BB->getName() << '\n'); + LLVM_DEBUG(dbgs() << "Assigning state #" << CleanupState << " to BB " + << BB->getName() << '\n'); for (const BasicBlock *PredBlock : predecessors(BB)) { if ((PredBlock = getEHPadFromPredecessor(PredBlock, CleanupPad->getParentPad()))) { @@ -351,8 +352,8 @@ static void calculateSEHStateNumbers(WinEHFuncInfo &FuncInfo, // Everything in the __try block uses TryState as its parent state. FuncInfo.EHPadStateMap[CatchSwitch] = TryState; - DEBUG(dbgs() << "Assigning state #" << TryState << " to BB " - << CatchPadBB->getName() << '\n'); + LLVM_DEBUG(dbgs() << "Assigning state #" << TryState << " to BB " + << CatchPadBB->getName() << '\n'); for (const BasicBlock *PredBlock : predecessors(BB)) if ((PredBlock = getEHPadFromPredecessor(PredBlock, CatchSwitch->getParentPad()))) @@ -387,8 +388,8 @@ static void calculateSEHStateNumbers(WinEHFuncInfo &FuncInfo, int CleanupState = addSEHFinally(FuncInfo, ParentState, BB); FuncInfo.EHPadStateMap[CleanupPad] = CleanupState; - DEBUG(dbgs() << "Assigning state #" << CleanupState << " to BB " - << BB->getName() << '\n'); + LLVM_DEBUG(dbgs() << "Assigning state #" << CleanupState << " to BB " + << BB->getName() << '\n'); for (const BasicBlock *PredBlock : predecessors(BB)) if ((PredBlock = getEHPadFromPredecessor(PredBlock, CleanupPad->getParentPad()))) @@ -1034,17 +1035,17 @@ bool WinEHPrepare::prepareExplicitEH(Function &F) { demotePHIsOnFunclets(F); if (!DisableCleanups) { - DEBUG(verifyFunction(F)); + LLVM_DEBUG(verifyFunction(F)); removeImplausibleInstructions(F); - DEBUG(verifyFunction(F)); + LLVM_DEBUG(verifyFunction(F)); cleanupPreparedFunclets(F); } - DEBUG(verifyPreparedFunclets(F)); + LLVM_DEBUG(verifyPreparedFunclets(F)); // Recolor the CFG to verify that all is well. - DEBUG(colorFunclets(F)); - DEBUG(verifyPreparedFunclets(F)); + LLVM_DEBUG(colorFunclets(F)); + LLVM_DEBUG(verifyPreparedFunclets(F)); BlockColors.clear(); FuncletBlocks.clear(); |
