diff options
| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-07-21 23:56:13 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-07-21 23:56:13 +0000 |
| commit | 6a963f76cad7ecaf93c2f53359069ced354f340c (patch) | |
| tree | 95e98582ab3a659ec2cbfe20c3b1f2f7132dfd9d /llvm/lib/CodeGen/RegAllocBase.cpp | |
| parent | 3545ee5f3f4b385cfef109006ec9d58f6a9663e7 (diff) | |
| download | bcm5719-llvm-6a963f76cad7ecaf93c2f53359069ced354f340c.tar.gz bcm5719-llvm-6a963f76cad7ecaf93c2f53359069ced354f340c.zip | |
RA: Remove assert on empty live intervals
This is possible if there is an undef use when
splitting the vreg during spilling.
Fixes bug 33620.
llvm-svn: 308808
Diffstat (limited to 'llvm/lib/CodeGen/RegAllocBase.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/RegAllocBase.cpp | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/RegAllocBase.cpp b/llvm/lib/CodeGen/RegAllocBase.cpp index a7b7a9f8ab1..5a80bd95d6e 100644 --- a/llvm/lib/CodeGen/RegAllocBase.cpp +++ b/llvm/lib/CodeGen/RegAllocBase.cpp @@ -144,7 +144,6 @@ void RegAllocBase::allocatePhysRegs() { continue; } DEBUG(dbgs() << "queuing new interval: " << *SplitVirtReg << "\n"); - assert(!SplitVirtReg->empty() && "expecting non-empty interval"); assert(TargetRegisterInfo::isVirtualRegister(SplitVirtReg->reg) && "expect split value in virtual register"); enqueue(SplitVirtReg); |
