diff options
| -rw-r--r-- | llvm/lib/CodeGen/RegAllocBase.cpp | 1 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/spill-empty-live-interval.mir | 40 |
2 files changed, 40 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/RegAllocBase.cpp b/llvm/lib/CodeGen/RegAllocBase.cpp index a7b7a9f8ab1..5a80bd95d6e 100644 --- a/llvm/lib/CodeGen/RegAllocBase.cpp +++ b/llvm/lib/CodeGen/RegAllocBase.cpp @@ -144,7 +144,6 @@ void RegAllocBase::allocatePhysRegs() { continue; } DEBUG(dbgs() << "queuing new interval: " << *SplitVirtReg << "\n"); - assert(!SplitVirtReg->empty() && "expecting non-empty interval"); assert(TargetRegisterInfo::isVirtualRegister(SplitVirtReg->reg) && "expect split value in virtual register"); enqueue(SplitVirtReg); diff --git a/llvm/test/CodeGen/AMDGPU/spill-empty-live-interval.mir b/llvm/test/CodeGen/AMDGPU/spill-empty-live-interval.mir new file mode 100644 index 00000000000..68bd8c45dcb --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/spill-empty-live-interval.mir @@ -0,0 +1,40 @@ +# RUN: llc -mtriple=amdgcn-amd-amdhsa-opencl -verify-machineinstrs -stress-regalloc=1 -start-before=simple-register-coalescing -stop-after=greedy -o - %s | FileCheck %s +# https://bugs.llvm.org/show_bug.cgi?id=33620 + +--- +# This would assert due to the empty live interval created for %vreg9 +# on the last S_NOP with an undef subreg use. + +# CHECK-LABEL: name: expecting_non_empty_interval + +# CHECK: undef %7.sub1 = V_MAC_F32_e32 0, undef %1, undef %7.sub1, implicit %exec +# CHECK-NEXT: SI_SPILL_V64_SAVE %7, %stack.0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr5, 0, implicit %exec :: (store 8 into %stack.0, align 4) +# CHECK-NEXT: undef %5.sub1 = V_MOV_B32_e32 1786773504, implicit %exec +# CHECK-NEXT: dead %2 = V_MUL_F32_e32 0, %5.sub1, implicit %exec + +# CHECK: S_NOP 0, implicit %6.sub1 +# CHECK-NEXT: %8 = SI_SPILL_V64_RESTORE %stack.0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr5, 0, implicit %exec :: (load 8 from %stack.0, align 4) +# CHECK-NEXT: S_NOP 0, implicit %8.sub1 +# CHECK-NEXT: S_NOP 0, implicit undef %9.sub0 + +name: expecting_non_empty_interval +tracksRegLiveness: true +registers: + - { id: 0, class: vreg_64, preferred-register: '' } + - { id: 1, class: vgpr_32, preferred-register: '' } + - { id: 2, class: vgpr_32, preferred-register: '' } + - { id: 3, class: vreg_64, preferred-register: '' } +body: | + bb.0: + successors: %bb.1 + undef %0.sub1 = V_MAC_F32_e32 0, undef %1, undef %0.sub1, implicit %exec + undef %3.sub1 = V_MOV_B32_e32 1786773504, implicit %exec + dead %2 = V_MUL_F32_e32 0, %3.sub1, implicit %exec + + bb.1: + S_NOP 0, implicit %3.sub1 + S_NOP 0, implicit %0.sub1 + S_NOP 0, implicit undef %0.sub0 + S_ENDPGM + +... |
