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author | Nicola Zaghen <nicola.zaghen@imgtec.com> | 2018-05-14 12:53:11 +0000 |
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committer | Nicola Zaghen <nicola.zaghen@imgtec.com> | 2018-05-14 12:53:11 +0000 |
commit | d34e60ca8532511acb8c93ef26297e349fbec86a (patch) | |
tree | 1a095bc8694498d94232e81b95c1da05d462d3ec /llvm/lib/CodeGen/PostRASchedulerList.cpp | |
parent | affbc99bea94e77f7ebccd8ba887e33051bd04ee (diff) | |
download | bcm5719-llvm-d34e60ca8532511acb8c93ef26297e349fbec86a.tar.gz bcm5719-llvm-d34e60ca8532511acb8c93ef26297e349fbec86a.zip |
Rename DEBUG macro to LLVM_DEBUG.
The DEBUG() macro is very generic so it might clash with other projects.
The renaming was done as follows:
- git grep -l 'DEBUG' | xargs sed -i 's/\bDEBUG\s\?(/LLVM_DEBUG(/g'
- git diff -U0 master | ../clang/tools/clang-format/clang-format-diff.py -i -p1 -style LLVM
- Manual change to APInt
- Manually chage DOCS as regex doesn't match it.
In the transition period the DEBUG() macro is still present and aliased
to the LLVM_DEBUG() one.
Differential Revision: https://reviews.llvm.org/D43624
llvm-svn: 332240
Diffstat (limited to 'llvm/lib/CodeGen/PostRASchedulerList.cpp')
-rw-r--r-- | llvm/lib/CodeGen/PostRASchedulerList.cpp | 44 |
1 files changed, 23 insertions, 21 deletions
diff --git a/llvm/lib/CodeGen/PostRASchedulerList.cpp b/llvm/lib/CodeGen/PostRASchedulerList.cpp index 2e5e6754bd2..215da630caf 100644 --- a/llvm/lib/CodeGen/PostRASchedulerList.cpp +++ b/llvm/lib/CodeGen/PostRASchedulerList.cpp @@ -243,11 +243,11 @@ void SchedulePostRATDList::enterRegion(MachineBasicBlock *bb, /// Print the schedule before exiting the region. void SchedulePostRATDList::exitRegion() { - DEBUG({ - dbgs() << "*** Final schedule ***\n"; - dumpSchedule(); - dbgs() << '\n'; - }); + LLVM_DEBUG({ + dbgs() << "*** Final schedule ***\n"; + dumpSchedule(); + dbgs() << '\n'; + }); ScheduleDAGInstrs::exitRegion(); } @@ -309,7 +309,7 @@ bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) { : TargetSubtargetInfo::ANTIDEP_NONE); } - DEBUG(dbgs() << "PostRAScheduler\n"); + LLVM_DEBUG(dbgs() << "PostRAScheduler\n"); SchedulePostRATDList Scheduler(Fn, MLI, AA, RegClassInfo, AntiDepMode, CriticalPathRCs); @@ -413,13 +413,12 @@ void SchedulePostRATDList::schedule() { postprocessDAG(); - DEBUG(dbgs() << "********** List Scheduling **********\n"); - DEBUG( - for (const SUnit &SU : SUnits) { - SU.dumpAll(this); - dbgs() << '\n'; - } - ); + LLVM_DEBUG(dbgs() << "********** List Scheduling **********\n"); + LLVM_DEBUG(for (const SUnit &SU + : SUnits) { + SU.dumpAll(this); + dbgs() << '\n'; + }); AvailableQueue.initNodes(SUnits); ListScheduleTopDown(); @@ -502,8 +501,8 @@ void SchedulePostRATDList::ReleaseSuccessors(SUnit *SU) { /// count of its successors. If a successor pending count is zero, add it to /// the Available queue. void SchedulePostRATDList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) { - DEBUG(dbgs() << "*** Scheduling [" << CurCycle << "]: "); - DEBUG(SU->dump(this)); + LLVM_DEBUG(dbgs() << "*** Scheduling [" << CurCycle << "]: "); + LLVM_DEBUG(SU->dump(this)); Sequence.push_back(SU); assert(CurCycle >= SU->getDepth() && @@ -517,7 +516,7 @@ void SchedulePostRATDList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) { /// emitNoop - Add a noop to the current instruction sequence. void SchedulePostRATDList::emitNoop(unsigned CurCycle) { - DEBUG(dbgs() << "*** Emitting noop in cycle " << CurCycle << '\n'); + LLVM_DEBUG(dbgs() << "*** Emitting noop in cycle " << CurCycle << '\n'); HazardRec->EmitNoop(); Sequence.push_back(nullptr); // NULL here means noop ++NumNoops; @@ -569,7 +568,8 @@ void SchedulePostRATDList::ListScheduleTopDown() { MinDepth = PendingQueue[i]->getDepth(); } - DEBUG(dbgs() << "\n*** Examining Available\n"; AvailableQueue.dump(this)); + LLVM_DEBUG(dbgs() << "\n*** Examining Available\n"; + AvailableQueue.dump(this)); SUnit *FoundSUnit = nullptr, *NotPreferredSUnit = nullptr; bool HasNoopHazards = false; @@ -605,7 +605,8 @@ void SchedulePostRATDList::ListScheduleTopDown() { // non-preferred node. if (NotPreferredSUnit) { if (!FoundSUnit) { - DEBUG(dbgs() << "*** Will schedule a non-preferred instruction...\n"); + LLVM_DEBUG( + dbgs() << "*** Will schedule a non-preferred instruction...\n"); FoundSUnit = NotPreferredSUnit; } else { AvailableQueue.push(NotPreferredSUnit); @@ -632,19 +633,20 @@ void SchedulePostRATDList::ListScheduleTopDown() { HazardRec->EmitInstruction(FoundSUnit); CycleHasInsts = true; if (HazardRec->atIssueLimit()) { - DEBUG(dbgs() << "*** Max instructions per cycle " << CurCycle << '\n'); + LLVM_DEBUG(dbgs() << "*** Max instructions per cycle " << CurCycle + << '\n'); HazardRec->AdvanceCycle(); ++CurCycle; CycleHasInsts = false; } } else { if (CycleHasInsts) { - DEBUG(dbgs() << "*** Finished cycle " << CurCycle << '\n'); + LLVM_DEBUG(dbgs() << "*** Finished cycle " << CurCycle << '\n'); HazardRec->AdvanceCycle(); } else if (!HasNoopHazards) { // Otherwise, we have a pipeline stall, but no other problem, // just advance the current cycle and try again. - DEBUG(dbgs() << "*** Stall in cycle " << CurCycle << '\n'); + LLVM_DEBUG(dbgs() << "*** Stall in cycle " << CurCycle << '\n'); HazardRec->AdvanceCycle(); ++NumStalls; } else { |