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authorMatt Arsenault <Matthew.Arsenault@amd.com>2017-10-25 07:14:07 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2017-10-25 07:14:07 +0000
commit8a752b77a2868066237f9ec4c5c9b292f9983afa (patch)
tree46a4638b195b8f8d3e75ea06ba54e12d44a45ac5 /llvm/lib/CodeGen/MachineScheduler.cpp
parent28f52e51f1c6253abc6a2cf0203f834805ed3a2d (diff)
downloadbcm5719-llvm-8a752b77a2868066237f9ec4c5c9b292f9983afa.tar.gz
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DAG: Fix creating select with wrong condition type
This code added in r297930 assumed that it could create a select with a condition type that is just an integer bitcast of the selected type. For AMDGPU any vselect is going to be scalarized (although the vector types are legal), and all select conditions must be i1 (the same as getSetCCResultType). This logic doesn't really make sense to me, but there's never really been a consistent policy in what the select condition mask type is supposed to be. Try to extend the logic for skipping the transform for condition types that aren't setccs. It doesn't seem quite right to me though, but checking conditions that seem more sensible (like whether the vselect is going to be expanded) doesn't work since this seems to depend on that also. llvm-svn: 316554
Diffstat (limited to 'llvm/lib/CodeGen/MachineScheduler.cpp')
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