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| author | Craig Topper <craig.topper@intel.com> | 2018-07-09 18:23:55 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-07-09 18:23:55 +0000 |
| commit | e3b0c7e5bd4d9e8e39a8ef8e0e039e7ddab9e0ad (patch) | |
| tree | 0997233787c871e00c558f227c3eaba02226e41b /llvm/lib/CodeGen/MachineRegisterInfo.cpp | |
| parent | 61d44f188ac3bb10505246ffb9185d2a0747db95 (diff) | |
| download | bcm5719-llvm-e3b0c7e5bd4d9e8e39a8ef8e0e039e7ddab9e0ad.tar.gz bcm5719-llvm-e3b0c7e5bd4d9e8e39a8ef8e0e039e7ddab9e0ad.zip | |
[SelectionDAG] Add VT consistency checks to the creation of ISD::FMA.
This is similar to what is done for binops. I don't know if this would have helped us catch the bug fixed in r336566 earlier or not, but I figured it couldn't hurt.
llvm-svn: 336576
Diffstat (limited to 'llvm/lib/CodeGen/MachineRegisterInfo.cpp')
0 files changed, 0 insertions, 0 deletions
