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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-12-19 13:16:43 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-12-19 13:16:43 +0000 |
| commit | fd5df639a3c464b5be20c5cd7746528b369fa740 (patch) | |
| tree | 4e927b1d84318cd7a227d70932e03c8b0ebdc9cb /llvm/lib/CodeGen/MachineOperand.cpp | |
| parent | b536a2a5ba0958619b6e9ce6304f863845eeda30 (diff) | |
| download | bcm5719-llvm-fd5df639a3c464b5be20c5cd7746528b369fa740.tar.gz bcm5719-llvm-fd5df639a3c464b5be20c5cd7746528b369fa740.zip | |
[X86][SSE] Add cpu feature for aggressive combining to variable shuffles
As mentioned in D38318 and D40865, modern Intel processors prefer to combine multiple shuffles to a variable shuffle mask (PSHUFB/VPERMPS etc.) instead of having multiple stage 'fixed' shuffles which put more pressure on Port 5 (at the expense of extra shuffle mask loads).
This patch provides a FeatureFastVariableShuffle target flag for Haswell+ CPUs that prefers combining 2 or more fixed shuffles to a single variable shuffle (default is 3 shuffles).
The long term aim is to drive more of this from schedule data (probably via the MC) but we're not close to being ready for that yet.
Differential Revision: https://reviews.llvm.org/D41323
llvm-svn: 321074
Diffstat (limited to 'llvm/lib/CodeGen/MachineOperand.cpp')
0 files changed, 0 insertions, 0 deletions
