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authorAlkis Evlogimenos <alkis@evlogimenos.com>2004-02-13 21:01:20 +0000
committerAlkis Evlogimenos <alkis@evlogimenos.com>2004-02-13 21:01:20 +0000
commit8cdd0215bf004968dffc50c73c9aaa19cee5822c (patch)
tree83a48d75e47bb8cf4445366cc9561a5f75e34c0e /llvm/lib/CodeGen/MachineInstr.cpp
parentef9d025ebedc5495b17ba41cb6f3d12bf29af022 (diff)
downloadbcm5719-llvm-8cdd0215bf004968dffc50c73c9aaa19cee5822c.tar.gz
bcm5719-llvm-8cdd0215bf004968dffc50c73c9aaa19cee5822c.zip
Remove getAllocatedRegNum(). Use getReg() instead.
llvm-svn: 11393
Diffstat (limited to 'llvm/lib/CodeGen/MachineInstr.cpp')
-rw-r--r--llvm/lib/CodeGen/MachineInstr.cpp10
1 files changed, 5 insertions, 5 deletions
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp
index b5ffd6215a8..ca2c2db4a84 100644
--- a/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/llvm/lib/CodeGen/MachineInstr.cpp
@@ -187,7 +187,7 @@ static inline std::ostream& OutputValue(std::ostream &os, const Value* val) {
static inline void OutputReg(std::ostream &os, unsigned RegNo,
const MRegisterInfo *MRI = 0) {
if (MRI) {
- if (RegNo < MRegisterInfo::FirstVirtualRegister)
+ if (MRegisterInfo::isPhysicalRegister(RegNo))
os << "%" << MRI->get(RegNo).Name;
else
os << "%reg" << RegNo;
@@ -219,14 +219,14 @@ static void print(const MachineOperand &MO, std::ostream &OS,
OS << "==";
}
if (MO.hasAllocatedReg())
- OutputReg(OS, MO.getAllocatedRegNum(), MRI);
+ OutputReg(OS, MO.getReg(), MRI);
break;
case MachineOperand::MO_CCRegister:
OS << "%ccreg";
OutputValue(OS, MO.getVRegValue());
if (MO.hasAllocatedReg()) {
OS << "==";
- OutputReg(OS, MO.getAllocatedRegNum(), MRI);
+ OutputReg(OS, MO.getReg(), MRI);
}
break;
case MachineOperand::MO_MachineRegister:
@@ -360,7 +360,7 @@ std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) {
{
case MachineOperand::MO_VirtualRegister:
if (MO.hasAllocatedReg())
- OutputReg(OS, MO.getAllocatedRegNum());
+ OutputReg(OS, MO.getReg());
if (MO.getVRegValue()) {
if (MO.hasAllocatedReg()) OS << "==";
@@ -373,7 +373,7 @@ std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) {
OutputValue(OS, MO.getVRegValue());
if (MO.hasAllocatedReg()) {
OS << "==";
- OutputReg(OS, MO.getAllocatedRegNum());
+ OutputReg(OS, MO.getReg());
}
break;
case MachineOperand::MO_MachineRegister:
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