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| author | Vikram S. Adve <vadve@cs.uiuc.edu> | 2003-05-27 00:02:22 +0000 |
|---|---|---|
| committer | Vikram S. Adve <vadve@cs.uiuc.edu> | 2003-05-27 00:02:22 +0000 |
| commit | 8adb9944aafd95a15264f27fc02eeecbde1d1d94 (patch) | |
| tree | 34462566d8a9913c788234ee1d688579046149fd /llvm/lib/CodeGen/MachineInstr.cpp | |
| parent | 196897c42457211b000ca17e9e90f5cee75ba2a5 (diff) | |
| download | bcm5719-llvm-8adb9944aafd95a15264f27fc02eeecbde1d1d94.tar.gz bcm5719-llvm-8adb9944aafd95a15264f27fc02eeecbde1d1d94.zip | |
Added special register class containing (for now) %fsr.
Fixed spilling of %fcc[0-3] which are part of %fsr.
Moved some machine-independent reg-class code to class TargetRegInfo
from SparcReg{Class,}Info.
llvm-svn: 6339
Diffstat (limited to 'llvm/lib/CodeGen/MachineInstr.cpp')
0 files changed, 0 insertions, 0 deletions
