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author | Chris Lattner <sabre@nondot.org> | 2006-05-04 00:49:59 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2006-05-04 00:49:59 +0000 |
commit | 6e663f1c1ec03c8660a0987e6be8f4d872c78445 (patch) | |
tree | c2689c10718a40adac53858f4d35c417583f1369 /llvm/lib/CodeGen/MachineInstr.cpp | |
parent | 9f6639b64d2ad1e09938696dac9de854b96d0bdd (diff) | |
download | bcm5719-llvm-6e663f1c1ec03c8660a0987e6be8f4d872c78445.tar.gz bcm5719-llvm-6e663f1c1ec03c8660a0987e6be8f4d872c78445.zip |
Remove some more V9-specific stuff.
llvm-svn: 28092
Diffstat (limited to 'llvm/lib/CodeGen/MachineInstr.cpp')
-rw-r--r-- | llvm/lib/CodeGen/MachineInstr.cpp | 34 |
1 files changed, 2 insertions, 32 deletions
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp index 8889a7aea2d..3d65dfd31bd 100644 --- a/llvm/lib/CodeGen/MachineInstr.cpp +++ b/llvm/lib/CodeGen/MachineInstr.cpp @@ -176,18 +176,6 @@ static void print(const MachineOperand &MO, std::ostream &OS, if (TM) MRI = TM->getRegisterInfo(); - bool CloseParen = true; - if (MO.isHiBits32()) - OS << "%lm("; - else if (MO.isLoBits32()) - OS << "%lo("; - else if (MO.isHiBits64()) - OS << "%hh("; - else if (MO.isLoBits64()) - OS << "%hm("; - else - CloseParen = false; - switch (MO.getType()) { case MachineOperand::MO_VirtualRegister: if (MO.getVRegValue()) { @@ -235,9 +223,6 @@ static void print(const MachineOperand &MO, std::ostream &OS, default: assert(0 && "Unrecognized operand type"); } - - if (CloseParen) - OS << ")"; } void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const { @@ -272,8 +257,7 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const { OS << "\n"; } -namespace llvm { -std::ostream &operator<<(std::ostream &os, const MachineInstr &MI) { +std::ostream &llvm::operator<<(std::ostream &os, const MachineInstr &MI) { // If the instruction is embedded into a basic block, we can find the target // info for the instruction. if (const MachineBasicBlock *MBB = MI.getParent()) { @@ -301,16 +285,7 @@ std::ostream &operator<<(std::ostream &os, const MachineInstr &MI) { return os << "\n"; } -std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) { - if (MO.isHiBits32()) - OS << "%lm("; - else if (MO.isLoBits32()) - OS << "%lo("; - else if (MO.isHiBits64()) - OS << "%hh("; - else if (MO.isLoBits64()) - OS << "%hm("; - +std::ostream &llvm::operator<<(std::ostream &OS, const MachineOperand &MO) { switch (MO.getType()) { case MachineOperand::MO_VirtualRegister: if (MO.hasAllocatedReg()) @@ -356,10 +331,5 @@ std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) { break; } - if (MO.isHiBits32() || MO.isLoBits32() || MO.isHiBits64() || MO.isLoBits64()) - OS << ")"; - return OS; } - -} |