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authorVikram S. Adve <vadve@cs.uiuc.edu>2002-07-08 22:38:45 +0000
committerVikram S. Adve <vadve@cs.uiuc.edu>2002-07-08 22:38:45 +0000
commit6c013a96897891b52ea286d50966832b738ac722 (patch)
treec548573ebeba2c85a09036e0f5bcda1f890b96b1 /llvm/lib/CodeGen/MachineInstr.cpp
parentff045b2e18b08bee0aed340043e685889715eb86 (diff)
downloadbcm5719-llvm-6c013a96897891b52ea286d50966832b738ac722.tar.gz
bcm5719-llvm-6c013a96897891b52ea286d50966832b738ac722.zip
Moved class MachineCodeForBasicBlock to MachineCodeForBasicBlock.{cpp,h}.
An (explicit or implicit) operand may now be both a def and a use. Also add a set of regs used by each instruction. dump() no longer takes an optional argument, which doesn't work in gdb. llvm-svn: 2821
Diffstat (limited to 'llvm/lib/CodeGen/MachineInstr.cpp')
-rw-r--r--llvm/lib/CodeGen/MachineInstr.cpp36
1 files changed, 25 insertions, 11 deletions
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp
index b113c602cf2..09992728574 100644
--- a/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/llvm/lib/CodeGen/MachineInstr.cpp
@@ -42,13 +42,16 @@ MachineInstr::MachineInstr(MachineOpCode _opCode,
void
MachineInstr::SetMachineOperandVal(unsigned int i,
- MachineOperand::MachineOperandType operandType,
- Value* _val, bool isdef=false)
+ MachineOperand::MachineOperandType opType,
+ Value* _val,
+ bool isdef=false,
+ bool isDefAndUse=false)
{
assert(i < operands.size());
- operands[i].Initialize(operandType, _val);
+ operands[i].Initialize(opType, _val);
operands[i].isDef = isdef ||
TargetInstrDescriptors[opCode].resultPos == (int) i;
+ operands[i].isDefAndUse = isDefAndUse;
}
void
@@ -61,27 +64,36 @@ MachineInstr::SetMachineOperandConst(unsigned int i,
"immed. constant cannot be defined");
operands[i].InitializeConst(operandType, intValue);
operands[i].isDef = false;
+ operands[i].isDefAndUse = false;
}
void
MachineInstr::SetMachineOperandReg(unsigned int i,
int regNum,
bool isdef=false,
+ bool isDefAndUse=false,
bool isCCReg=false)
{
assert(i < operands.size());
operands[i].InitializeReg(regNum, isCCReg);
operands[i].isDef = isdef ||
TargetInstrDescriptors[opCode].resultPos == (int) i;
+ operands[i].isDefAndUse = isDefAndUse;
+ regsUsed.insert(regNum);
}
void
-MachineInstr::dump(unsigned int indent) const
+MachineInstr::SetRegForOperand(unsigned i, int regNum)
{
- for (unsigned i=0; i < indent; i++)
- cerr << " ";
-
- cerr << *this;
+ operands[i].setRegForValue(regNum);
+ regsUsed.insert(regNum);
+}
+
+
+void
+MachineInstr::dump() const
+{
+ cerr << " " << *this;
}
static inline std::ostream &OutputValue(std::ostream &os,
@@ -101,7 +113,9 @@ std::ostream &operator<<(std::ostream& os, const MachineInstr& minstr)
for (unsigned i=0, N=minstr.getNumOperands(); i < N; i++) {
os << "\t" << minstr.getOperand(i);
- if( minstr.getOperand(i).opIsDef() )
+ if( minstr.operandIsDefined(i) )
+ os << "*";
+ if( minstr.operandIsDefinedAndUsed(i) )
os << "*";
}
@@ -112,6 +126,7 @@ std::ostream &operator<<(std::ostream& os, const MachineInstr& minstr)
for(unsigned z=0; z < NumOfImpRefs; z++) {
OutputValue(os, minstr.getImplicitRef(z));
if( minstr.implicitRefIsDefined(z)) os << "*";
+ if( minstr.implicitRefIsDefinedAndUsed(z)) os << "*";
os << "\t";
}
}
@@ -136,7 +151,6 @@ static inline std::ostream &OutputOperand(std::ostream &os,
}
}
-
std::ostream &operator<<(std::ostream &os, const MachineOperand &mop)
{
switch(mop.opType)
@@ -160,7 +174,7 @@ std::ostream &operator<<(std::ostream &os, const MachineOperand &mop)
if (opVal->hasName())
os << opVal->getName();
else
- os << opVal;
+ os << (const void*) opVal;
return os << ")";
}
default:
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