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authorEvan Cheng <evan.cheng@apple.com>2010-10-22 21:49:09 +0000
committerEvan Cheng <evan.cheng@apple.com>2010-10-22 21:49:09 +0000
commit21eedfb5a2829c0216b31aa541ed2b538ce8424e (patch)
treefabffc96f50c48462d08ec15406556e156b1d903 /llvm/lib/CodeGen/MachineInstr.cpp
parenta4e231c880e83317ee4463abb12f7f2d8568aa6f (diff)
downloadbcm5719-llvm-21eedfb5a2829c0216b31aa541ed2b538ce8424e.tar.gz
bcm5719-llvm-21eedfb5a2829c0216b31aa541ed2b538ce8424e.zip
Unbreak build.
llvm-svn: 117155
Diffstat (limited to 'llvm/lib/CodeGen/MachineInstr.cpp')
-rw-r--r--llvm/lib/CodeGen/MachineInstr.cpp11
1 files changed, 11 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp
index 6f0b9719e1a..bc2a545a5f2 100644
--- a/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/llvm/lib/CodeGen/MachineInstr.cpp
@@ -1253,6 +1253,17 @@ bool MachineInstr::allDefsAreDead() const {
return true;
}
+/// copyImplicitOps - Copy implicit register operands from specified
+/// instruction to this instruction.
+void MachineInstr::copyImplicitOps(const MachineInstr *MI) {
+ for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
+ i != e; ++i) {
+ const MachineOperand &MO = MI->getOperand(i);
+ if (MO.isReg() && MO.isImplicit())
+ addOperand(MO);
+ }
+}
+
void MachineInstr::dump() const {
dbgs() << " " << *this;
}
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