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authorDuncan P. N. Exon Smith <dexonsmith@apple.com>2014-10-03 20:01:09 +0000
committerDuncan P. N. Exon Smith <dexonsmith@apple.com>2014-10-03 20:01:09 +0000
commit176b691d322208a192e24aaa928cd5c072046a97 (patch)
tree5080d66b5d84122a2842a47d6fd625293280bdd5 /llvm/lib/CodeGen/MachineInstr.cpp
parentff63a2dc51af5eaeb48887e345e1e1ce51e17476 (diff)
downloadbcm5719-llvm-176b691d322208a192e24aaa928cd5c072046a97.tar.gz
bcm5719-llvm-176b691d322208a192e24aaa928cd5c072046a97.zip
Revert "Revert "DI: Fold constant arguments into a single MDString""
This reverts commit r218918, effectively reapplying r218914 after fixing an Ocaml bindings test and an Asan crash. The root cause of the latter was a tightened-up check in `DILexicalBlock::Verify()`, so I'll file a PR to investigate who requires the loose check (and why). Original commit message follows. -- This patch addresses the first stage of PR17891 by folding constant arguments together into a single MDString. Integers are stringified and a `\0` character is used as a separator. Part of PR17891. Note: I've attached my testcases upgrade scripts to the PR. If I've just broken your out-of-tree testcases, they might help. llvm-svn: 219010
Diffstat (limited to 'llvm/lib/CodeGen/MachineInstr.cpp')
-rw-r--r--llvm/lib/CodeGen/MachineInstr.cpp10
1 files changed, 5 insertions, 5 deletions
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp
index d33d4a9d26a..2e59f371826 100644
--- a/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/llvm/lib/CodeGen/MachineInstr.cpp
@@ -1643,11 +1643,11 @@ void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM,
if (isDebugValue() && MO.isMetadata()) {
// Pretty print DBG_VALUE instructions.
const MDNode *MD = MO.getMetadata();
- if (MD->getNumOperands() >= 2)
- if (const MDString *MDS = dyn_cast<MDString>(MD->getOperand(2)))
- OS << "!\"" << MDS->getString() << '\"';
- else
- MO.print(OS, TM);
+ DIDescriptor DI(MD);
+ DIVariable DIV(MD);
+
+ if (DI.isVariable() && !DIV.getName().empty())
+ OS << "!\"" << DIV.getName() << '\"';
else
MO.print(OS, TM);
} else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
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