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| author | Puyan Lotfi <puyan@puyan.org> | 2019-05-30 18:06:28 +0000 |
|---|---|---|
| committer | Puyan Lotfi <puyan@puyan.org> | 2019-05-30 18:06:28 +0000 |
| commit | 0f4446b2700a02612297bdb73a75a784a46d31bf (patch) | |
| tree | 9ab4069b8d96e8e34a1026c7f12213b809b1b738 /llvm/lib/CodeGen/LiveIntervalUnion.cpp | |
| parent | 50daaa5f6b2636578ac70ed08e0db246be3b95b8 (diff) | |
| download | bcm5719-llvm-0f4446b2700a02612297bdb73a75a784a46d31bf.tar.gz bcm5719-llvm-0f4446b2700a02612297bdb73a75a784a46d31bf.zip | |
[MIR-Canon] Add support for rewriting VRegs that are typed but don't have an RC.
There were crashes (addrspace-memoperands.mir was only one of them) in MIR that
had operands that came from before register classes were set. With these
operands, creating a replacement vreg (for MIR-Canon's renaming) needs to use
the vreg type rather than the RegisterClass which is not present.
Differential Revision: https://reviews.llvm.org/D62543
llvm-svn: 362122
Diffstat (limited to 'llvm/lib/CodeGen/LiveIntervalUnion.cpp')
0 files changed, 0 insertions, 0 deletions
