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| author | Marina Yatsina <marina.yatsina@intel.com> | 2016-07-21 12:37:07 +0000 |
|---|---|---|
| committer | Marina Yatsina <marina.yatsina@intel.com> | 2016-07-21 12:37:07 +0000 |
| commit | c1fa163392f52d2119dec645f4f127ef79b83310 (patch) | |
| tree | 2f6985de132bf3468ddc1354f9a9e48ac4ee3173 /llvm/lib/CodeGen/LatencyPriorityQueue.cpp | |
| parent | 2a185a2547caccd5e969e2c5e704ee9733aaa2fc (diff) | |
| download | bcm5719-llvm-c1fa163392f52d2119dec645f4f127ef79b83310.tar.gz bcm5719-llvm-c1fa163392f52d2119dec645f4f127ef79b83310.zip | |
ExecutionDepsFix - Fix bug in clearance calculation
The clearance calculation did not take into account registers defined as outputs or clobbers in inline assembly machine instructions because these register defs are implicit.
Differential Revision: http://reviews.llvm.org/D22580
llvm-svn: 276266
Diffstat (limited to 'llvm/lib/CodeGen/LatencyPriorityQueue.cpp')
0 files changed, 0 insertions, 0 deletions
