diff options
| author | Marina Yatsina <marina.yatsina@intel.com> | 2016-07-21 12:37:07 +0000 |
|---|---|---|
| committer | Marina Yatsina <marina.yatsina@intel.com> | 2016-07-21 12:37:07 +0000 |
| commit | c1fa163392f52d2119dec645f4f127ef79b83310 (patch) | |
| tree | 2f6985de132bf3468ddc1354f9a9e48ac4ee3173 | |
| parent | 2a185a2547caccd5e969e2c5e704ee9733aaa2fc (diff) | |
| download | bcm5719-llvm-c1fa163392f52d2119dec645f4f127ef79b83310.tar.gz bcm5719-llvm-c1fa163392f52d2119dec645f4f127ef79b83310.zip | |
ExecutionDepsFix - Fix bug in clearance calculation
The clearance calculation did not take into account registers defined as outputs or clobbers in inline assembly machine instructions because these register defs are implicit.
Differential Revision: http://reviews.llvm.org/D22580
llvm-svn: 276266
| -rw-r--r-- | llvm/lib/CodeGen/ExecutionDepsFix.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/break-false-dep.ll | 10 |
2 files changed, 10 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/ExecutionDepsFix.cpp b/llvm/lib/CodeGen/ExecutionDepsFix.cpp index 566b8d507b2..1fe5f459b69 100644 --- a/llvm/lib/CodeGen/ExecutionDepsFix.cpp +++ b/llvm/lib/CodeGen/ExecutionDepsFix.cpp @@ -520,8 +520,6 @@ void ExeDepsFix::processDefs(MachineInstr *MI, bool Kill) { MachineOperand &MO = MI->getOperand(i); if (!MO.isReg()) continue; - if (MO.isImplicit()) - break; if (MO.isUse()) continue; for (int rx : regIndices(MO.getReg())) { diff --git a/llvm/test/CodeGen/X86/break-false-dep.ll b/llvm/test/CodeGen/X86/break-false-dep.ll index 74a0728f918..a7cda499dab 100644 --- a/llvm/test/CodeGen/X86/break-false-dep.ll +++ b/llvm/test/CodeGen/X86/break-false-dep.ll @@ -199,3 +199,13 @@ for.end16: ; preds = %for.inc14 ;AVX-NEXT: vmulsd {{.*}}, [[XMM0]], [[XMM0]] ;AVX-NEXT: vmovsd [[XMM0]], } + +define double @inlineasmdep(i64 %arg) { +top: + tail call void asm sideeffect "", "~{xmm0},~{dirflag},~{fpsr},~{flags}"() + %tmp1 = sitofp i64 %arg to double + ret double %tmp1 +;AVX-LABEL:@inlineasmdep +;AVX: vxorps [[XMM0:%xmm[0-9]+]], [[XMM0]], [[XMM0]] +;AVX-NEXT: vcvtsi2sdq {{.*}}, [[XMM0]], {{%xmm[0-9]+}} +} |
