GlobalISel: improve representation of G_SEQUENCE and G_EXTRACT

First, make sure all types involved are represented, rather than being implicit
from the register width.

Second, canonicalize all types to scalar. These operations just act in bits and
don't care about vectors.

Also standardize spelling of Indices in the MachineIRBuilder (NFC here).

llvm-svn: 279294

1 files changed, 26 insertions, 11 deletions

diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
index 0ee70999b08..bd66a28bdc2 100644
--- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
@@ -141,33 +141,48 @@ MachineInstrBuilder MachineIRBuilder::buildAnyExtend(LLT Ty, unsigned Res,
   return buildInstr(TargetOpcode::G_ANYEXTEND, Ty).addDef(Res).addUse(Op);
 }
 
-MachineInstrBuilder
-MachineIRBuilder::buildExtract(LLT Ty, ArrayRef<unsigned> Results, unsigned Src,
-                               ArrayRef<uint64_t> Indexes) {
-  assert(Results.size() == Indexes.size() && "inconsistent number of regs");
+MachineInstrBuilder MachineIRBuilder::buildExtract(ArrayRef<LLT> ResTys,
+                                                   ArrayRef<unsigned> Results,
+                                                   ArrayRef<uint64_t> Indices,
+                                                   LLT SrcTy, unsigned Src) {
+  assert(ResTys.size() == Results.size() && Results.size() == Indices.size() &&
+         "inconsistent number of regs");
+  assert(!Results.empty() && "invalid trivial extract");
+
+  auto MIB = BuildMI(getMF(), DL, getTII().get(TargetOpcode::G_EXTRACT));
+  for (unsigned i = 0; i < ResTys.size(); ++i)
+    MIB->setType(LLT::scalar(ResTys[i].getSizeInBits()), i);
+  MIB->setType(LLT::scalar(SrcTy.getSizeInBits()), ResTys.size());
 
-  MachineInstrBuilder MIB = buildInstr(TargetOpcode::G_EXTRACT, Ty);
   for (auto Res : Results)
     MIB.addDef(Res);
 
   MIB.addUse(Src);
 
-  for (auto Idx : Indexes)
+  for (auto Idx : Indices)
     MIB.addImm(Idx);
+
+  getMBB().insert(getInsertPt(), MIB);
+
   return MIB;
 }
 
 MachineInstrBuilder
-MachineIRBuilder::buildSequence(LLT Ty, unsigned Res,
+MachineIRBuilder::buildSequence(LLT ResTy, unsigned Res,
+                                ArrayRef<LLT> OpTys,
                                 ArrayRef<unsigned> Ops,
-                                ArrayRef<unsigned> Indexes) {
-  assert(Ops.size() == Indexes.size() && "incompatible args");
+                                ArrayRef<unsigned> Indices) {
+  assert(OpTys.size() == Ops.size() && Ops.size() == Indices.size() &&
+         "incompatible args");
+  assert(!Ops.empty() && "invalid trivial sequence");
 
-  MachineInstrBuilder MIB = buildInstr(TargetOpcode::G_SEQUENCE, Ty);
+  MachineInstrBuilder MIB =
+      buildInstr(TargetOpcode::G_SEQUENCE, LLT::scalar(ResTy.getSizeInBits()));
   MIB.addDef(Res);
   for (unsigned i = 0; i < Ops.size(); ++i) {
     MIB.addUse(Ops[i]);
-    MIB.addImm(Indexes[i]);
+    MIB.addImm(Indices[i]);
+    MIB->setType(LLT::scalar(OpTys[i].getSizeInBits()), MIB->getNumTypes());
   }
   return MIB;
 }