GlobalISel: improve representation of G_SEQUENCE and G_EXTRACT

First, make sure all types involved are represented, rather than being implicit
from the register width.

Second, canonicalize all types to scalar. These operations just act in bits and
don't care about vectors.

Also standardize spelling of Indices in the MachineIRBuilder (NFC here).

llvm-svn: 279294

3 files changed, 42 insertions, 20 deletions

diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 8703915f919..545b85f1c21 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -197,8 +197,8 @@ bool IRTranslator::translateExtractValue(const User &U) {
   uint64_t Offset = 8 * DL->getIndexedOffsetInType(Src->getType(), Indices);
 
   unsigned Res = getOrCreateVReg(EVI);
-  MIRBuilder.buildExtract(LLT{*EVI.getType(), DL}, Res, getOrCreateVReg(*Src),
-                          Offset);
+  MIRBuilder.buildExtract(LLT{*EVI.getType(), DL}, Res, Offset,
+                          LLT{*Src->getType(), DL}, getOrCreateVReg(*Src));
 
   return true;
 }
@@ -255,8 +255,8 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI,
     MIB.addUse(Zero);
   }
 
-  MIRBuilder.buildSequence(LLT{*CI.getType(), DL}, getOrCreateVReg(CI), Res, 0,
-                           Overflow, Width);
+  MIRBuilder.buildSequence(LLT{*CI.getType(), DL}, getOrCreateVReg(CI), Ty, Res,
+                           0, s1, Overflow, Width);
   return true;
 }
 
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
index 0ee70999b08..bd66a28bdc2 100644
--- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
@@ -141,33 +141,48 @@ MachineInstrBuilder MachineIRBuilder::buildAnyExtend(LLT Ty, unsigned Res,
   return buildInstr(TargetOpcode::G_ANYEXTEND, Ty).addDef(Res).addUse(Op);
 }
 
-MachineInstrBuilder
-MachineIRBuilder::buildExtract(LLT Ty, ArrayRef<unsigned> Results, unsigned Src,
-                               ArrayRef<uint64_t> Indexes) {
-  assert(Results.size() == Indexes.size() && "inconsistent number of regs");
+MachineInstrBuilder MachineIRBuilder::buildExtract(ArrayRef<LLT> ResTys,
+                                                   ArrayRef<unsigned> Results,
+                                                   ArrayRef<uint64_t> Indices,
+                                                   LLT SrcTy, unsigned Src) {
+  assert(ResTys.size() == Results.size() && Results.size() == Indices.size() &&
+         "inconsistent number of regs");
+  assert(!Results.empty() && "invalid trivial extract");
+
+  auto MIB = BuildMI(getMF(), DL, getTII().get(TargetOpcode::G_EXTRACT));
+  for (unsigned i = 0; i < ResTys.size(); ++i)
+    MIB->setType(LLT::scalar(ResTys[i].getSizeInBits()), i);
+  MIB->setType(LLT::scalar(SrcTy.getSizeInBits()), ResTys.size());
 
-  MachineInstrBuilder MIB = buildInstr(TargetOpcode::G_EXTRACT, Ty);
   for (auto Res : Results)
     MIB.addDef(Res);
 
   MIB.addUse(Src);
 
-  for (auto Idx : Indexes)
+  for (auto Idx : Indices)
     MIB.addImm(Idx);
+
+  getMBB().insert(getInsertPt(), MIB);
+
   return MIB;
 }
 
 MachineInstrBuilder
-MachineIRBuilder::buildSequence(LLT Ty, unsigned Res,
+MachineIRBuilder::buildSequence(LLT ResTy, unsigned Res,
+                                ArrayRef<LLT> OpTys,
                                 ArrayRef<unsigned> Ops,
-                                ArrayRef<unsigned> Indexes) {
-  assert(Ops.size() == Indexes.size() && "incompatible args");
+                                ArrayRef<unsigned> Indices) {
+  assert(OpTys.size() == Ops.size() && Ops.size() == Indices.size() &&
+         "incompatible args");
+  assert(!Ops.empty() && "invalid trivial sequence");
 
-  MachineInstrBuilder MIB = buildInstr(TargetOpcode::G_SEQUENCE, Ty);
+  MachineInstrBuilder MIB =
+      buildInstr(TargetOpcode::G_SEQUENCE, LLT::scalar(ResTy.getSizeInBits()));
   MIB.addDef(Res);
   for (unsigned i = 0; i < Ops.size(); ++i) {
     MIB.addUse(Ops[i]);
-    MIB.addImm(Indexes[i]);
+    MIB.addImm(Indices[i]);
+    MIB->setType(LLT::scalar(OpTys[i].getSizeInBits()), MIB->getNumTypes());
   }
   return MIB;
 }
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp b/llvm/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp
index 6d2d1057a6b..29fdee8633f 100644
--- a/llvm/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp
@@ -52,11 +52,14 @@ void MachineLegalizeHelper::extractParts(unsigned Reg, LLT Ty, int NumParts,
                                          SmallVectorImpl<unsigned> &VRegs) {
   unsigned Size = Ty.getSizeInBits();
   SmallVector<uint64_t, 4> Indexes;
+  SmallVector<LLT, 4> ResTys;
   for (int i = 0; i < NumParts; ++i) {
     VRegs.push_back(MRI.createGenericVirtualRegister(Size));
     Indexes.push_back(i * Size);
+    ResTys.push_back(Ty);
   }
-  MIRBuilder.buildExtract(Ty, VRegs, Reg, Indexes);
+  MIRBuilder.buildExtract(ResTys, VRegs, Indexes,
+                          LLT::scalar(Ty.getSizeInBits() * NumParts), Reg);
 }
 
 MachineLegalizeHelper::LegalizeResult
@@ -78,6 +81,7 @@ MachineLegalizeHelper::narrowScalar(MachineInstr &MI, LLT NarrowTy) {
     unsigned CarryIn = MRI.createGenericVirtualRegister(1);
     MIRBuilder.buildConstant(LLT::scalar(1), CarryIn, 0);
 
+    SmallVector<LLT, 2> DstTys;
     for (int i = 0; i < NumParts; ++i) {
       unsigned DstReg = MRI.createGenericVirtualRegister(NarrowSize);
       unsigned CarryOut = MRI.createGenericVirtualRegister(1);
@@ -85,12 +89,13 @@ MachineLegalizeHelper::narrowScalar(MachineInstr &MI, LLT NarrowTy) {
       MIRBuilder.buildUAdde(NarrowTy, DstReg, CarryOut, Src1Regs[i],
                             Src2Regs[i], CarryIn);
 
+      DstTys.push_back(NarrowTy);
       DstRegs.push_back(DstReg);
       Indexes.push_back(i * NarrowSize);
       CarryIn = CarryOut;
     }
-    MIRBuilder.buildSequence(MI.getType(), MI.getOperand(0).getReg(), DstRegs,
-                             Indexes);
+    MIRBuilder.buildSequence(MI.getType(), MI.getOperand(0).getReg(), DstTys,
+                             DstRegs, Indexes);
     MI.eraseFromParent();
     return Legalized;
   }
@@ -146,15 +151,17 @@ MachineLegalizeHelper::fewerElementsVector(MachineInstr &MI, LLT NarrowTy) {
     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
 
+    SmallVector<LLT, 2> DstTys;
     for (int i = 0; i < NumParts; ++i) {
       unsigned DstReg = MRI.createGenericVirtualRegister(NarrowSize);
       MIRBuilder.buildAdd(NarrowTy, DstReg, Src1Regs[i], Src2Regs[i]);
+      DstTys.push_back(NarrowTy);
       DstRegs.push_back(DstReg);
       Indexes.push_back(i * NarrowSize);
     }
 
-    MIRBuilder.buildSequence(MI.getType(), MI.getOperand(0).getReg(), DstRegs,
-                             Indexes);
+    MIRBuilder.buildSequence(MI.getType(), MI.getOperand(0).getReg(), DstTys,
+                             DstRegs, Indexes);
     MI.eraseFromParent();
     return Legalized;
   }