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author | Aditya Nandakumar <aditya_nandakumar@apple.com> | 2017-08-25 04:57:27 +0000 |
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committer | Aditya Nandakumar <aditya_nandakumar@apple.com> | 2017-08-25 04:57:27 +0000 |
commit | 892979effc920252246c8e6909b552e936748a76 (patch) | |
tree | 5f7b3a2d8bb95904e766dcd47773f58e6bcb867f /llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | |
parent | 0f33300609a301650706022d03ec4433372796dd (diff) | |
download | bcm5719-llvm-892979effc920252246c8e6909b552e936748a76.tar.gz bcm5719-llvm-892979effc920252246c8e6909b552e936748a76.zip |
[GISel]: Implement widenScalar for Legalizing G_PHI
https://reviews.llvm.org/D37018
llvm-svn: 311763
Diffstat (limited to 'llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp')
-rw-r--r-- | llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp index c54b12b52ee..5e75f4da9bd 100644 --- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -659,6 +659,37 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) { MI.getOperand(2).setReg(OffsetExt); return Legalized; } + case TargetOpcode::G_PHI: { + assert(TypeIdx == 0 && "Expecting only Idx 0"); + MachineFunction *MF = MI.getParent()->getParent(); + auto getExtendedReg = [this, MF, WideTy](unsigned Reg, + MachineBasicBlock &MBB) { + auto FirstTermIt = MBB.getFirstTerminator(); + MIRBuilder.setInsertPt(MBB, FirstTermIt); + MachineInstr *DefMI = MRI.getVRegDef(Reg); + MachineInstrBuilder MIB; + if (DefMI->getOpcode() == TargetOpcode::G_TRUNC) + MIB = MIRBuilder.buildAnyExtOrTrunc(WideTy, + DefMI->getOperand(1).getReg()); + else + MIB = MIRBuilder.buildAnyExt(WideTy, Reg); + return MIB->getOperand(0).getReg(); + }; + auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_PHI, WideTy); + for (auto OpIt = MI.operands_begin() + 1, OpE = MI.operands_end(); + OpIt != OpE;) { + unsigned Reg = OpIt++->getReg(); + MachineBasicBlock *OpMBB = OpIt++->getMBB(); + MIB.addReg(getExtendedReg(Reg, *OpMBB)); + MIB.addMBB(OpMBB); + } + auto *MBB = MI.getParent(); + MIRBuilder.setInsertPt(*MBB, MBB->getFirstNonPHI()); + MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), + MIB->getOperand(0).getReg()); + MI.eraseFromParent(); + return Legalized; + } } } |