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authorAditya Nandakumar <aditya_nandakumar@apple.com>2017-08-25 04:57:27 +0000
committerAditya Nandakumar <aditya_nandakumar@apple.com>2017-08-25 04:57:27 +0000
commit892979effc920252246c8e6909b552e936748a76 (patch)
tree5f7b3a2d8bb95904e766dcd47773f58e6bcb867f /llvm/lib/CodeGen
parent0f33300609a301650706022d03ec4433372796dd (diff)
downloadbcm5719-llvm-892979effc920252246c8e6909b552e936748a76.tar.gz
bcm5719-llvm-892979effc920252246c8e6909b552e936748a76.zip
[GISel]: Implement widenScalar for Legalizing G_PHI
https://reviews.llvm.org/D37018 llvm-svn: 311763
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r--llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp31
-rw-r--r--llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp30
2 files changed, 47 insertions, 14 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index c54b12b52ee..5e75f4da9bd 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -659,6 +659,37 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
MI.getOperand(2).setReg(OffsetExt);
return Legalized;
}
+ case TargetOpcode::G_PHI: {
+ assert(TypeIdx == 0 && "Expecting only Idx 0");
+ MachineFunction *MF = MI.getParent()->getParent();
+ auto getExtendedReg = [this, MF, WideTy](unsigned Reg,
+ MachineBasicBlock &MBB) {
+ auto FirstTermIt = MBB.getFirstTerminator();
+ MIRBuilder.setInsertPt(MBB, FirstTermIt);
+ MachineInstr *DefMI = MRI.getVRegDef(Reg);
+ MachineInstrBuilder MIB;
+ if (DefMI->getOpcode() == TargetOpcode::G_TRUNC)
+ MIB = MIRBuilder.buildAnyExtOrTrunc(WideTy,
+ DefMI->getOperand(1).getReg());
+ else
+ MIB = MIRBuilder.buildAnyExt(WideTy, Reg);
+ return MIB->getOperand(0).getReg();
+ };
+ auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_PHI, WideTy);
+ for (auto OpIt = MI.operands_begin() + 1, OpE = MI.operands_end();
+ OpIt != OpE;) {
+ unsigned Reg = OpIt++->getReg();
+ MachineBasicBlock *OpMBB = OpIt++->getMBB();
+ MIB.addReg(getExtendedReg(Reg, *OpMBB));
+ MIB.addMBB(OpMBB);
+ }
+ auto *MBB = MI.getParent();
+ MIRBuilder.setInsertPt(*MBB, MBB->getFirstNonPHI());
+ MIRBuilder.buildTrunc(MI.getOperand(0).getReg(),
+ MIB->getOperand(0).getReg());
+ MI.eraseFromParent();
+ return Legalized;
+ }
}
}
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
index 8ca07f36c9c..b4fe5f15fdd 100644
--- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
@@ -346,14 +346,17 @@ MachineInstrBuilder MachineIRBuilder::buildZExt(unsigned Res, unsigned Op) {
return buildInstr(TargetOpcode::G_ZEXT).addDef(Res).addUse(Op);
}
-MachineInstrBuilder MachineIRBuilder::buildSExtOrTrunc(unsigned Res,
- unsigned Op) {
+MachineInstrBuilder
+MachineIRBuilder::buildExtOrTrunc(unsigned ExtOpc, unsigned Res, unsigned Op) {
+ assert((TargetOpcode::G_ANYEXT == ExtOpc || TargetOpcode::G_ZEXT == ExtOpc ||
+ TargetOpcode::G_SEXT == ExtOpc) &&
+ "Expecting Extending Opc");
assert(MRI->getType(Res).isScalar() || MRI->getType(Res).isVector());
assert(MRI->getType(Res).isScalar() == MRI->getType(Op).isScalar());
unsigned Opcode = TargetOpcode::COPY;
if (MRI->getType(Res).getSizeInBits() > MRI->getType(Op).getSizeInBits())
- Opcode = TargetOpcode::G_SEXT;
+ Opcode = ExtOpc;
else if (MRI->getType(Res).getSizeInBits() < MRI->getType(Op).getSizeInBits())
Opcode = TargetOpcode::G_TRUNC;
else
@@ -362,20 +365,19 @@ MachineInstrBuilder MachineIRBuilder::buildSExtOrTrunc(unsigned Res,
return buildInstr(Opcode).addDef(Res).addUse(Op);
}
-MachineInstrBuilder MachineIRBuilder::buildZExtOrTrunc(unsigned Res,
+MachineInstrBuilder MachineIRBuilder::buildSExtOrTrunc(unsigned Res,
unsigned Op) {
- assert(MRI->getType(Res).isScalar() || MRI->getType(Res).isVector());
- assert(MRI->getType(Res).isScalar() == MRI->getType(Op).isScalar());
+ return buildExtOrTrunc(TargetOpcode::G_SEXT, Res, Op);
+}
- unsigned Opcode = TargetOpcode::COPY;
- if (MRI->getType(Res).getSizeInBits() > MRI->getType(Op).getSizeInBits())
- Opcode = TargetOpcode::G_ZEXT;
- else if (MRI->getType(Res).getSizeInBits() < MRI->getType(Op).getSizeInBits())
- Opcode = TargetOpcode::G_TRUNC;
- else
- assert(MRI->getType(Res) == MRI->getType(Op));
+MachineInstrBuilder MachineIRBuilder::buildZExtOrTrunc(unsigned Res,
+ unsigned Op) {
+ return buildExtOrTrunc(TargetOpcode::G_ZEXT, Res, Op);
+}
- return buildInstr(Opcode).addDef(Res).addUse(Op);
+MachineInstrBuilder MachineIRBuilder::buildAnyExtOrTrunc(unsigned Res,
+ unsigned Op) {
+ return buildExtOrTrunc(TargetOpcode::G_ANYEXT, Res, Op);
}
MachineInstrBuilder MachineIRBuilder::buildCast(unsigned Dst, unsigned Src) {
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