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authorAndrea Di Biagio <Andrea_DiBiagio@sn.scee.net>2018-08-13 11:09:04 +0000
committerAndrea Di Biagio <Andrea_DiBiagio@sn.scee.net>2018-08-13 11:09:04 +0000
commit24d86d8513d59c0c294b6a3db40eebdc26f36702 (patch)
tree0c0ab2a5a404b73ad35b9c41cf936050c104f94f /llvm/lib/CodeGen/CodeGenPrepare.cpp
parent1bfbc62022290f282aef2765c5878ad82a4a4c46 (diff)
downloadbcm5719-llvm-24d86d8513d59c0c294b6a3db40eebdc26f36702.tar.gz
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[Tablegen][SubtargetEmitter] Improve expansion of predicates of a variant scheduling class.
This patch refactors the logic that expands predicates of a variant scheduling class. The idea is to improve the readability of the auto-generated code by removing redundant parentheses around predicate expressions, and by removing redundant if(true) statements. This patch replaces the definition of NoSchedPred in TargetSchedule.td with an instance of MCSchedPredicate. The new definition is sematically equivalent to the previous one. The main difference is that now SubtargetEmitter knows that it represents predicate "true". Before this patch, we always generated an if (true) for the default transition of a variant scheduling class. Example (taken from AArch64GenSubtargetInfo.inc) : ``` if (SchedModel->getProcessorID() == 3) { // CycloneModel if ((TII->isScaledAddr(*MI))) return 927; // (WriteIS_WriteLD)_ReadBaseRS if ((true)) return 928; // WriteLD_ReadDefault } ``` Extra parentheses were also generated around the predicate expressions. With this patch, we get the following auto-generated checks: ``` if (SchedModel->getProcessorID() == 3) { // CycloneModel if (TII->isScaledAddr(*MI)) return 927; // (WriteIS_WriteLD)_ReadBaseRS return 928; // WriteLD_ReadDefault } ``` The new auto-generated code behaves exactly the same as before. So, technically this is a non functional change. Differential revision: https://reviews.llvm.org/D50566 llvm-svn: 339552
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