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| author | Daniel Cederman <cederman@gaisler.com> | 2018-08-13 10:49:48 +0000 |
|---|---|---|
| committer | Daniel Cederman <cederman@gaisler.com> | 2018-08-13 10:49:48 +0000 |
| commit | 1bfbc62022290f282aef2765c5878ad82a4a4c46 (patch) | |
| tree | 87424e3fefa457fe9bd69de3356acf650dce1a47 /llvm/lib/CodeGen/CodeGenPrepare.cpp | |
| parent | c1ef96f593adc6bcf4f63ceeb5d0748e757d15ee (diff) | |
| download | bcm5719-llvm-1bfbc62022290f282aef2765c5878ad82a4a4c46.tar.gz bcm5719-llvm-1bfbc62022290f282aef2765c5878ad82a4a4c46.zip | |
[Sparc] Add support for the cycle counter available in GR740
Summary: The GR740 provides an up cycle counter in the
registers ASR22 and ASR23. As these registers can not be
read together atomically we only use the value of ASR23
for llvm.readcyclecounter(). The ASR23 register holds the
32 LSBs of the up-counter.
Reviewers: jyknight, venkatra
Reviewed By: jyknight
Subscribers: fedor.sergeev, jrtc27, llvm-commits
Differential Revision: https://reviews.llvm.org/D48638
llvm-svn: 339551
Diffstat (limited to 'llvm/lib/CodeGen/CodeGenPrepare.cpp')
0 files changed, 0 insertions, 0 deletions
