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authorToma Tabacu <toma.tabacu@imgtec.com>2015-03-17 13:17:44 +0000
committerToma Tabacu <toma.tabacu@imgtec.com>2015-03-17 13:17:44 +0000
commitdcebf5b901972005dccbe0854fb3203a6bfdae6e (patch)
tree24f002f66940a1db9d36f9cb97550bd077f5d946 /llvm/lib/CodeGen/AsmPrinter/Win64Exception.cpp
parent51067848e79da93c231a0c47f517541858d4be2d (diff)
downloadbcm5719-llvm-dcebf5b901972005dccbe0854fb3203a6bfdae6e.tar.gz
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[mips] [IAS] Add support for the XOR $reg,imm pseudo-instruction.
Summary: This adds a MipsInstAlias which expands to XORi $reg,$reg,imm. For example, "xor $6, 0x3A" should be expanded to "xori $6, $6, 58". This should work for all MIPS ISAs. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8284 llvm-svn: 232473
Diffstat (limited to 'llvm/lib/CodeGen/AsmPrinter/Win64Exception.cpp')
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