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authorToma Tabacu <toma.tabacu@imgtec.com>2015-03-17 13:17:44 +0000
committerToma Tabacu <toma.tabacu@imgtec.com>2015-03-17 13:17:44 +0000
commitdcebf5b901972005dccbe0854fb3203a6bfdae6e (patch)
tree24f002f66940a1db9d36f9cb97550bd077f5d946
parent51067848e79da93c231a0c47f517541858d4be2d (diff)
downloadbcm5719-llvm-dcebf5b901972005dccbe0854fb3203a6bfdae6e.tar.gz
bcm5719-llvm-dcebf5b901972005dccbe0854fb3203a6bfdae6e.zip
[mips] [IAS] Add support for the XOR $reg,imm pseudo-instruction.
Summary: This adds a MipsInstAlias which expands to XORi $reg,$reg,imm. For example, "xor $6, 0x3A" should be expanded to "xori $6, $6, 58". This should work for all MIPS ISAs. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8284 llvm-svn: 232473
-rw-r--r--llvm/lib/Target/Mips/MipsInstrInfo.td2
-rw-r--r--llvm/test/MC/Mips/mips1/valid.s1
-rw-r--r--llvm/test/MC/Mips/mips2/valid.s1
-rw-r--r--llvm/test/MC/Mips/mips3/valid.s1
-rw-r--r--llvm/test/MC/Mips/mips32/valid.s1
-rw-r--r--llvm/test/MC/Mips/mips32r2/valid.s1
-rw-r--r--llvm/test/MC/Mips/mips32r3/valid.s1
-rw-r--r--llvm/test/MC/Mips/mips32r5/valid.s1
-rw-r--r--llvm/test/MC/Mips/mips32r6/valid.s1
-rw-r--r--llvm/test/MC/Mips/mips4/valid.s1
-rw-r--r--llvm/test/MC/Mips/mips5/valid.s1
-rw-r--r--llvm/test/MC/Mips/mips64/valid.s1
-rw-r--r--llvm/test/MC/Mips/mips64r2/valid.s1
-rw-r--r--llvm/test/MC/Mips/mips64r3/valid.s1
-rw-r--r--llvm/test/MC/Mips/mips64r5/valid.s1
-rw-r--r--llvm/test/MC/Mips/mips64r6/valid.s1
16 files changed, 17 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td
index e543641ceaa..be1815d0519 100644
--- a/llvm/lib/Target/Mips/MipsInstrInfo.td
+++ b/llvm/lib/Target/Mips/MipsInstrInfo.td
@@ -1580,6 +1580,8 @@ def : MipsInstAlias<"sltu $rt, $rs, $imm",
(SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>;
def : MipsInstAlias<"xor $rs, $rt, $imm",
(XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
+def : MipsInstAlias<"xor $rs, $imm",
+ (XORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
def : MipsInstAlias<"or $rs, $rt, $imm",
(ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
def : MipsInstAlias<"or $rs, $imm",
diff --git a/llvm/test/MC/Mips/mips1/valid.s b/llvm/test/MC/Mips/mips1/valid.s
index 53ff6a0740a..d18f6f5780b 100644
--- a/llvm/test/MC/Mips/mips1/valid.s
+++ b/llvm/test/MC/Mips/mips1/valid.s
@@ -116,3 +116,4 @@
tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
xor $s2,$a0,$s8
+ xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
diff --git a/llvm/test/MC/Mips/mips2/valid.s b/llvm/test/MC/Mips/mips2/valid.s
index 34843bc9f77..6ee65122207 100644
--- a/llvm/test/MC/Mips/mips2/valid.s
+++ b/llvm/test/MC/Mips/mips2/valid.s
@@ -165,3 +165,4 @@
trunc.w.d $f22,$f15
trunc.w.s $f28,$f30
xor $s2,$a0,$s8
+ xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
diff --git a/llvm/test/MC/Mips/mips3/valid.s b/llvm/test/MC/Mips/mips3/valid.s
index a55576d9e67..6d55079f93f 100644
--- a/llvm/test/MC/Mips/mips3/valid.s
+++ b/llvm/test/MC/Mips/mips3/valid.s
@@ -228,3 +228,4 @@
trunc.w.d $f22,$f15
trunc.w.s $f28,$f30
xor $s2,$a0,$s8
+ xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
diff --git a/llvm/test/MC/Mips/mips32/valid.s b/llvm/test/MC/Mips/mips32/valid.s
index d79c390c47e..ba75d77e746 100644
--- a/llvm/test/MC/Mips/mips32/valid.s
+++ b/llvm/test/MC/Mips/mips32/valid.s
@@ -195,3 +195,4 @@
trunc.w.d $f22,$f15
trunc.w.s $f28,$f30
xor $s2,$a0,$s8
+ xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
diff --git a/llvm/test/MC/Mips/mips32r2/valid.s b/llvm/test/MC/Mips/mips32r2/valid.s
index 97cfa36e712..61be290d0b8 100644
--- a/llvm/test/MC/Mips/mips32r2/valid.s
+++ b/llvm/test/MC/Mips/mips32r2/valid.s
@@ -233,4 +233,5 @@
trunc.w.s $f28,$f30
wsbh $k1,$9
xor $s2,$a0,$s8
+ xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e]
diff --git a/llvm/test/MC/Mips/mips32r3/valid.s b/llvm/test/MC/Mips/mips32r3/valid.s
index 4280de59939..ff6589d951f 100644
--- a/llvm/test/MC/Mips/mips32r3/valid.s
+++ b/llvm/test/MC/Mips/mips32r3/valid.s
@@ -233,4 +233,5 @@
trunc.w.s $f28,$f30
wsbh $k1,$9
xor $s2,$a0,$s8
+ xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e]
diff --git a/llvm/test/MC/Mips/mips32r5/valid.s b/llvm/test/MC/Mips/mips32r5/valid.s
index 13341d5016e..408d0cc5afb 100644
--- a/llvm/test/MC/Mips/mips32r5/valid.s
+++ b/llvm/test/MC/Mips/mips32r5/valid.s
@@ -233,4 +233,5 @@
trunc.w.s $f28,$f30
wsbh $k1,$9
xor $s2,$a0,$s8
+ xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e]
diff --git a/llvm/test/MC/Mips/mips32r6/valid.s b/llvm/test/MC/Mips/mips32r6/valid.s
index 362785ba7ef..7033d4abbe5 100644
--- a/llvm/test/MC/Mips/mips32r6/valid.s
+++ b/llvm/test/MC/Mips/mips32r6/valid.s
@@ -175,3 +175,4 @@
tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33]
tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
+ xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
diff --git a/llvm/test/MC/Mips/mips4/valid.s b/llvm/test/MC/Mips/mips4/valid.s
index fc747a58ce8..7fcf781713d 100644
--- a/llvm/test/MC/Mips/mips4/valid.s
+++ b/llvm/test/MC/Mips/mips4/valid.s
@@ -257,3 +257,4 @@
trunc.w.d $f22,$f15
trunc.w.s $f28,$f30
xor $s2,$a0,$s8
+ xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
diff --git a/llvm/test/MC/Mips/mips5/valid.s b/llvm/test/MC/Mips/mips5/valid.s
index 995d1a52a06..4b1282e30f7 100644
--- a/llvm/test/MC/Mips/mips5/valid.s
+++ b/llvm/test/MC/Mips/mips5/valid.s
@@ -259,3 +259,4 @@
trunc.w.d $f22,$f15
trunc.w.s $f28,$f30
xor $s2,$a0,$s8
+ xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
diff --git a/llvm/test/MC/Mips/mips64/valid.s b/llvm/test/MC/Mips/mips64/valid.s
index f481a28eeed..d900ab7428a 100644
--- a/llvm/test/MC/Mips/mips64/valid.s
+++ b/llvm/test/MC/Mips/mips64/valid.s
@@ -276,3 +276,4 @@
trunc.w.d $f22,$f15
trunc.w.s $f28,$f30
xor $s2,$a0,$s8
+ xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
diff --git a/llvm/test/MC/Mips/mips64r2/valid.s b/llvm/test/MC/Mips/mips64r2/valid.s
index 77172380bdf..719345126b8 100644
--- a/llvm/test/MC/Mips/mips64r2/valid.s
+++ b/llvm/test/MC/Mips/mips64r2/valid.s
@@ -302,4 +302,5 @@
trunc.w.d $f22,$f15
trunc.w.s $f28,$f30
xor $s2,$a0,$s8
+ xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
wsbh $k1,$9
diff --git a/llvm/test/MC/Mips/mips64r3/valid.s b/llvm/test/MC/Mips/mips64r3/valid.s
index d8f1721754c..3a3f7adfad1 100644
--- a/llvm/test/MC/Mips/mips64r3/valid.s
+++ b/llvm/test/MC/Mips/mips64r3/valid.s
@@ -302,4 +302,5 @@
trunc.w.d $f22,$f15
trunc.w.s $f28,$f30
xor $s2,$a0,$s8
+ xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
wsbh $k1,$9
diff --git a/llvm/test/MC/Mips/mips64r5/valid.s b/llvm/test/MC/Mips/mips64r5/valid.s
index 17068526cd8..5ba102d253d 100644
--- a/llvm/test/MC/Mips/mips64r5/valid.s
+++ b/llvm/test/MC/Mips/mips64r5/valid.s
@@ -302,4 +302,5 @@
trunc.w.d $f22,$f15
trunc.w.s $f28,$f30
xor $s2,$a0,$s8
+ xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
wsbh $k1,$9
diff --git a/llvm/test/MC/Mips/mips64r6/valid.s b/llvm/test/MC/Mips/mips64r6/valid.s
index 3e8fc415626..600cb4813dc 100644
--- a/llvm/test/MC/Mips/mips64r6/valid.s
+++ b/llvm/test/MC/Mips/mips64r6/valid.s
@@ -198,3 +198,4 @@
tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33]
tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
+ xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
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