summaryrefslogtreecommitdiffstats
path: root/llvm/include
diff options
context:
space:
mode:
authorVolkan Keles <vkeles@apple.com>2017-03-07 18:03:28 +0000
committerVolkan Keles <vkeles@apple.com>2017-03-07 18:03:28 +0000
commit20d3c4200d6151fc10f78e996b36ef078b4be75d (patch)
tree33f1313e5f2fc0d62279b3580dc6f12280e922f0 /llvm/include
parent654975b5a643b304f1db133950471b1b55325d6d (diff)
downloadbcm5719-llvm-20d3c4200d6151fc10f78e996b36ef078b4be75d.tar.gz
bcm5719-llvm-20d3c4200d6151fc10f78e996b36ef078b4be75d.zip
[GlobalISel] Translate floating-point negation
Reviewers: qcolombet, javed.absar, aditya_nandakumar, dsanders, t.p.northover, ab Reviewed By: qcolombet Subscribers: dberris, rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30671 llvm-svn: 297171
Diffstat (limited to 'llvm/include')
-rw-r--r--llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h5
-rw-r--r--llvm/include/llvm/Target/GenericOpcodes.td6
-rw-r--r--llvm/include/llvm/Target/TargetOpcodes.def3
3 files changed, 11 insertions, 3 deletions
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h b/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
index 52c39231508..74b0c8d63fd 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
@@ -206,6 +206,8 @@ private:
/// \pre \p U is a return instruction.
bool translateRet(const User &U, MachineIRBuilder &MIRBuilder);
+ bool translateFSub(const User &U, MachineIRBuilder &MIRBuilder);
+
bool translateAdd(const User &U, MachineIRBuilder &MIRBuilder) {
return translateBinaryOp(TargetOpcode::G_ADD, U, MIRBuilder);
}
@@ -288,9 +290,6 @@ private:
bool translateFAdd(const User &U, MachineIRBuilder &MIRBuilder) {
return translateBinaryOp(TargetOpcode::G_FADD, U, MIRBuilder);
}
- bool translateFSub(const User &U, MachineIRBuilder &MIRBuilder) {
- return translateBinaryOp(TargetOpcode::G_FSUB, U, MIRBuilder);
- }
bool translateFMul(const User &U, MachineIRBuilder &MIRBuilder) {
return translateBinaryOp(TargetOpcode::G_FMUL, U, MIRBuilder);
}
diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td
index 766f8a2488b..cb0ab8d7e95 100644
--- a/llvm/include/llvm/Target/GenericOpcodes.td
+++ b/llvm/include/llvm/Target/GenericOpcodes.td
@@ -316,6 +316,12 @@ def G_SMULH : Instruction {
// Floating Point Unary Ops.
//------------------------------------------------------------------------------
+def G_FNEG : Instruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src);
+ let hasSideEffects = 0;
+}
+
def G_FPEXT : Instruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$src);
diff --git a/llvm/include/llvm/Target/TargetOpcodes.def b/llvm/include/llvm/Target/TargetOpcodes.def
index 6f450cdb62e..a39fa3f7739 100644
--- a/llvm/include/llvm/Target/TargetOpcodes.def
+++ b/llvm/include/llvm/Target/TargetOpcodes.def
@@ -364,6 +364,9 @@ HANDLE_TARGET_OPCODE(G_FREM)
/// Generic FP exponentiation.
HANDLE_TARGET_OPCODE(G_FPOW)
+/// Generic FP negation.
+HANDLE_TARGET_OPCODE(G_FNEG)
+
/// Generic FP extension.
HANDLE_TARGET_OPCODE(G_FPEXT)
OpenPOWER on IntegriCloud