diff options
| -rw-r--r-- | llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h | 5 | ||||
| -rw-r--r-- | llvm/include/llvm/Target/GenericOpcodes.td | 6 | ||||
| -rw-r--r-- | llvm/include/llvm/Target/TargetOpcodes.def | 3 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 12 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll | 18 |
5 files changed, 41 insertions, 3 deletions
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h b/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h index 52c39231508..74b0c8d63fd 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h @@ -206,6 +206,8 @@ private: /// \pre \p U is a return instruction. bool translateRet(const User &U, MachineIRBuilder &MIRBuilder); + bool translateFSub(const User &U, MachineIRBuilder &MIRBuilder); + bool translateAdd(const User &U, MachineIRBuilder &MIRBuilder) { return translateBinaryOp(TargetOpcode::G_ADD, U, MIRBuilder); } @@ -288,9 +290,6 @@ private: bool translateFAdd(const User &U, MachineIRBuilder &MIRBuilder) { return translateBinaryOp(TargetOpcode::G_FADD, U, MIRBuilder); } - bool translateFSub(const User &U, MachineIRBuilder &MIRBuilder) { - return translateBinaryOp(TargetOpcode::G_FSUB, U, MIRBuilder); - } bool translateFMul(const User &U, MachineIRBuilder &MIRBuilder) { return translateBinaryOp(TargetOpcode::G_FMUL, U, MIRBuilder); } diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td index 766f8a2488b..cb0ab8d7e95 100644 --- a/llvm/include/llvm/Target/GenericOpcodes.td +++ b/llvm/include/llvm/Target/GenericOpcodes.td @@ -316,6 +316,12 @@ def G_SMULH : Instruction { // Floating Point Unary Ops. //------------------------------------------------------------------------------ +def G_FNEG : Instruction { + let OutOperandList = (outs type0:$dst); + let InOperandList = (ins type0:$src); + let hasSideEffects = 0; +} + def G_FPEXT : Instruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type1:$src); diff --git a/llvm/include/llvm/Target/TargetOpcodes.def b/llvm/include/llvm/Target/TargetOpcodes.def index 6f450cdb62e..a39fa3f7739 100644 --- a/llvm/include/llvm/Target/TargetOpcodes.def +++ b/llvm/include/llvm/Target/TargetOpcodes.def @@ -364,6 +364,9 @@ HANDLE_TARGET_OPCODE(G_FREM) /// Generic FP exponentiation. HANDLE_TARGET_OPCODE(G_FPOW) +/// Generic FP negation. +HANDLE_TARGET_OPCODE(G_FNEG) + /// Generic FP extension. HANDLE_TARGET_OPCODE(G_FPEXT) diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index 0470b3af7f5..70333057a76 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -171,6 +171,18 @@ bool IRTranslator::translateBinaryOp(unsigned Opcode, const User &U, return true; } +bool IRTranslator::translateFSub(const User &U, MachineIRBuilder &MIRBuilder) { + // -0.0 - X --> G_FNEG + if (isa<Constant>(U.getOperand(0)) && + U.getOperand(0) == ConstantFP::getZeroValueForNegation(U.getType())) { + MIRBuilder.buildInstr(TargetOpcode::G_FNEG) + .addDef(getOrCreateVReg(U)) + .addUse(getOrCreateVReg(*U.getOperand(1))); + return true; + } + return translateBinaryOp(TargetOpcode::G_FSUB, U, MIRBuilder); +} + bool IRTranslator::translateCompare(const User &U, MachineIRBuilder &MIRBuilder) { const CmpInst *CI = dyn_cast<CmpInst>(&U); diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll index 65a1422c360..7539ceef451 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll @@ -1209,3 +1209,21 @@ define void @test_load_store_atomics(i8* %addr) { ret void } + +define float @test_fneg_f32(float %x) { +; CHECK-LABEL: name: test_fneg_f32 +; CHECK: [[ARG:%[0-9]+]](s32) = COPY %s0 +; CHECK: [[RES:%[0-9]+]](s32) = G_FNEG [[ARG]] +; CHECK: %s0 = COPY [[RES]](s32) + %neg = fsub float -0.000000e+00, %x + ret float %neg +} + +define double @test_fneg_f64(double %x) { +; CHECK-LABEL: name: test_fneg_f64 +; CHECK: [[ARG:%[0-9]+]](s64) = COPY %d0 +; CHECK: [[RES:%[0-9]+]](s64) = G_FNEG [[ARG]] +; CHECK: %d0 = COPY [[RES]](s64) + %neg = fsub double -0.000000e+00, %x + ret double %neg +} |
