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| author | Roman Lebedev <lebedev.ri@gmail.com> | 2019-10-20 20:52:06 +0000 |
|---|---|---|
| committer | Roman Lebedev <lebedev.ri@gmail.com> | 2019-10-20 20:52:06 +0000 |
| commit | 7015a5c54b53d8d2297a3aa38bc32aab167bdcfc (patch) | |
| tree | d1f8a01d1cb0f0bd83f059db0574c5b6c0df9b1b /lldb/packages/Python/lldbsuite/test/python_api/frame/TestFrames.py | |
| parent | f7aec25d4fb193c2efb5c8bdcecd6d0611183bcc (diff) | |
| download | bcm5719-llvm-7015a5c54b53d8d2297a3aa38bc32aab167bdcfc.tar.gz bcm5719-llvm-7015a5c54b53d8d2297a3aa38bc32aab167bdcfc.zip | |
[InstCombine] conditional sign-extend of high-bit-extract: 'or' pattern.
In this pattern, all the "magic" bits that we'd `add` are all
high sign bits, and in the value we'd be adding to they are all unset,
not unexpectedly, so we can have an `or` there:
https://rise4fun.com/Alive/ups
It is possible that `haveNoCommonBitsSet()` should be taught about this
pattern so that we never have an `add` variant, but the reasoning would
need to be recursive (because of that `select`), so i'm not really sure
that would be worth it just yet.
llvm-svn: 375378
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/python_api/frame/TestFrames.py')
0 files changed, 0 insertions, 0 deletions
