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authorCraig Topper <craig.topper@intel.com>2018-02-26 02:16:33 +0000
committerCraig Topper <craig.topper@intel.com>2018-02-26 02:16:33 +0000
commit2bf8e3e0e191bd434b867133d0ee093eec63edfb (patch)
treeb95ac185dcb44cca0ecbe8ea7e44a33a020494d1 /lldb/packages/Python/lldbsuite/test/expression_command/macros/TestMacros.py
parent79d189f5970e43cac372403cdf329d6ba04e6bf1 (diff)
downloadbcm5719-llvm-2bf8e3e0e191bd434b867133d0ee093eec63edfb.tar.gz
bcm5719-llvm-2bf8e3e0e191bd434b867133d0ee093eec63edfb.zip
[X86] Simplify the ReplaceNodeResults code for X86ISD::AVG.
This code seemed to try to widen to 128, 256, or 512 bit vectors, but we only create X86ISD::AVG with a power of 2 number of elements. This means the only nodes that need to be legalized are less than 128-bits and need to be widened up to 128 bits. llvm-svn: 326064
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/expression_command/macros/TestMacros.py')
0 files changed, 0 insertions, 0 deletions
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