diff options
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 20 |
1 files changed, 7 insertions, 13 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index f2a88ef6f5c..e1fc9a2d514 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -24828,19 +24828,13 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N, assert(Subtarget.hasSSE2() && "Requires at least SSE2!"); auto InVT = N->getValueType(0); - auto InVTSize = InVT.getSizeInBits(); - const unsigned RegSize = - (InVTSize > 128) ? ((InVTSize > 256) ? 512 : 256) : 128; - assert((Subtarget.hasBWI() || RegSize < 512) && - "512-bit vector requires AVX512BW"); - assert((Subtarget.hasAVX2() || RegSize < 256) && - "256-bit vector requires AVX2"); - - auto ElemVT = InVT.getVectorElementType(); - auto RegVT = EVT::getVectorVT(*DAG.getContext(), ElemVT, - RegSize / ElemVT.getSizeInBits()); - assert(RegSize % InVT.getSizeInBits() == 0); - unsigned NumConcat = RegSize / InVT.getSizeInBits(); + assert(InVT.getSizeInBits() < 128); + assert(128 % InVT.getSizeInBits() == 0); + unsigned NumConcat = 128 / InVT.getSizeInBits(); + + EVT RegVT = EVT::getVectorVT(*DAG.getContext(), + InVT.getVectorElementType(), + NumConcat * InVT.getVectorNumElements()); SmallVector<SDValue, 16> Ops(NumConcat, DAG.getUNDEF(InVT)); Ops[0] = N->getOperand(0); |
