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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2015-02-04 14:25:47 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2015-02-04 14:25:47 +0000 |
| commit | aa748a8db551be46ea6a24b288b7972bcbd52068 (patch) | |
| tree | 03589a5fe0acaef72ae2c91d46d6d3c59b397f4c /clang/test | |
| parent | 34c325e74994ad8d5ea5e265243a82e8dad2e2fc (diff) | |
| download | bcm5719-llvm-aa748a8db551be46ea6a24b288b7972bcbd52068.tar.gz bcm5719-llvm-aa748a8db551be46ea6a24b288b7972bcbd52068.zip | |
Preserve early clobber flag when using named registers in inline assembly.
Summary:
Named registers with the constraint "=&r" currently lose the early clobber flag
and turn into "=r" when converted to LLVM-IR. This patch correctly passes it on.
Reviewers: atanasyan
Reviewed By: atanasyan
Subscribers: cfe-commits
Differential Revision: http://reviews.llvm.org/D7346
llvm-svn: 228143
Diffstat (limited to 'clang/test')
| -rw-r--r-- | clang/test/CodeGen/arm-asm-variable.c | 2 | ||||
| -rw-r--r-- | clang/test/CodeGen/asm-reg-var-local.c | 24 |
2 files changed, 25 insertions, 1 deletions
diff --git a/clang/test/CodeGen/arm-asm-variable.c b/clang/test/CodeGen/arm-asm-variable.c index f874269b0a0..6868cb7996a 100644 --- a/clang/test/CodeGen/arm-asm-variable.c +++ b/clang/test/CodeGen/arm-asm-variable.c @@ -17,7 +17,7 @@ int64_t foo(int64_t v, volatile int64_t *p) : [_rl] "=&r" (rl), [_rh] "=&r" (rh) \ : [_p] "p" (p) : "memory"); - // CHECK: call { i32, i32 } asm sideeffect "ldrexd$0, $1, [$2]", "={r1},={r2},r,~{memory}"(i64* + // CHECK: call { i32, i32 } asm sideeffect "ldrexd$0, $1, [$2]", "=&{r1},=&{r2},r,~{memory}"(i64* return r; } diff --git a/clang/test/CodeGen/asm-reg-var-local.c b/clang/test/CodeGen/asm-reg-var-local.c index 9060e120ffc..44417d4a76b 100644 --- a/clang/test/CodeGen/asm-reg-var-local.c +++ b/clang/test/CodeGen/asm-reg-var-local.c @@ -2,6 +2,7 @@ // Exercise various use cases for local asm "register variables". int foo() { +// CHECK-LABEL: define i32 @foo() // CHECK: [[A:%[a-zA-Z0-9]+]] = alloca i32 register int a asm("rsi")=5; @@ -22,3 +23,26 @@ int foo() { // CHECK: [[TMP1:%[a-zA-Z0-9]+]] = load i32* [[A]] // CHECK: ret i32 [[TMP1]] } + +int earlyclobber() { +// CHECK-LABEL: define i32 @earlyclobber() +// CHECK: [[A:%[a-zA-Z0-9]+]] = alloca i32 + + register int a asm("rsi")=5; +// CHECK: store i32 5, i32* [[A]] + + asm volatile("; %0 This asm defines rsi" : "=&r"(a)); +// CHECK: [[Z:%[a-zA-Z0-9]+]] = call i32 asm sideeffect "; $0 This asm defines rsi", "=&{rsi},~{dirflag},~{fpsr},~{flags}"() +// CHECK: store i32 [[Z]], i32* [[A]] + + a = 42; +// CHECK: store i32 42, i32* [[A]] + + asm volatile("; %0 This asm uses rsi" : : "r"(a)); +// CHECK: [[TMP:%[a-zA-Z0-9]+]] = load i32* [[A]] +// CHECK: call void asm sideeffect "; $0 This asm uses rsi", "{rsi},~{dirflag},~{fpsr},~{flags}"(i32 [[TMP]]) + + return a; +// CHECK: [[TMP1:%[a-zA-Z0-9]+]] = load i32* [[A]] +// CHECK: ret i32 [[TMP1]] +} |
