Preserve early clobber flag when using named registers in inline assembly.

Summary:
Named registers with the constraint "=&r" currently lose the early clobber flag
and turn into "=r" when converted to LLVM-IR. This patch correctly passes it on.

Reviewers: atanasyan

Reviewed By: atanasyan

Subscribers: cfe-commits

Differential Revision: http://reviews.llvm.org/D7346

llvm-svn: 228143

3 files changed, 30 insertions, 5 deletions

diff --git a/clang/lib/CodeGen/CGStmt.cpp b/clang/lib/CodeGen/CGStmt.cpp
index 0d41055bf7e..8e1c7f2d197 100644
--- a/clang/lib/CodeGen/CGStmt.cpp
+++ b/clang/lib/CodeGen/CGStmt.cpp
@@ -1696,7 +1696,7 @@ SimplifyConstraint(const char *Constraint, const TargetInfo &Target,
 static std::string
 AddVariableConstraints(const std::string &Constraint, const Expr &AsmExpr,
                        const TargetInfo &Target, CodeGenModule &CGM,
-                       const AsmStmt &Stmt) {
+                       const AsmStmt &Stmt, const bool EarlyClobber) {
   const DeclRefExpr *AsmDeclRef = dyn_cast<DeclRefExpr>(&AsmExpr);
   if (!AsmDeclRef)
     return Constraint;
@@ -1721,7 +1721,7 @@ AddVariableConstraints(const std::string &Constraint, const Expr &AsmExpr,
   }
   // Canonicalize the register here before returning it.
   Register = Target.getNormalizedGCCRegisterName(Register);
-  return "{" + Register.str() + "}";
+  return (EarlyClobber ? "&{" : "{") + Register.str() + "}";
 }
 
 llvm::Value*
@@ -1854,7 +1854,8 @@ void CodeGenFunction::EmitAsmStmt(const AsmStmt &S) {
     OutExpr = OutExpr->IgnoreParenNoopCasts(getContext());
 
     OutputConstraint = AddVariableConstraints(OutputConstraint, *OutExpr,
-                                              getTarget(), CGM, S);
+                                              getTarget(), CGM, S,
+                                              Info.earlyClobber());
 
     LValue Dest = EmitLValue(OutExpr);
     if (!Constraints.empty())
@@ -1959,7 +1960,7 @@ void CodeGenFunction::EmitAsmStmt(const AsmStmt &S) {
     InputConstraint =
       AddVariableConstraints(InputConstraint,
                             *InputExpr->IgnoreParenNoopCasts(getContext()),
-                            getTarget(), CGM, S);
+                            getTarget(), CGM, S, Info.earlyClobber());
 
     llvm::Value *Arg = EmitAsmInput(Info, InputExpr, Constraints);
 
diff --git a/clang/test/CodeGen/arm-asm-variable.c b/clang/test/CodeGen/arm-asm-variable.c
index f874269b0a0..6868cb7996a 100644
--- a/clang/test/CodeGen/arm-asm-variable.c
+++ b/clang/test/CodeGen/arm-asm-variable.c
@@ -17,7 +17,7 @@ int64_t foo(int64_t v, volatile int64_t *p)
 		       : [_rl] "=&r" (rl), [_rh] "=&r" (rh)		\
 		       : [_p] "p" (p) : "memory");
 
-  // CHECK: call { i32, i32 } asm sideeffect "ldrexd$0, $1, [$2]", "={r1},={r2},r,~{memory}"(i64*
+  // CHECK: call { i32, i32 } asm sideeffect "ldrexd$0, $1, [$2]", "=&{r1},=&{r2},r,~{memory}"(i64*
 
   return r;
 }
diff --git a/clang/test/CodeGen/asm-reg-var-local.c b/clang/test/CodeGen/asm-reg-var-local.c
index 9060e120ffc..44417d4a76b 100644
--- a/clang/test/CodeGen/asm-reg-var-local.c
+++ b/clang/test/CodeGen/asm-reg-var-local.c
@@ -2,6 +2,7 @@
 // Exercise various use cases for local asm "register variables".
 
 int foo() {
+// CHECK-LABEL: define i32 @foo()
 // CHECK: [[A:%[a-zA-Z0-9]+]] = alloca i32
 
   register int a asm("rsi")=5;
@@ -22,3 +23,26 @@ int foo() {
 // CHECK:  [[TMP1:%[a-zA-Z0-9]+]] = load i32* [[A]]
 // CHECK:  ret i32 [[TMP1]]
 }
+
+int earlyclobber() {
+// CHECK-LABEL: define i32 @earlyclobber()
+// CHECK: [[A:%[a-zA-Z0-9]+]] = alloca i32
+
+  register int a asm("rsi")=5;
+// CHECK: store i32 5, i32* [[A]]
+
+  asm volatile("; %0 This asm defines rsi" : "=&r"(a));
+// CHECK: [[Z:%[a-zA-Z0-9]+]] = call i32 asm sideeffect "; $0 This asm defines rsi", "=&{rsi},~{dirflag},~{fpsr},~{flags}"()
+// CHECK: store i32 [[Z]], i32* [[A]]
+
+  a = 42;
+// CHECK:  store i32 42, i32* [[A]]
+
+  asm volatile("; %0 This asm uses rsi" : : "r"(a));
+// CHECK:  [[TMP:%[a-zA-Z0-9]+]] = load i32* [[A]]
+// CHECK:  call void asm sideeffect "; $0 This asm uses rsi", "{rsi},~{dirflag},~{fpsr},~{flags}"(i32 [[TMP]])
+
+  return a;
+// CHECK:  [[TMP1:%[a-zA-Z0-9]+]] = load i32* [[A]]
+// CHECK:  ret i32 [[TMP1]]
+}