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authorSander de Smalen <sander.desmalen@arm.com>2018-04-12 11:40:52 +0000
committerSander de Smalen <sander.desmalen@arm.com>2018-04-12 11:40:52 +0000
commit650234ba36b57a782e844f05f18e2ec58b18c6b7 (patch)
tree045f0ffe7523475b6b57cfd167c189b5446d5e12 /clang/lib/Frontend/CompilerInvocation.cpp
parentb48b027d05eb28a868ffda436c4409b6b606a0cc (diff)
downloadbcm5719-llvm-650234ba36b57a782e844f05f18e2ec58b18c6b7.tar.gz
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[AArch64][AsmParser] Make parse function for VectorLists generic to other vector types.
Summary: Added 'RegisterKind' to the VectorListOp structure, so that this operand type can be reused for SVE vector lists in a later patch. It also refactors the 'tryParseVectorList' function so it can be used directly in the ParserMethod of an operand. The parsing can now parse multiple kinds of vectors and recover if there is no match. This is patch [3/6] in a series to add assembler/disassembler support for SVE's contiguous ST1 (scalar+imm) instructions. Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro Reviewed By: rengolin Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D45429 llvm-svn: 329900
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