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| author | Craig Topper <craig.topper@intel.com> | 2019-03-18 20:43:15 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-03-18 20:43:15 +0000 |
| commit | f086e562f940b76e2a9f0bff37391a721071d8ca (patch) | |
| tree | 1171ecaadc414af50a253971a23e6ca8f960c608 | |
| parent | 0b9c640fe079642cb44a902189ebbfeedc6a27cc (diff) | |
| download | bcm5719-llvm-f086e562f940b76e2a9f0bff37391a721071d8ca.tar.gz bcm5719-llvm-f086e562f940b76e2a9f0bff37391a721071d8ca.zip | |
[X86] Use relocImm in the ROL8ri/ROL16ri/ROL32ri/ROL64ri patterns to be consistent with the ROR patterns.
llvm-svn: 356407
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrShiftRotate.td | 10 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/absolute-rotate.ll | 16 |
2 files changed, 22 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86InstrShiftRotate.td b/llvm/lib/Target/X86/X86InstrShiftRotate.td index 5c4507440ed..633b7099af6 100644 --- a/llvm/lib/Target/X86/X86InstrShiftRotate.td +++ b/llvm/lib/Target/X86/X86InstrShiftRotate.td @@ -472,17 +472,19 @@ def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src1), def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2), "rol{b}\t{$src2, $dst|$dst, $src2}", - [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>; + [(set GR8:$dst, (rotl GR8:$src1, (i8 relocImm:$src2)))]>; def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2), "rol{w}\t{$src2, $dst|$dst, $src2}", - [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize16; + [(set GR16:$dst, (rotl GR16:$src1, (i8 relocImm:$src2)))]>, + OpSize16; def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2), "rol{l}\t{$src2, $dst|$dst, $src2}", - [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>, OpSize32; + [(set GR32:$dst, (rotl GR32:$src1, (i8 relocImm:$src2)))]>, + OpSize32; def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst), (ins GR64:$src1, u8imm:$src2), "rol{q}\t{$src2, $dst|$dst, $src2}", - [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>; + [(set GR64:$dst, (rotl GR64:$src1, (i8 relocImm:$src2)))]>; // Rotate by 1 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1), diff --git a/llvm/test/CodeGen/X86/absolute-rotate.ll b/llvm/test/CodeGen/X86/absolute-rotate.ll index 6240e8d3f76..c7b165d38c2 100644 --- a/llvm/test/CodeGen/X86/absolute-rotate.ll +++ b/llvm/test/CodeGen/X86/absolute-rotate.ll @@ -24,4 +24,20 @@ f: ret void } +define void @bar(i64 %val) { + %shr = shl i64 %val, zext (i8 ptrtoint (i8* @align to i8) to i64) + %shl = lshr i64 %val, zext (i8 sub (i8 64, i8 ptrtoint (i8* @align to i8)) to i64) + ; CHECK: rolq $align@ABS8, %rdi + %rol = or i64 %shr, %shl + %cmp = icmp ult i64 %rol, 109 + br i1 %cmp, label %t, label %f + +t: + call void @f() + ret void + +f: + ret void +} + !0 = !{i64 0, i64 128} |
