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| author | Craig Topper <craig.topper@intel.com> | 2019-03-18 20:43:09 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-03-18 20:43:09 +0000 |
| commit | 0b9c640fe079642cb44a902189ebbfeedc6a27cc (patch) | |
| tree | 5790ecfbfa14585e7e2e9079950c27adf53d77df | |
| parent | efb4f9e568bfa91c422738abae63afead55c5a70 (diff) | |
| download | bcm5719-llvm-0b9c640fe079642cb44a902189ebbfeedc6a27cc.tar.gz bcm5719-llvm-0b9c640fe079642cb44a902189ebbfeedc6a27cc.zip | |
[X86] Replace uses of i64immSExt32_su with i64relocImmSExt32_su.
For the i8, i16, and i32 instructions we were using a relocImm. Presumably we should for i64 as well.
llvm-svn: 356406
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrArithmetic.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrCompiler.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrInfo.td | 5 |
3 files changed, 2 insertions, 7 deletions
diff --git a/llvm/lib/Target/X86/X86InstrArithmetic.td b/llvm/lib/Target/X86/X86InstrArithmetic.td index 5bb0fdafe3e..cf27e6826e8 100644 --- a/llvm/lib/Target/X86/X86InstrArithmetic.td +++ b/llvm/lib/Target/X86/X86InstrArithmetic.td @@ -611,7 +611,7 @@ def Xi32 : X86TypeInfo<i32, "l", GR32, loadi32, i32mem, Imm32, i32imm, relocImm32_su, i32i8imm, i32immSExt8_su, 1, OpSize32, 0>; def Xi64 : X86TypeInfo<i64, "q", GR64, loadi64, i64mem, - Imm32S, i64i32imm, i64immSExt32_su, i64i8imm, i64immSExt8_su, + Imm32S, i64i32imm, i64relocImmSExt32_su, i64i8imm, i64immSExt8_su, 1, OpSizeFixed, 1>; /// ITy - This instruction base class takes the type info for the instruction. diff --git a/llvm/lib/Target/X86/X86InstrCompiler.td b/llvm/lib/Target/X86/X86InstrCompiler.td index 44f2ac48d3c..e7a0383a254 100644 --- a/llvm/lib/Target/X86/X86InstrCompiler.td +++ b/llvm/lib/Target/X86/X86InstrCompiler.td @@ -1995,8 +1995,6 @@ def : Pat<(X86sub_flag 0, GR64:$src), (NEG64r GR64:$src)>; // sub reg, relocImm def : Pat<(X86sub_flag GR64:$src1, i64relocImmSExt8_su:$src2), (SUB64ri8 GR64:$src1, i64relocImmSExt8_su:$src2)>; -def : Pat<(X86sub_flag GR64:$src1, i64relocImmSExt32_su:$src2), - (SUB64ri32 GR64:$src1, i64relocImmSExt32_su:$src2)>; // mul reg, reg def : Pat<(mul GR16:$src1, GR16:$src2), diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td index 5bf3008d937..64d1c2f2452 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.td +++ b/llvm/lib/Target/X86/X86InstrInfo.td @@ -993,9 +993,6 @@ def relocImm16_su : PatLeaf<(i16 relocImm), [{ def relocImm32_su : PatLeaf<(i32 relocImm), [{ return !shouldAvoidImmediateInstFormsForSize(N); }]>; -def i64immSExt32_su : PatLeaf<(i64immSExt32), [{ - return !shouldAvoidImmediateInstFormsForSize(N); -}]>; def i16immSExt8_su : PatLeaf<(i16immSExt8), [{ return !shouldAvoidImmediateInstFormsForSize(N); @@ -1503,7 +1500,7 @@ def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src), [(store (i32 relocImm32_su:$src), addr:$dst)]>, OpSize32; def MOV64mi32 : RIi32S<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src), "mov{q}\t{$src, $dst|$dst, $src}", - [(store i64immSExt32_su:$src, addr:$dst)]>, + [(store i64relocImmSExt32_su:$src, addr:$dst)]>, Requires<[In64BitMode]>; } // SchedRW |
